From nobody Fri Dec 19 04:05:00 2025 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9955D2101A0; Fri, 10 Jan 2025 09:22:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736500947; cv=none; b=ayEH+QgAHaR3KQ1/HS+KoTzW3R59aJMxb8W7BFuSwaL/7TnmVC6qh/rzaE8TGnuhp/FuvdMOYg3mBtyq2Z813i5mkujHS67+nm+idauol13/wEvE37xD4Wc1DgLmsjQ522NWSoeOUXemm7Jun6eqTq/O/lWyT8SN2vdliflQ1Gc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736500947; c=relaxed/simple; bh=WezfflLED2Of8XPWwxpZAd0T7zFSgMc8vNQIDUVuikM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=sODZZOMAlbGLC0U3mE0ccihDxN+vcpo9bM/3fzn1QOXWHq2HCB5qSYuvir70uOCUYyb8GWpggExv0+4JTxXW2wNaODSQZMmB5W956v2natGqXtCdurdpjFOVsuoLQrs2Zp+1omwmWXzkzPtnjioNCojGXJBMxdLAkGmohfBDRnE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=4TusN0TF; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="4TusN0TF" Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 50A48Abs006343; Fri, 10 Jan 2025 10:22:14 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= 4B2L1h8/Ga92df8AG9HXGme/BlFA+G//Iy0I6fG3Wps=; b=4TusN0TFKFxZVSzx bnMV9k0sV0GK2Iu5YYMwghnplI42VceTYplQOtOek16scy/PGMiNf/dhJ4GPcvBV qHrx8OPHjCou6vsyqbmJVXWd0Wbe8eraMVIiNX4vxXA5aZ7NlvuLRkzA7rMJ9GWb Bq/8QK3vLodYZLlxUHVgrGY0b+RphvEAI2PaVumPwYe/jzXVfqkh9AMjc9BwEJfa 2MU4qmye1evFAhqpVAiIkBTQs2MWrg2vDCD7JNyqRTjbQd9Iff71aEx/otm04gfz jRqlgpTi8dCztDE7I3C5hqPN6yjX+IlL1UvNX+SP5ZOsoCWB7bX9cCciaYmlLRwM qEnI6Q== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 442hnxay4s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Jan 2025 10:22:13 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 52A3640061; Fri, 10 Jan 2025 10:21:06 +0100 (CET) Received: from Webmail-eu.st.com (eqndag1node5.st.com [10.75.129.134]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 91C05289F18; Fri, 10 Jan 2025 10:20:04 +0100 (CET) Received: from SAFDAG1NODE1.st.com (10.75.90.17) by EQNDAG1NODE5.st.com (10.75.129.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Fri, 10 Jan 2025 10:20:04 +0100 Received: from localhost (10.252.28.64) by SAFDAG1NODE1.st.com (10.75.90.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Fri, 10 Jan 2025 10:20:04 +0100 From: Fabrice Gasnier To: , , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 6/8] arm64: dts: st: add timer nodes on stm32mp251 Date: Fri, 10 Jan 2025 10:19:20 +0100 Message-ID: <20250110091922.980627-7-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250110091922.980627-1-fabrice.gasnier@foss.st.com> References: <20250110091922.980627-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SAFDAG1NODE1.st.com (10.75.90.17) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Type: text/plain; charset="utf-8" Add timers support on STM32MP25 SoC. Use dedicated compatible to handle new features and instances introduced with this SoC. STM32MP25 SoC has various timer flavours, each group has its own specific feature list: - Advanced-control timers (TIM1/TIM8/TIM20) - General-purpose timers (TIM2/TIM3/TIM4/TIM5) - Basic timers (TIM6/TIM7) - General-purpose timers (TIM10/TIM11/TIM12/TIM13/TIM14) - General purpose timers (TIM15/TIM16/TIM17) Signed-off-by: Fabrice Gasnier --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 524 +++++++++++++++++++++++++ 1 file changed, 524 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 6fe12e3bd7dd..220fb1a3da71 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -237,6 +237,273 @@ rifsc: bus@42080000 { #access-controller-cells =3D <1>; ranges; =20 + timers2: timer@40000000 { + compatible =3D "st,stm32mp25-timers"; + reg =3D <0x40000000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc CK_KER_TIM2>; + clock-names =3D "int"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 1>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-timer-counter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@1 { + compatible =3D "st,stm32mp25-timer-trigger"; + reg =3D <1>; + status =3D "disabled"; + }; + }; + + timers3: timer@40010000 { + compatible =3D "st,stm32mp25-timers"; + reg =3D <0x40010000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc CK_KER_TIM3>; + clock-names =3D "int"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 2>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-timer-counter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@2 { + compatible =3D "st,stm32mp25-timer-trigger"; + reg =3D <2>; + status =3D "disabled"; + }; + }; + + timers4: timer@40020000 { + compatible =3D "st,stm32mp25-timers"; + reg =3D <0x40020000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc CK_KER_TIM4>; + clock-names =3D "int"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 3>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-timer-counter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@3 { + compatible =3D "st,stm32mp25-timer-trigger"; + reg =3D <3>; + status =3D "disabled"; + }; + }; + + timers5: timer@40030000 { + compatible =3D "st,stm32mp25-timers"; + reg =3D <0x40030000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc CK_KER_TIM5>; + clock-names =3D "int"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 4>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-timer-counter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@4 { + compatible =3D "st,stm32mp25-timer-trigger"; + reg =3D <4>; + status =3D "disabled"; + }; + }; + + timers6: timer@40040000 { + compatible =3D "st,stm32mp25-timers"; + reg =3D <0x40040000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc CK_KER_TIM6>; + clock-names =3D "int"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 5>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-timer-counter"; + status =3D "disabled"; + }; + + timer@5 { + compatible =3D "st,stm32mp25-timer-trigger"; + reg =3D <5>; + status =3D "disabled"; + }; + }; + + timers7: timer@40050000 { + compatible =3D "st,stm32mp25-timers"; + reg =3D <0x40050000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc CK_KER_TIM7>; + clock-names =3D "int"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 6>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-timer-counter"; + status =3D "disabled"; + }; + + timer@6 { + compatible =3D "st,stm32mp25-timer-trigger"; + reg =3D <6>; + status =3D "disabled"; + }; + }; + + timers12: timer@40060000 { + compatible =3D "st,stm32mp25-timers"; + reg =3D <0x40060000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc CK_KER_TIM12>; + clock-names =3D "int"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 10>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-timer-counter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@11 { + compatible =3D "st,stm32mp25-timer-trigger"; + reg =3D <11>; + status =3D "disabled"; + }; + }; + + timers13: timer@40070000 { + compatible =3D "st,stm32mp25-timers"; + reg =3D <0x40070000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc CK_KER_TIM13>; + clock-names =3D "int"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 11>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-timer-counter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@12 { + compatible =3D "st,stm32mp25-timer-trigger"; + reg =3D <12>; + status =3D "disabled"; + }; + }; + + timers14: timer@40080000 { + compatible =3D "st,stm32mp25-timers"; + reg =3D <0x40080000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc CK_KER_TIM14>; + clock-names =3D "int"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 12>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-timer-counter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@13 { + compatible =3D "st,stm32mp25-timer-trigger"; + reg =3D <13>; + status =3D "disabled"; + }; + }; + spi2: spi@400b0000 { #address-cells =3D <1>; #size-cells =3D <0>; @@ -427,6 +694,136 @@ i2c7: i2c@40180000 { status =3D "disabled"; }; =20 + timers10: timer@401c0000 { + compatible =3D "st,stm32mp25-timers"; + reg =3D <0x401c0000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc CK_KER_TIM10>; + clock-names =3D "int"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 8>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-timer-counter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@9 { + compatible =3D "st,stm32mp25-timer-trigger"; + reg =3D <9>; + status =3D "disabled"; + }; + }; + + timers11: timer@401d0000 { + compatible =3D "st,stm32mp25-timers"; + reg =3D <0x401d0000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc CK_KER_TIM11>; + clock-names =3D "int"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 9>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-timer-counter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@10 { + compatible =3D "st,stm32mp25-timer-trigger"; + reg =3D <10>; + status =3D "disabled"; + }; + }; + + timers1: timer@40200000 { + compatible =3D "st,stm32mp25-timers"; + reg =3D <0x40200000 0x400>; + interrupts =3D , + , + , + ; + interrupt-names =3D "brk", "up", "trg-com", "cc"; + clocks =3D <&rcc CK_KER_TIM1>; + clock-names =3D "int"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 0>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-timer-counter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@0 { + compatible =3D "st,stm32mp25-timer-trigger"; + reg =3D <0>; + status =3D "disabled"; + }; + }; + + timers8: timer@40210000 { + compatible =3D "st,stm32mp25-timers"; + reg =3D <0x40210000 0x400>; + interrupts =3D , + , + , + ; + interrupt-names =3D "brk", "up", "trg-com", "cc"; + clocks =3D <&rcc CK_KER_TIM8>; + clock-names =3D "int"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 7>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-timer-counter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@7 { + compatible =3D "st,stm32mp25-timer-trigger"; + reg =3D <7>; + status =3D "disabled"; + }; + }; + usart6: serial@40220000 { compatible =3D "st,stm32h7-uart"; reg =3D <0x40220000 0x400>; @@ -469,6 +866,99 @@ spi4: spi@40240000 { status =3D "disabled"; }; =20 + timers15: timer@40250000 { + compatible =3D "st,stm32mp25-timers"; + reg =3D <0x40250000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc CK_KER_TIM15>; + clock-names =3D "int"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 13>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-timer-counter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@14 { + compatible =3D "st,stm32mp25-timer-trigger"; + reg =3D <14>; + status =3D "disabled"; + }; + }; + + timers16: timer@40260000 { + compatible =3D "st,stm32mp25-timers"; + reg =3D <0x40260000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc CK_KER_TIM16>; + clock-names =3D "int"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 14>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-timer-counter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@15 { + compatible =3D "st,stm32mp25-timer-trigger"; + reg =3D <15>; + status =3D "disabled"; + }; + }; + + timers17: timer@40270000 { + compatible =3D "st,stm32mp25-timers"; + reg =3D <0x40270000 0x400>; + interrupts =3D ; + interrupt-names =3D "global"; + clocks =3D <&rcc CK_KER_TIM17>; + clock-names =3D "int"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 15>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-timer-counter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@16 { + compatible =3D "st,stm32mp25-timer-trigger"; + reg =3D <16>; + status =3D "disabled"; + }; + }; + spi5: spi@40280000 { #address-cells =3D <1>; #size-cells =3D <0>; @@ -496,6 +986,40 @@ uart9: serial@402c0000 { status =3D "disabled"; }; =20 + timers20: timer@40320000 { + compatible =3D "st,stm32mp25-timers"; + reg =3D <0x40320000 0x400>; + interrupts =3D , + , + , + ; + interrupt-names =3D "brk", "up", "trg-com", "cc"; + clocks =3D <&rcc CK_KER_TIM20>; + clock-names =3D "int"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 16>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-timer-counter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer@19 { + compatible =3D "st,stm32mp25-timer-trigger"; + reg =3D <19>; + status =3D "disabled"; + }; + }; + usart1: serial@40330000 { compatible =3D "st,stm32h7-uart"; reg =3D <0x40330000 0x400>; --=20 2.25.1