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Fri, 10 Jan 2025 07:21:26 -0800 (PST) From: Neil Armstrong Date: Fri, 10 Jan 2025 16:21:20 +0100 Subject: [PATCH 3/4] arm64: dts: qcom: sm8650: add cpu interconnect nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250110-topic-sm8650-ddr-bw-scaling-v1-3-041d836b084c@linaro.org> References: <20250110-topic-sm8650-ddr-bw-scaling-v1-0-041d836b084c@linaro.org> In-Reply-To: <20250110-topic-sm8650-ddr-bw-scaling-v1-0-041d836b084c@linaro.org> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4643; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=d+GjSlfsiPtSREFcW4TugBdSP8ZalkWtqO1Bjmm9SpI=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBngTryq4Bh+HB/bbJLSHlqQw/GCyFv95Uv2hzD4Thd cx5ejUyJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ4E68gAKCRB33NvayMhJ0ZGJD/ 0WbtOCLd1Zon0ZVlw2QyaM+yLmR4VHsX4VfA23zhC2tjQjJHOz4g32E0EJyxyYy/diTYQ7LQRhIlBf /EaiW0lvV9lfhFsDKDYOYadDWKe2Psldsr/jaNe7GZPh+s3W16qH0EiC3GFxrkIrIbG+nl/NVfNmNl FjB7pZyTSB0It2eyLtBIp5IL2e0kv01vUBFXKwrXtohIUUQWj6WtFP6a3DB54WibOU6pltDLnnZTuw 5X/lV6WGpz0rdyS0bF8mmn1Nxz/CYmQYuLYFJg1UPKH+C8sR/zuqrMFoqSHACT9mkBSh0ml3ZfB6kx xQ9pqXgwRjKLtPWOT7SRP84bllAFJUNJWhwV16CaeIypHWQRfG3DBMdVGfP9ov/usucyt4ECKvVlTH cxbHjfEcwbcGK7Hhx4ZqnTWO5m844jRKR3YaR3ZVKEpVrmlmTW+NtAL1Rwr+57EIldjP+z3ZHje3/Q 4z94wh3TB0sVbO85a8bxiCyiofYtZxG+d/HXeyFPJU/C7f4YbZIcbjuXRO57YdjJWS53lfj4MudLjK ScwsBb54My48JXJzZG55lMc5554+OULKTm+nHky5lhzdxhEIpIeRk+m/DoO61FdD/HMWL/nRF9SCY/ 4kstLym/Zc2QFUEKdbiC3hWraKVB9f6vico1YaBpAmTQGSg+870tG3o3rz3A== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add the interconnect entry for each cpu, with 3 different paths: - CPU to Last Level Cache Controller (LLCC) - Last Level Cache Controller (LLCC) to DDR - L3 Cache from CPU to DDR interface Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 57 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index bc09e879c1440873a52daf3fc7a38f451f1f972c..e194a95cdcc0f0f692e62b94233= 1cd9e07a4eae0 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -85,6 +86,13 @@ cpu0: cpu@0 { =20 qcom,freq-domain =3D <&cpufreq_hw 0>; =20 + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; =20 l2_0: l2-cache { @@ -118,6 +126,13 @@ cpu1: cpu@100 { =20 qcom,freq-domain =3D <&cpufreq_hw 0>; =20 + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; }; =20 @@ -138,6 +153,13 @@ cpu2: cpu@200 { =20 qcom,freq-domain =3D <&cpufreq_hw 3>; =20 + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; =20 l2_200: l2-cache { @@ -165,6 +187,13 @@ cpu3: cpu@300 { =20 qcom,freq-domain =3D <&cpufreq_hw 3>; =20 + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; }; =20 @@ -185,6 +214,13 @@ cpu4: cpu@400 { =20 qcom,freq-domain =3D <&cpufreq_hw 3>; =20 + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; =20 l2_400: l2-cache { @@ -212,6 +248,13 @@ cpu5: cpu@500 { =20 qcom,freq-domain =3D <&cpufreq_hw 1>; =20 + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; =20 l2_500: l2-cache { @@ -239,6 +282,13 @@ cpu6: cpu@600 { =20 qcom,freq-domain =3D <&cpufreq_hw 1>; =20 + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; =20 l2_600: l2-cache { @@ -266,6 +316,13 @@ cpu7: cpu@700 { =20 qcom,freq-domain =3D <&cpufreq_hw 2>; =20 + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; =20 l2_700: l2-cache { --=20 2.34.1