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Fri, 10 Jan 2025 05:39:55 +0000 (UTC) From: Ao Xu via B4 Relay Date: Fri, 10 Jan 2025 13:39:51 +0800 Subject: [PATCH 01/11] dt-bindings: display: meson-dw-hdmi: Add compatible for S4 HDMI controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250110-drm-s4-v1-1-cbc2d5edaae8@amlogic.com> References: <20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com> In-Reply-To: <20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com> To: Neil Armstrong , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ao Xu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1736487593; l=876; i=ao.xu@amlogic.com; s=20250103; h=from:subject:message-id; bh=/06xHmC2myfGLoM8tpTANbPOABYZF56wo8NJNiKgZ5A=; b=J74TFdNjfeuf4xmz4NKNLHVau7fIMmNSUihqIqgeyFjm92lB/udlEzM3roEpMg+hkQ+N4X7s8 UeGx5QN1XU3Di8eU0SCdOogQj+QOImkjRWWthXzpVE0fDQoU6NLI3e7 X-Developer-Key: i=ao.xu@amlogic.com; a=ed25519; pk=c0TSXrwQuL4EhPVf3lJ676U27ax2yfFTqmRoseP/fA8= X-Endpoint-Received: by B4 Relay for ao.xu@amlogic.com/20250103 with auth_id=308 X-Original-From: Ao Xu Reply-To: ao.xu@amlogic.com From: Ao Xu Add devicetree document for S4 HDMI controller Signed-off-by: Ao Xu --- Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdm= i.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.ya= ml index 84d68b8cfccc86fd87a6a0fd2b70af12e51eb8a4..6e0a8369eee915fab55af24d450= a6c40e08def38 100644 --- a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml @@ -55,6 +55,7 @@ properties: - const: amlogic,meson-gx-dw-hdmi - enum: - amlogic,meson-g12a-dw-hdmi # G12A (S905X2, S905Y2, S905D2) + - amlogic,meson-s4-dw-hdmi # S4 (S905Y4) =20 reg: maxItems: 1 --=20 2.43.0 From nobody Sun Feb 8 15:46:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08F78290F; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250110-drm-s4-v1-2-cbc2d5edaae8@amlogic.com> References: <20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com> In-Reply-To: <20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com> To: Neil Armstrong , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ao Xu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1736487593; l=2203; i=ao.xu@amlogic.com; s=20250103; h=from:subject:message-id; bh=7+BtboC52S07wz4NFzmNC6kZHvkpp2eBKVt3C4Xqx5Y=; b=CfujSyzUv9OLLfUTtlU/ZasbtyNhObfGZZzeJqGPSuymCtEYkqty8iYTDGqEc3XrrmliBV6r1 pypNDhmrAXdCOb1JDhpEygzsZ+uDPnUt6CnWrJ0A1eycBeCoOwfv2gV X-Developer-Key: i=ao.xu@amlogic.com; a=ed25519; pk=c0TSXrwQuL4EhPVf3lJ676U27ax2yfFTqmRoseP/fA8= X-Endpoint-Received: by B4 Relay for ao.xu@amlogic.com/20250103 with auth_id=308 X-Original-From: Ao Xu Reply-To: ao.xu@amlogic.com From: Ao Xu Add devicetree document for S4 VPU Signed-off-by: Ao Xu --- .../bindings/display/amlogic,meson-vpu.yaml | 48 ++++++++++++++++++= ++-- 1 file changed, 44 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.ya= ml b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml index cb0a90f0232190031430c08f936b8f0d3b217601..3d7eceb3724e81d9c911039507d= f072d332a028f 100644 --- a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml +++ b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml @@ -66,14 +66,13 @@ properties: - const: amlogic,meson-gx-vpu - enum: - amlogic,meson-g12a-vpu # G12A (S905X2, S905Y2, S905D2) + - amlogic,meson-s4-vpu # S4 (S905Y4) =20 reg: - maxItems: 2 + minItems: 2 =20 reg-names: - items: - - const: vpu - - const: hhi + minItems: 2 =20 interrupts: maxItems: 1 @@ -117,6 +116,47 @@ required: - "#size-cells" - amlogic,canvas =20 +allOf: + - if: + properties: + compatible: + contains: + const: amlogic,meson-s4-vpu + then: + properties: + reg: + items: + - description: vcbus registers + - description: hhi registers + - description: clkctrl registers + - description: power control registers + - description: sysctrl registers + reg-names: + items: + - const: vpu + - const: hhi + - const: clkctrl + - const: pwctrl + - const: sysctrl + clocks: + items: + - description: vpu clock + - description: vapb clock + clock-names: + items: + - const: vpu + - const: vapb + else: + properties: + reg: + items: + - description: vcbus registers + - description: hhi registers + reg-names: + items: + - const: vpu + - const: hhi + additionalProperties: false =20 examples: --=20 2.43.0 From nobody Sun Feb 8 15:46:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31A112063FC; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250110-drm-s4-v1-3-cbc2d5edaae8@amlogic.com> References: <20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com> In-Reply-To: <20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com> To: Neil Armstrong , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ao Xu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1736487593; l=7142; i=ao.xu@amlogic.com; s=20250103; h=from:subject:message-id; bh=GnKCqq83/fUtrB77EhTpFJy/e7nbJHAdb/ugnZdZD1A=; b=ftzCIj0t4Ah/uuU+STje9qCx7QjfYryE18vx0j8JMqoHoNjILg/kCpeXf165b3RwDRDvTm1vY w9049UIPZznDF4WD4aaKsliIfnyYyFNn1ZYzHiDfSDu+HPmb/3AH8O3 X-Developer-Key: i=ao.xu@amlogic.com; a=ed25519; pk=c0TSXrwQuL4EhPVf3lJ676U27ax2yfFTqmRoseP/fA8= X-Endpoint-Received: by B4 Relay for ao.xu@amlogic.com/20250103 with auth_id=308 X-Original-From: Ao Xu Reply-To: ao.xu@amlogic.com From: Ao Xu Add S4 compatible for DRM driver. This update driver logic to support S4-specific configurations. This also add vpu clock operation in bind, suspend, resume, shutdown stage. Signed-off-by: Ao Xu --- drivers/gpu/drm/meson/meson_drv.c | 127 ++++++++++++++++++++++++++++++++++= +++- drivers/gpu/drm/meson/meson_drv.h | 6 ++ 2 files changed, 132 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meso= n_drv.c index 81d2ee37e7732dca89d02347b9c972300b38771a..d28094efeb137ae0b9990ab3608= 825d563358dba 100644 --- a/drivers/gpu/drm/meson/meson_drv.c +++ b/drivers/gpu/drm/meson/meson_drv.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -160,6 +161,34 @@ static void meson_vpu_init(struct meson_drm *priv) writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1)); } =20 +static void meson_setup_clk(struct meson_drm *priv, bool enable) +{ + int ret; + + if (!priv || !priv->vpu_clk || !priv->vapb_clk) + return; + + if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) + return; + + if (enable) { + ret =3D clk_prepare_enable(priv->vpu_clk); + if (ret) { + dev_err(priv->dev, "Failed to set vpu clk\n"); + return; + } + ret =3D clk_prepare_enable(priv->vapb_clk); + if (ret) { + dev_err(priv->dev, "Failed to Set vapb clk\n"); + clk_disable_unprepare(priv->vpu_clk); + return; + } + } else { + clk_disable_unprepare(priv->vpu_clk); + clk_disable_unprepare(priv->vapb_clk); + } +} + struct meson_drm_soc_attr { struct meson_drm_soc_limits limits; const struct soc_device_attribute *attrs; @@ -241,6 +270,83 @@ static int meson_drv_bind_master(struct device *dev, b= ool has_components) goto free_drm; } =20 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "sysctrl"); + if (!res) { + ret =3D -EINVAL; + goto free_drm; + } + /* Simply ioremap since it may be a shared register zone */ + regs =3D devm_ioremap(dev, res->start, resource_size(res)); + if (!regs) { + ret =3D -EADDRNOTAVAIL; + goto free_drm; + } + + priv->sysctrl =3D devm_regmap_init_mmio(dev, regs, + &meson_regmap_config); + if (IS_ERR(priv->sysctrl)) { + dev_err(&pdev->dev, "Couldn't create the SYSCTRL regmap\n"); + ret =3D PTR_ERR(priv->sysctrl); + goto free_drm; + } + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "clkctrl"); + if (!res) { + ret =3D -EINVAL; + goto free_drm; + } + /* Simply ioremap since it may be a shared register zone */ + regs =3D devm_ioremap(dev, res->start, resource_size(res)); + if (!regs) { + ret =3D -EADDRNOTAVAIL; + goto free_drm; + } + + priv->clkctrl =3D devm_regmap_init_mmio(dev, regs, + &meson_regmap_config); + if (IS_ERR(priv->clkctrl)) { + dev_err(&pdev->dev, "Couldn't create the clkctrl regmap\n"); + ret =3D PTR_ERR(priv->clkctrl); + goto free_drm; + } + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrctrl"); + if (!res) { + ret =3D -EINVAL; + goto free_drm; + } + /* Simply ioremap since it may be a shared register zone */ + regs =3D devm_ioremap(dev, res->start, resource_size(res)); + if (!regs) { + ret =3D -EADDRNOTAVAIL; + goto free_drm; + } + + priv->pwrctrl =3D devm_regmap_init_mmio(dev, regs, + &meson_regmap_config); + if (IS_ERR(priv->pwrctrl)) { + dev_err(&pdev->dev, "Couldn't create the pwrctrl regmap\n"); + ret =3D PTR_ERR(priv->pwrctrl); + goto free_drm; + } + + priv->vpu_clk =3D devm_clk_get(&pdev->dev, "vpu"); + if (IS_ERR(priv->vpu_clk)) { + dev_err(&pdev->dev, "vpu clock request failed\n"); + ret =3D PTR_ERR(priv->vpu_clk); + goto free_drm; + } + + priv->vapb_clk =3D devm_clk_get(&pdev->dev, "vapb"); + if (IS_ERR(priv->vapb_clk)) { + dev_err(&pdev->dev, "vapb clock request failed\n"); + ret =3D PTR_ERR(priv->vapb_clk); + goto free_drm; + } + meson_setup_clk(priv, true); + } + priv->canvas =3D meson_canvas_get(dev); if (IS_ERR(priv->canvas)) { ret =3D PTR_ERR(priv->canvas); @@ -424,12 +530,21 @@ static const struct component_master_ops meson_drv_ma= ster_ops =3D { =20 static int __maybe_unused meson_drv_pm_suspend(struct device *dev) { + int ret; struct meson_drm *priv =3D dev_get_drvdata(dev); =20 if (!priv) return 0; =20 - return drm_mode_config_helper_suspend(priv->drm); + ret =3D drm_mode_config_helper_suspend(priv->drm); + if (unlikely(ret)) { + drm_err(dev, "suspend error: %d", ret); + return ret; + } + + meson_setup_clk(priv, false); + + return ret; } =20 static int __maybe_unused meson_drv_pm_resume(struct device *dev) @@ -439,6 +554,7 @@ static int __maybe_unused meson_drv_pm_resume(struct de= vice *dev) if (!priv) return 0; =20 + meson_setup_clk(priv, true); meson_vpu_init(priv); meson_venc_init(priv); meson_vpp_init(priv); @@ -458,6 +574,7 @@ static void meson_drv_shutdown(struct platform_device *= pdev) =20 drm_kms_helper_poll_fini(priv->drm); drm_atomic_helper_shutdown(priv->drm); + meson_setup_clk(priv, false); } =20 /* @@ -471,6 +588,7 @@ static const struct of_device_id components_dev_match[]= =3D { { .compatible =3D "amlogic,meson-gxl-dw-hdmi" }, { .compatible =3D "amlogic,meson-gxm-dw-hdmi" }, { .compatible =3D "amlogic,meson-g12a-dw-hdmi" }, + { .compatible =3D "amlogic,meson-s4-dw-hdmi" }, {} }; =20 @@ -539,6 +657,11 @@ static struct meson_drm_match_data meson_drm_g12a_data= =3D { .afbcd_ops =3D &meson_afbcd_g12a_ops, }; =20 +static struct meson_drm_match_data meson_drm_s4_data =3D { + .compat =3D VPU_COMPATIBLE_S4, + .afbcd_ops =3D &meson_afbcd_g12a_ops, +}; + static const struct of_device_id dt_match[] =3D { { .compatible =3D "amlogic,meson-gxbb-vpu", .data =3D (void *)&meson_drm_gxbb_data }, @@ -548,6 +671,8 @@ static const struct of_device_id dt_match[] =3D { .data =3D (void *)&meson_drm_gxm_data }, { .compatible =3D "amlogic,meson-g12a-vpu", .data =3D (void *)&meson_drm_g12a_data }, + { .compatible =3D "amlogic,meson-s4-vpu", + .data =3D (void *)&meson_drm_s4_data }, {} }; MODULE_DEVICE_TABLE(of, dt_match); diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meso= n_drv.h index 3f9345c14f31c13b071f420533fe8a450d3e0f36..c801a2e3e55a054247710aebae5= 602e44c9e1624 100644 --- a/drivers/gpu/drm/meson/meson_drv.h +++ b/drivers/gpu/drm/meson/meson_drv.h @@ -22,6 +22,7 @@ enum vpu_compatible { VPU_COMPATIBLE_GXL =3D 1, VPU_COMPATIBLE_GXM =3D 2, VPU_COMPATIBLE_G12A =3D 3, + VPU_COMPATIBLE_S4 =3D 4, }; =20 enum { @@ -45,6 +46,11 @@ struct meson_drm { enum vpu_compatible compat; void __iomem *io_base; struct regmap *hhi; + struct regmap *sysctrl; + struct regmap *clkctrl; + struct regmap *pwrctrl; + struct clk *vpu_clk; + struct clk *vapb_clk; int vsync_irq; =20 struct meson_canvas *canvas; --=20 2.43.0 From nobody Sun Feb 8 15:46:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31AB62066C0; Fri, 10 Jan 2025 05:39:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736487596; cv=none; b=sPcN+vHF3gNKISr31/o7jHhJEn8XrkcO6YoUd6nRcz82gjjDOXTDhHrnfYwdvOhXDkDi38YhkwQ365ojkjUMWf2HODvoHsOJ8IdlxflypuuQ+n3A7vsi6QvrJgLNA0jkOHCuuXwvLNj9lEH4wngjJVzqmHKamnC9hLrRdOyKR3c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736487596; c=relaxed/simple; bh=CP9UbudAqwoBvCWySj8azYf9NNwJceXOZUXEJzaPRD4=; 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Fri, 10 Jan 2025 05:39:55 +0000 (UTC) From: Ao Xu via B4 Relay Date: Fri, 10 Jan 2025 13:39:54 +0800 Subject: [PATCH 04/11] drm: meson: add primary and overlay plane support for S4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250110-drm-s4-v1-4-cbc2d5edaae8@amlogic.com> References: <20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com> In-Reply-To: <20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com> To: Neil Armstrong , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ao Xu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1736487593; l=11576; i=ao.xu@amlogic.com; s=20250103; h=from:subject:message-id; bh=4U1UBMlyjt5Zc6sAX/P7YN/CLGBHy2Chyz1U7fL/wAw=; b=KfM82SwD5kqsto6e4i+22SDcOHT4uufvChBuyIrcem90+gp3VyFgl4516CcugzEfx4VNoMC9Z J5aZ9P2h/heBbry2eb5t0V+YNjSMsfDsE6JRTUH91fbxxDc+R7nYKP/ X-Developer-Key: i=ao.xu@amlogic.com; a=ed25519; pk=c0TSXrwQuL4EhPVf3lJ676U27ax2yfFTqmRoseP/fA8= X-Endpoint-Received: by B4 Relay for ao.xu@amlogic.com/20250103 with auth_id=308 X-Original-From: Ao Xu Reply-To: ao.xu@amlogic.com From: Ao Xu Update plane register configurations in the Meson DRM driver to support the Amlogic S4 SoC. These adjustments ensure proper handling of display planes with S4-specific hardware requirements. Signed-off-by: Ao Xu --- drivers/gpu/drm/meson/meson_crtc.c | 90 +++++++++++++++++++++++------= ---- drivers/gpu/drm/meson/meson_overlay.c | 7 ++- drivers/gpu/drm/meson/meson_plane.c | 24 ++++++--- drivers/gpu/drm/meson/meson_registers.h | 16 ++++++ 4 files changed, 102 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/mes= on_crtc.c index d70616da8ce2fd974b57af6aadca5c98fbb88fce..64c7450b7f688d8997e8ad23947= bff3ec6484aff 100644 --- a/drivers/gpu/drm/meson/meson_crtc.c +++ b/drivers/gpu/drm/meson/meson_crtc.c @@ -28,6 +28,7 @@ #include "meson_osd_afbcd.h" =20 #define MESON_G12A_VIU_OFFSET 0x5ec0 +#define MESON_S4_VIU_OFFSET 0xb6c0 =20 /* CRTC definition */ =20 @@ -479,21 +480,60 @@ void meson_crtc_irq(struct meson_drm *priv) writel_relaxed(priv->viu.vd1_if0_gen_reg, priv->io_base + meson_crtc->viu_offset + _REG(VD2_IF0_GEN_REG)); - writel_relaxed(priv->viu.vd1_if0_gen_reg2, - priv->io_base + meson_crtc->viu_offset + - _REG(VD1_IF0_GEN_REG2)); - writel_relaxed(priv->viu.viu_vd1_fmt_ctrl, - priv->io_base + meson_crtc->viu_offset + - _REG(VIU_VD1_FMT_CTRL)); - writel_relaxed(priv->viu.viu_vd1_fmt_ctrl, - priv->io_base + meson_crtc->viu_offset + - _REG(VIU_VD2_FMT_CTRL)); - writel_relaxed(priv->viu.viu_vd1_fmt_w, - priv->io_base + meson_crtc->viu_offset + - _REG(VIU_VD1_FMT_W)); - writel_relaxed(priv->viu.viu_vd1_fmt_w, - priv->io_base + meson_crtc->viu_offset + - _REG(VIU_VD2_FMT_W)); + + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { + writel_relaxed(priv->viu.vd1_if0_gen_reg2, + priv->io_base + + _REG(VD1_IF0_GEN_REG2_S4)); + writel_relaxed(priv->viu.viu_vd1_fmt_ctrl, + priv->io_base + + _REG(VIU_VD1_FMT_CTRL_S4)); + writel_relaxed(priv->viu.viu_vd1_fmt_ctrl, + priv->io_base + + _REG(VIU_VD2_FMT_CTRL_S4)); + writel_relaxed(priv->viu.viu_vd1_fmt_w, + priv->io_base + + _REG(VIU_VD1_FMT_W_S4)); + writel_relaxed(priv->viu.viu_vd1_fmt_w, + priv->io_base + + _REG(VIU_VD2_FMT_W_S4)); + + writel_relaxed(priv->viu.vd1_range_map_y, + priv->io_base + + _REG(VD1_IF0_RANGE_MAP_Y_S4)); + writel_relaxed(priv->viu.vd1_range_map_cb, + priv->io_base + + _REG(VD1_IF0_RANGE_MAP_CB_S4)); + writel_relaxed(priv->viu.vd1_range_map_cr, + priv->io_base + + _REG(VD1_IF0_RANGE_MAP_CR_S4)); + } else { + writel_relaxed(priv->viu.vd1_if0_gen_reg2, + priv->io_base + meson_crtc->viu_offset + + _REG(VD1_IF0_GEN_REG2)); + writel_relaxed(priv->viu.viu_vd1_fmt_ctrl, + priv->io_base + meson_crtc->viu_offset + + _REG(VIU_VD1_FMT_CTRL)); + writel_relaxed(priv->viu.viu_vd1_fmt_ctrl, + priv->io_base + meson_crtc->viu_offset + + _REG(VIU_VD2_FMT_CTRL)); + writel_relaxed(priv->viu.viu_vd1_fmt_w, + priv->io_base + meson_crtc->viu_offset + + _REG(VIU_VD1_FMT_W)); + writel_relaxed(priv->viu.viu_vd1_fmt_w, + priv->io_base + meson_crtc->viu_offset + + _REG(VIU_VD2_FMT_W)); + + writel_relaxed(priv->viu.vd1_range_map_y, + priv->io_base + meson_crtc->viu_offset + + _REG(VD1_IF0_RANGE_MAP_Y)); + writel_relaxed(priv->viu.vd1_range_map_cb, + priv->io_base + meson_crtc->viu_offset + + _REG(VD1_IF0_RANGE_MAP_CB)); + writel_relaxed(priv->viu.vd1_range_map_cr, + priv->io_base + meson_crtc->viu_offset + + _REG(VD1_IF0_RANGE_MAP_CR)); + } writel_relaxed(priv->viu.vd1_if0_canvas0, priv->io_base + meson_crtc->viu_offset + _REG(VD1_IF0_CANVAS0)); @@ -592,15 +632,7 @@ void meson_crtc_irq(struct meson_drm *priv) _REG(VD2_IF0_LUMA_PSEL)); writel_relaxed(0, priv->io_base + meson_crtc->viu_offset + _REG(VD2_IF0_CHROMA_PSEL)); - writel_relaxed(priv->viu.vd1_range_map_y, - priv->io_base + meson_crtc->viu_offset + - _REG(VD1_IF0_RANGE_MAP_Y)); - writel_relaxed(priv->viu.vd1_range_map_cb, - priv->io_base + meson_crtc->viu_offset + - _REG(VD1_IF0_RANGE_MAP_CB)); - writel_relaxed(priv->viu.vd1_range_map_cr, - priv->io_base + meson_crtc->viu_offset + - _REG(VD1_IF0_RANGE_MAP_CR)); + writel_relaxed(VPP_VSC_BANK_LENGTH(4) | VPP_HSC_BANK_LENGTH(4) | VPP_SC_VD_EN_ENABLE | @@ -692,10 +724,16 @@ int meson_crtc_create(struct meson_drm *priv) return ret; } =20 - if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) || + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { meson_crtc->enable_osd1 =3D meson_g12a_crtc_enable_osd1; meson_crtc->enable_vd1 =3D meson_g12a_crtc_enable_vd1; - meson_crtc->viu_offset =3D MESON_G12A_VIU_OFFSET; + + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) + meson_crtc->viu_offset =3D MESON_S4_VIU_OFFSET; + else + meson_crtc->viu_offset =3D MESON_G12A_VIU_OFFSET; + meson_crtc->enable_osd1_afbc =3D meson_crtc_g12a_enable_osd1_afbc; meson_crtc->disable_osd1_afbc =3D diff --git a/drivers/gpu/drm/meson/meson_overlay.c b/drivers/gpu/drm/meson/= meson_overlay.c index 7f98de38842bf932ca3388707ec3e2f2c38d97e3..3cf2efa407849d6af9b010a5ad5= 3e611155b6c9f 100644 --- a/drivers/gpu/drm/meson/meson_overlay.c +++ b/drivers/gpu/drm/meson/meson_overlay.c @@ -733,7 +733,12 @@ static void meson_overlay_atomic_disable(struct drm_pl= ane *plane, priv->viu.vd1_enabled =3D false; =20 /* Disable VD1 */ - if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { + writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL)); + writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL)); + writel_relaxed(0, priv->io_base + _REG(VD1_IF0_GEN_REG + 0x2db0)); + writel_relaxed(0, priv->io_base + _REG(VD2_IF0_GEN_REG + 0x2db0)); + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL)); writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL)); writel_relaxed(0, priv->io_base + _REG(VD1_IF0_GEN_REG + 0x17b0)); diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/me= son_plane.c index b43ac61201f3123e58effa9c4b734c23cfd3d5df..79cfa42af00f34f23993ab4b7af= 8b7bdfb23abce 100644 --- a/drivers/gpu/drm/meson/meson_plane.c +++ b/drivers/gpu/drm/meson/meson_plane.c @@ -161,7 +161,8 @@ static void meson_plane_atomic_update(struct drm_plane = *plane, =20 /* Check if AFBC decoder is required for this buffer */ if ((meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || - meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) && + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) || + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) && fb->modifier & DRM_FORMAT_MOD_ARM_AFBC(MESON_MOD_AFBC_VALID_BITS)) priv->viu.osd1_afbcd =3D true; else @@ -181,7 +182,8 @@ static void meson_plane_atomic_update(struct drm_plane = *plane, priv->viu.osd1_blk0_cfg[0] =3D canvas_id_osd1 << OSD_CANVAS_SEL; =20 if (priv->viu.osd1_afbcd) { - if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) || + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { /* This is the internal decoding memory address */ priv->viu.osd1_blk1_cfg4 =3D MESON_G12A_AFBCD_OUT_ADDR; priv->viu.osd1_blk0_cfg[0] |=3D OSD_ENDIANNESS_BE; @@ -205,7 +207,8 @@ static void meson_plane_atomic_update(struct drm_plane = *plane, priv->viu.osd1_blk0_cfg[0] |=3D OSD_OUTPUT_COLOR_RGB; =20 if (priv->viu.osd1_afbcd && - meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { + (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) || + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4))) { priv->viu.osd1_blk0_cfg[0] |=3D OSD_MALI_SRC_EN | priv->afbcd.ops->fmt_to_blk_mode(fb->modifier, fb->format->format); @@ -357,7 +360,8 @@ static void meson_plane_atomic_update(struct drm_plane = *plane, priv->viu.osd1_blk0_cfg[3] =3D ((dest.x2 - 1) << 16) | dest.x1; priv->viu.osd1_blk0_cfg[4] =3D ((dest.y2 - 1) << 16) | dest.y1; =20 - if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) || + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { priv->viu.osd_blend_din0_scope_h =3D ((dest.x2 - 1) << 16) | dest.x1; priv->viu.osd_blend_din0_scope_v =3D ((dest.y2 - 1) << 16) | dest.y1; priv->viu.osb_blend0_size =3D dst_h << 16 | dst_w; @@ -377,7 +381,8 @@ static void meson_plane_atomic_update(struct drm_plane = *plane, priv->afbcd.format =3D fb->format->format; =20 /* Calculate decoder write stride */ - if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) || + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) priv->viu.osd1_blk2_cfg4 =3D meson_g12a_afbcd_line_stride(priv); } @@ -408,7 +413,8 @@ static void meson_plane_atomic_disable(struct drm_plane= *plane, } =20 /* Disable OSD1 */ - if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) || + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) writel_bits_relaxed(VIU_OSD1_POSTBLD_SRC_OSD1, 0, priv->io_base + _REG(OSD1_BLEND_SRC_CTRL)); else @@ -439,7 +445,8 @@ static bool meson_plane_format_mod_supported(struct drm= _plane *plane, return true; =20 if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) && - !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) + !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) && + !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) return false; =20 if (modifier & ~DRM_FORMAT_MOD_ARM_AFBC(MESON_MOD_AFBC_VALID_BITS)) @@ -546,7 +553,8 @@ int meson_plane_create(struct meson_drm *priv) =20 if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) format_modifiers =3D format_modifiers_afbc_gxm; - else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) || + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) format_modifiers =3D format_modifiers_afbc_g12a; =20 ret =3D drm_universal_plane_init(priv->drm, plane, 0xFF, diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meso= n/meson_registers.h index 3d73d00a1f4c64cb90d2ab78f74133311d028197..c62ee8bac272be035e92dbc8e74= 3b2d4f864bc55 100644 --- a/drivers/gpu/drm/meson/meson_registers.h +++ b/drivers/gpu/drm/meson/meson_registers.h @@ -328,6 +328,22 @@ #define VIU_VD2_FMT_CTRL 0x1a88 #define VIU_VD2_FMT_W 0x1a89 =20 +#define VD1_IF0_RANGE_MAP_Y_S4 0x4816 +#define VD1_IF0_RANGE_MAP_CB_S4 0x4817 +#define VD1_IF0_RANGE_MAP_CR_S4 0x4818 +#define VD1_IF0_GEN_REG2_S4 0x4819 +#define VD1_IF0_GEN_REG3_S4 0x481c +#define VIU_VD1_FMT_CTRL_S4 0x481d +#define VIU_VD1_FMT_W_S4 0x481e + +#define VD2_IF0_RANGE_MAP_Y_S4 0x4896 +#define VD2_IF0_RANGE_MAP_CB_S4 0x4897 +#define VD2_IF0_RANGE_MAP_CR_S4 0x4898 +#define VD2_IF0_GEN_REG2_S4 0x4899 +#define VD2_IF0_GEN_REG3_S4 0x489c +#define VIU_VD2_FMT_CTRL_S4 0x489d +#define VIU_VD2_FMT_W_S4 0x489e + /* VIU Matrix Registers */ #define VIU_OSD1_MATRIX_CTRL 0x1a90 #define VIU_OSD1_MATRIX_COEF00_01 0x1a91 --=20 2.43.0 From nobody Sun Feb 8 15:46:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 550DB2066D4; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250110-drm-s4-v1-5-cbc2d5edaae8@amlogic.com> References: <20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com> In-Reply-To: <20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com> To: Neil Armstrong , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ao Xu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1736487593; l=4836; i=ao.xu@amlogic.com; s=20250103; h=from:subject:message-id; bh=AGf1FwU4Slf2RT1FJ8w3vm6caQaY7qdQQ+kqeFclowk=; b=O03WoOl7ev2tKtABGVQFak9car0stGf1lLLxx+0xHTWkr7gSQ0Z4TdcjEBv8DxNtBz4Q1NHR6 YEijsRWs97vBmVj6VMlNFSALP2RgaJU3F1fS16/hQn9GjDHiYDW76UN X-Developer-Key: i=ao.xu@amlogic.com; a=ed25519; pk=c0TSXrwQuL4EhPVf3lJ676U27ax2yfFTqmRoseP/fA8= X-Endpoint-Received: by B4 Relay for ao.xu@amlogic.com/20250103 with auth_id=308 X-Original-From: Ao Xu Reply-To: ao.xu@amlogic.com From: Ao Xu Update VIU and VPP initialization for S4 compatibility. VPP_MISC register definition was different with G12 SoCs, so disabled watermark control for S4. Signed-off-by: Ao Xu --- drivers/gpu/drm/meson/meson_registers.h | 1 + drivers/gpu/drm/meson/meson_viu.c | 9 ++++++--- drivers/gpu/drm/meson/meson_vpp.c | 12 +++++++++--- 3 files changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meso= n/meson_registers.h index c62ee8bac272be035e92dbc8e743b2d4f864bc55..4017c3344b3f90686d1041eda4f= f00a549ba6e54 100644 --- a/drivers/gpu/drm/meson/meson_registers.h +++ b/drivers/gpu/drm/meson/meson_registers.h @@ -463,6 +463,7 @@ #define VPP_OSD2_ALPHA_PREMULT BIT(8) #define VPP_OSD1_ALPHA_PREMULT BIT(9) #define VPP_VD1_POSTBLEND BIT(10) +#define VPP_WATER_MARK_10BIT BIT(10) #define VPP_VD2_POSTBLEND BIT(11) #define VPP_OSD1_POSTBLEND BIT(12) #define VPP_OSD2_POSTBLEND BIT(13) diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meso= n_viu.c index cd399b0b7181499218a8f969c0d320be88fd93c4..cb3646ccae68f3ce35b1148e5b5= df98b0116da96 100644 --- a/drivers/gpu/drm/meson/meson_viu.c +++ b/drivers/gpu/drm/meson/meson_viu.c @@ -425,7 +425,8 @@ void meson_viu_init(struct meson_drm *priv) if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) meson_viu_load_matrix(priv); - else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) || + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { meson_viu_set_g12a_osd1_matrix(priv, RGB709_to_YUV709l_coeff, true); /* fix green/pink color distortion from vendor u-boot */ @@ -440,7 +441,8 @@ void meson_viu_init(struct meson_drm *priv) VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */ VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=3D32 */ =20 - if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) || + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) reg |=3D (VIU_OSD_BURST_LENGTH_32 | VIU_OSD_HOLD_FIFO_LINES(31)); else reg |=3D (VIU_OSD_BURST_LENGTH_64 | VIU_OSD_HOLD_FIFO_LINES(4)); @@ -467,7 +469,8 @@ void meson_viu_init(struct meson_drm *priv) writel_relaxed(0x00FF00C0, priv->io_base + _REG(VD2_IF0_LUMA_FIFO_SIZE)); =20 - if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) || + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { u32 val =3D (u32)VIU_OSD_BLEND_REORDER(0, 1) | (u32)VIU_OSD_BLEND_REORDER(1, 0) | (u32)VIU_OSD_BLEND_REORDER(2, 0) | diff --git a/drivers/gpu/drm/meson/meson_vpp.c b/drivers/gpu/drm/meson/meso= n_vpp.c index 5df1957c8e41f4e438545f91dd9eecb423e53b91..92e7d26abaa8771e5cc99a03e5a= 5ff32f5a48d30 100644 --- a/drivers/gpu/drm/meson/meson_vpp.c +++ b/drivers/gpu/drm/meson/meson_vpp.c @@ -102,11 +102,13 @@ void meson_vpp_init(struct meson_drm *priv) priv->io_base + _REG(VPP_DUMMY_DATA1)); writel_relaxed(0x42020, priv->io_base + _REG(VPP_DUMMY_DATA)); - } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) || + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) writel_relaxed(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL)); =20 /* Initialize vpu fifo control registers */ - if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) || + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) writel_relaxed(VPP_OFIFO_SIZE_DEFAULT, priv->io_base + _REG(VPP_OFIFO_SIZE)); else @@ -115,7 +117,8 @@ void meson_vpp_init(struct meson_drm *priv) writel_relaxed(VPP_POSTBLEND_HOLD_LINES(4) | VPP_PREBLEND_HOLD_LINES(4), priv->io_base + _REG(VPP_HOLD_LINES)); =20 - if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { + if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) && + !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { /* Turn off preblend */ writel_bits_relaxed(VPP_PREBLEND_ENABLE, 0, priv->io_base + _REG(VPP_MISC)); @@ -137,6 +140,9 @@ void meson_vpp_init(struct meson_drm *priv) priv->io_base + _REG(VPP_BLEND_VD2_H_START_END)); } =20 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) + writel_bits_relaxed(VPP_WATER_MARK_10BIT, 0, priv->io_base + _REG(VPP_MI= SC)); + /* Disable Scalers */ writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0)); writel_relaxed(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0)); --=20 2.43.0 From nobody Sun Feb 8 15:46:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5506C2066CF; Fri, 10 Jan 2025 05:39:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736487596; cv=none; b=VUXkoNcsIZgAssRG7mm4Y64MNUnwD2rNIvaGiw3MrziBX90jK4soishWeOmeE5nctEt4qG/tioStgTNBdyBDZdqdRIg7QQeyO4y4WCBVJivMgGNCVNYRFmwfJN/Oy2b//n/mb11WIUBe6YGWZDsmTEgdi0LKTh9RvRCzEI+wK4I= ARC-Message-Signature: i=1; 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b=X0fo6UOp8sj6MzyBZxiqWtXtvm5UUYNtCFYAbpur8gkRX6HSI9IStsmFHImRIPzQz frq9aci6WYW92IBrebMNk8nj7SHDiEWUWIwv/CNDMkDjjU2BCbN/z/tmnUnUsKfPVh trPFUfI4ceowTjy9/NhdyHzUowJmesmEiOwg5ncPXGZTbHmdB8aHuaJ3a5IGQ9juzv HbLq2cd0O/yWrjC3sAzntHH6TbpirNS+Cn2DSX8QvrMv5OT4nKO+xloYsXM5Zpkp1Y qwUQHF/sTmh3AUhDUPdO3Plv0WXNMlzMazIRKsj5K4+9zBA+hz/UVEujwnRTOInXAC VqKDvFDoivDWw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E769BE77188; Fri, 10 Jan 2025 05:39:55 +0000 (UTC) From: Ao Xu via B4 Relay Date: Fri, 10 Jan 2025 13:39:56 +0800 Subject: [PATCH 06/11] drm: meson: add meson_dw_hdmi support for S4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250110-drm-s4-v1-6-cbc2d5edaae8@amlogic.com> References: <20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com> In-Reply-To: <20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com> To: Neil Armstrong , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ao Xu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1736487593; l=19811; i=ao.xu@amlogic.com; s=20250103; h=from:subject:message-id; bh=WtQmA6Oy2yV+LVYGHtPBPe9Fmnab2MVpSkcVYbGAx6E=; b=OXgye7NZ5HKzlo+5WNe2i78vhVyJf8xmH4H1CQE+WoYY5v1TTtfye7tYw1fzSrvHoRkdZsjl1 yLrWl0WCTGuBluQBJXpMmMYagFTofrJfiFZTgPZeGgtpC7Dx0cmkash X-Developer-Key: i=ao.xu@amlogic.com; a=ed25519; pk=c0TSXrwQuL4EhPVf3lJ676U27ax2yfFTqmRoseP/fA8= X-Endpoint-Received: by B4 Relay for ao.xu@amlogic.com/20250103 with auth_id=308 X-Original-From: Ao Xu Reply-To: ao.xu@amlogic.com From: Ao Xu Add S4 dw_hdmi register access method. Adjust clock, power domain, and PHY configurations to support HDMI on the S4. Signed-off-by: Ao Xu --- drivers/gpu/drm/meson/meson_dw_hdmi.c | 244 ++++++++++++++++++++++++++++--= ---- drivers/gpu/drm/meson/meson_dw_hdmi.h | 126 ++++++++++++++++++ 2 files changed, 329 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/= meson_dw_hdmi.c index 0d7c68b29dfff43ef276734368b15da9ee497919..bf59e68bba498620dd6e503de4e= 5e087637c17a0 100644 --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c @@ -14,6 +14,7 @@ #include #include #include +#include =20 #include #include @@ -90,29 +91,6 @@ * - CEC Management */ =20 -/* TOP Block Communication Channel */ -#define HDMITX_TOP_ADDR_REG 0x0 -#define HDMITX_TOP_DATA_REG 0x4 -#define HDMITX_TOP_CTRL_REG 0x8 -#define HDMITX_TOP_G12A_OFFSET 0x8000 - -/* Controller Communication Channel */ -#define HDMITX_DWC_ADDR_REG 0x10 -#define HDMITX_DWC_DATA_REG 0x14 -#define HDMITX_DWC_CTRL_REG 0x18 - -/* HHI Registers */ -#define HHI_MEM_PD_REG0 0x100 /* 0x40 */ -#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */ -#define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 */ -#define HHI_HDMI_PHY_CNTL1 0x3a4 /* 0xe9 */ -#define PHY_CNTL1_INIT 0x03900000 -#define PHY_INVERT BIT(17) -#define HHI_HDMI_PHY_CNTL2 0x3a8 /* 0xea */ -#define HHI_HDMI_PHY_CNTL3 0x3ac /* 0xeb */ -#define HHI_HDMI_PHY_CNTL4 0x3b0 /* 0xec */ -#define HHI_HDMI_PHY_CNTL5 0x3b4 /* 0xed */ - static DEFINE_SPINLOCK(reg_lock); =20 enum meson_venc_source { @@ -185,6 +163,39 @@ static unsigned int dw_hdmi_g12a_top_read(struct meson= _dw_hdmi *dw_hdmi, return readl(dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2)); } =20 +static unsigned int dw_hdmi_s4_top_read(struct meson_dw_hdmi *dw_hdmi, + unsigned int addr) +{ + struct arm_smccc_res res; + unsigned int val; + + switch (addr) { + case HDMITX_TOP_SKP_CNTL_STAT: + case HDMITX_TOP_NONCE_0: + case HDMITX_TOP_NONCE_1: + case HDMITX_TOP_NONCE_2: + case HDMITX_TOP_NONCE_3: + case HDMITX_TOP_PKF_0: + case HDMITX_TOP_PKF_1: + case HDMITX_TOP_PKF_2: + case HDMITX_TOP_PKF_3: + case HDMITX_TOP_DUK_0: + case HDMITX_TOP_DUK_1: + case HDMITX_TOP_DUK_2: + case HDMITX_TOP_DUK_3: + case HDMITX_TOP_HDCP22_BSOD: + addr |=3D TOP_SEC_OFFSET_MASK; + arm_smccc_smc(HDMI_SEC_READ_REG, (unsigned long)addr, 0, 0, 0, 0, 0, 0, = &res); + val =3D (unsigned int)((res.a0) & 0xffffffff); + break; + default: + val =3D readl(dw_hdmi->hdmitx + HDMITX_TOP_S4_OFFSET + (addr << 2)); + break; + } + + return val; +} + static inline void dw_hdmi_top_write(struct meson_dw_hdmi *dw_hdmi, unsigned int addr, unsigned int data) { @@ -208,6 +219,35 @@ static inline void dw_hdmi_g12a_top_write(struct meson= _dw_hdmi *dw_hdmi, writel(data, dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2)); } =20 +static inline void dw_hdmi_s4_top_write(struct meson_dw_hdmi *dw_hdmi, + unsigned int addr, unsigned int data) +{ + struct arm_smccc_res res; + + switch (addr) { + case HDMITX_TOP_SKP_CNTL_STAT: + case HDMITX_TOP_NONCE_0: + case HDMITX_TOP_NONCE_1: + case HDMITX_TOP_NONCE_2: + case HDMITX_TOP_NONCE_3: + case HDMITX_TOP_PKF_0: + case HDMITX_TOP_PKF_1: + case HDMITX_TOP_PKF_2: + case HDMITX_TOP_PKF_3: + case HDMITX_TOP_DUK_0: + case HDMITX_TOP_DUK_1: + case HDMITX_TOP_DUK_2: + case HDMITX_TOP_DUK_3: + case HDMITX_TOP_HDCP22_BSOD: + addr |=3D TOP_SEC_OFFSET_MASK; + arm_smccc_smc(HDMI_SEC_WRITE_REG, (unsigned long)addr, data, 0, 0, 0, 0,= 0, &res); + break; + default: + writel(data, dw_hdmi->hdmitx + HDMITX_TOP_S4_OFFSET + (addr << 2)); + break; + } +} + /* Helper to change specific bits in PHY registers */ static inline void dw_hdmi_top_write_bits(struct meson_dw_hdmi *dw_hdmi, unsigned int addr, @@ -249,6 +289,38 @@ static unsigned int dw_hdmi_g12a_dwc_read(struct meson= _dw_hdmi *dw_hdmi, return readb(dw_hdmi->hdmitx + addr); } =20 +static unsigned int dw_hdmi_s4_dwc_read(struct meson_dw_hdmi *dw_hdmi, + unsigned int addr) +{ + struct arm_smccc_res res; + unsigned int val; + + switch (addr) { + case HDMITX_DWC_MC_CLKDIS: + case HDMITX_DWC_A_HDCPCFG0: + case HDMITX_DWC_A_HDCPCFG1: + case HDMITX_DWC_HDCPREG_SEED0: + case HDMITX_DWC_HDCPREG_SEED1: + case HDMITX_DWC_HDCPREG_DPK0: + case HDMITX_DWC_HDCPREG_DPK1: + case HDMITX_DWC_HDCPREG_DPK2: + case HDMITX_DWC_HDCPREG_DPK3: + case HDMITX_DWC_HDCPREG_DPK4: + case HDMITX_DWC_HDCPREG_DPK5: + case HDMITX_DWC_HDCPREG_DPK6: + case HDMITX_DWC_HDCP22REG_CTRL: + addr |=3D DWC_SEC_OFFSET_MASK; + arm_smccc_smc(HDMI_SEC_READ_REG, (unsigned long)addr, 0, 0, 0, 0, 0, 0, = &res); + val =3D (unsigned int)((res.a0) & 0xffffffff); + break; + default: + val =3D readb(dw_hdmi->hdmitx + addr); + break; + } + + return val; +} + static inline void dw_hdmi_dwc_write(struct meson_dw_hdmi *dw_hdmi, unsigned int addr, unsigned int data) { @@ -272,6 +344,34 @@ static inline void dw_hdmi_g12a_dwc_write(struct meson= _dw_hdmi *dw_hdmi, writeb(data, dw_hdmi->hdmitx + addr); } =20 +static inline void dw_hdmi_s4_dwc_write(struct meson_dw_hdmi *dw_hdmi, + unsigned int addr, unsigned int data) +{ + struct arm_smccc_res res; + + switch (addr) { + case HDMITX_DWC_MC_CLKDIS: + case HDMITX_DWC_A_HDCPCFG0: + case HDMITX_DWC_A_HDCPCFG1: + case HDMITX_DWC_HDCPREG_SEED0: + case HDMITX_DWC_HDCPREG_SEED1: + case HDMITX_DWC_HDCPREG_DPK0: + case HDMITX_DWC_HDCPREG_DPK1: + case HDMITX_DWC_HDCPREG_DPK2: + case HDMITX_DWC_HDCPREG_DPK3: + case HDMITX_DWC_HDCPREG_DPK4: + case HDMITX_DWC_HDCPREG_DPK5: + case HDMITX_DWC_HDCPREG_DPK6: + case HDMITX_DWC_HDCP22REG_CTRL: + addr |=3D DWC_SEC_OFFSET_MASK; + arm_smccc_smc(HDMI_SEC_WRITE_REG, (unsigned long)addr, data, 0, 0, 0, 0,= 0, &res); + break; + default: + writeb(data, dw_hdmi->hdmitx + addr); + break; + } +} + /* Bridge */ =20 /* Setup PHY bandwidth modes */ @@ -337,6 +437,23 @@ static void meson_hdmi_phy_setup_mode(struct meson_dw_= hdmi *dw_hdmi, regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL5, 0x00000003); } + } else if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-s4-dw-hdmi")) { + if (pixel_clock >=3D 371250) { + /* 5.94Gbps, 4.5Gbps, 3.7125Gbps */ + regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL5, 0x0000080b); + regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL0, 0x37eb65c4); + regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b); + } else if (pixel_clock >=3D 297000) { + /* 2.97Gbps */ + regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL5, 0x00000003); + regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL0, 0x33eb42a2); + regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b); + } else { + /* 1.485Gbps, and below */ + regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL5, 0x00000003); + regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL0, 0x33eb4252); + regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b); + } } } =20 @@ -344,13 +461,23 @@ static inline void meson_dw_hdmi_phy_reset(struct mes= on_dw_hdmi *dw_hdmi) { struct meson_drm *priv =3D dw_hdmi->priv; =20 - /* Enable and software reset */ - regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xf); + if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-s4-dw-hdmi")) { + /* Enable and software reset */ + regmap_update_bits(priv->hhi, ANACTRL_HDMIPHY_CTRL1, 0xf, 0xf); =20 - mdelay(2); + mdelay(2); =20 - /* Enable and unreset */ - regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xe); + /* Enable and unreset */ + regmap_update_bits(priv->hhi, ANACTRL_HDMIPHY_CTRL1, 0xf, 0xe); + } else { + /* Enable and software reset */ + regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xf); + + mdelay(2); + + /* Enable and unreset */ + regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xe); + } =20 mdelay(2); } @@ -396,7 +523,10 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void= *data, meson_hdmi_phy_setup_mode(dw_hdmi, mode, mode_is_420); =20 /* Disable clock, fifo, fifo_wr */ - regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0); + if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-s4-dw-hdmi")) + regmap_update_bits(priv->hhi, ANACTRL_HDMIPHY_CTRL1, 0xf, 0); + else + regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0); =20 dw_hdmi_set_high_tmds_clock_ratio(hdmi, display); =20 @@ -449,8 +579,15 @@ static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, DRM_DEBUG_DRIVER("\n"); =20 /* Fallback to init mode */ - regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, dw_hdmi->data->cntl1_init); - regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, dw_hdmi->data->cntl0_init); + if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-s4-dw-hdmi")) { + regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL1, + dw_hdmi->data->cntl1_init); + regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL0, + dw_hdmi->data->cntl0_init); + } else { + regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, dw_hdmi->data->cntl1_init); + regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, dw_hdmi->data->cntl0_init); + } } =20 static enum drm_connector_status dw_hdmi_read_hpd(struct dw_hdmi *hdmi, @@ -595,23 +732,36 @@ static const struct meson_dw_hdmi_data meson_dw_hdmi_= g12a_data =3D { .cntl1_init =3D PHY_CNTL1_INIT, }; =20 +static const struct meson_dw_hdmi_data meson_dw_hdmi_s4_data =3D { + .top_read =3D dw_hdmi_s4_top_read, + .top_write =3D dw_hdmi_s4_top_write, + .dwc_read =3D dw_hdmi_s4_dwc_read, + .dwc_write =3D dw_hdmi_s4_dwc_write, + .cntl0_init =3D 0x0, + .cntl1_init =3D PHY_CNTL1_INIT, +}; + static void meson_dw_hdmi_init(struct meson_dw_hdmi *meson_dw_hdmi) { struct meson_drm *priv =3D meson_dw_hdmi->priv; =20 - /* Enable clocks */ - regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100); - - /* Bring HDMITX MEM output of power down */ - regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0); - + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { + regmap_update_bits(priv->hhi, CLKCTRL_HDMI_CLK_CTRL, 0xffff, 0x100); + regmap_update_bits(priv->pwrctrl, PWRCTRL_MEM_PD11, 0xff << 8, 0); + } else { + /* Enable clocks */ + regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100); + /* Bring HDMITX MEM output of power down */ + regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0); + } /* Reset HDMITX APB & TX & PHY */ reset_control_reset(meson_dw_hdmi->hdmitx_apb); reset_control_reset(meson_dw_hdmi->hdmitx_ctrl); reset_control_reset(meson_dw_hdmi->hdmitx_phy); =20 /* Enable APB3 fail on error */ - if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { + if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) && + !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { writel_bits_relaxed(BIT(15), BIT(15), meson_dw_hdmi->hdmitx + HDMITX_TOP_CTRL_REG); writel_bits_relaxed(BIT(15), BIT(15), @@ -631,8 +781,15 @@ static void meson_dw_hdmi_init(struct meson_dw_hdmi *m= eson_dw_hdmi) meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(1= 2)); =20 /* Setup PHY */ - regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, meson_dw_hdmi->data->cntl1_in= it); - regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, meson_dw_hdmi->data->cntl0_in= it); + if (dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-s4-dw-hdmi")) { + regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL1, + meson_dw_hdmi->data->cntl1_init); + regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL0, + meson_dw_hdmi->data->cntl0_init); + } else { + regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, meson_dw_hdmi->data->cntl1_i= nit); + regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, meson_dw_hdmi->data->cntl0_i= nit); + } =20 /* Enable HDMI-TX Interrupt */ meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR, @@ -766,10 +923,13 @@ static int meson_dw_hdmi_bind(struct device *dev, str= uct device *master, dw_plat_data->ycbcr_420_allowed =3D true; dw_plat_data->disable_cec =3D true; dw_plat_data->output_port =3D 1; + if (dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-s4-dw-hdmi")) + dw_plat_data->phy_force_vendor =3D 1; =20 if (dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxl-dw-hdmi") || dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxm-dw-hdmi") || - dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-g12a-dw-hdmi")) + dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-g12a-dw-hdmi") || + dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-s4-dw-hdmi")) dw_plat_data->use_drm_infoframe =3D true; =20 platform_set_drvdata(pdev, meson_dw_hdmi); @@ -850,6 +1010,8 @@ static const struct of_device_id meson_dw_hdmi_of_tabl= e[] =3D { .data =3D &meson_dw_hdmi_gxl_data }, { .compatible =3D "amlogic,meson-g12a-dw-hdmi", .data =3D &meson_dw_hdmi_g12a_data }, + { .compatible =3D "amlogic,meson-s4-dw-hdmi", + .data =3D &meson_dw_hdmi_s4_data }, { } }; MODULE_DEVICE_TABLE(of, meson_dw_hdmi_of_table); diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.h b/drivers/gpu/drm/meson/= meson_dw_hdmi.h index 08e1c14e4ea07c694f2c5fccbbf593661a8a3feb..66203b59e5e0ca67463ec5c7916= 5e757f3a24406 100644 --- a/drivers/gpu/drm/meson/meson_dw_hdmi.h +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.h @@ -8,6 +8,16 @@ #ifndef __MESON_DW_HDMI_H #define __MESON_DW_HDMI_H =20 +/* TOP-level wrapper registers addresses + * bit24: 1 means secure access + * bit28: 1 means DWC, 0 means TOP + */ +#define TOP_SEC_OFFSET_MASK BIT(24) +#define DWC_SEC_OFFSET_MASK (BIT(24) | BIT(28)) + +#define HDMI_SEC_READ_REG (0x82000018) +#define HDMI_SEC_WRITE_REG (0x82000019) + /* * Bit 15-10: RW Reserved. Default 1 starting from G12A * Bit 9 RW sw_reset_i2c starting from G12A @@ -157,4 +167,120 @@ */ #define HDMITX_TOP_STAT0 (0x00E) =20 +#define HDMITX_TOP_SKP_CNTL_STAT (0x010) +#define HDMITX_TOP_NONCE_0 (0x011) +#define HDMITX_TOP_NONCE_1 (0x012) +#define HDMITX_TOP_NONCE_2 (0x013) +#define HDMITX_TOP_NONCE_3 (0x014) +#define HDMITX_TOP_PKF_0 (0x015) +#define HDMITX_TOP_PKF_1 (0x016) +#define HDMITX_TOP_PKF_2 (0x017) +#define HDMITX_TOP_PKF_3 (0x018) +#define HDMITX_TOP_DUK_0 (0x019) +#define HDMITX_TOP_DUK_1 (0x01A) +#define HDMITX_TOP_DUK_2 (0x01B) +#define HDMITX_TOP_DUK_3 (0x01C) + +/* [26:24] infilter_ddc_intern_clk_divide */ +/* [23:16] infilter_ddc_sample_clk_divide */ +/* [10: 8] infilter_cec_intern_clk_divide */ +/* [ 7: 0] infilter_cec_sample_clk_divide */ +#define HDMITX_TOP_INFILTER (0x01D) +#define HDMITX_TOP_NSEC_SCRATCH (0x01E) +#define HDMITX_TOP_SEC_SCRATCH (0x01F) +#define HDMITX_TOP_EMP_CNTL0 (0x020) +#define HDMITX_TOP_EMP_CNTL1 (0x021) +#define HDMITX_TOP_EMP_MEMADDR_START (0x022) +#define HDMITX_TOP_EMP_STAT0 (0x023) +#define HDMITX_TOP_EMP_STAT1 (0x024) +#define HDMITX_TOP_AXI_ASYNC_CNTL0 (0x025) +#define HDMITX_TOP_AXI_ASYNC_CNTL1 (0x026) +#define HDMITX_TOP_AXI_ASYNC_STAT0 (0x027) +#define HDMITX_TOP_I2C_BUSY_CNT_MAX (0x028) +#define HDMITX_TOP_I2C_BUSY_CNT_STAT (0x029) +#define HDMITX_TOP_HDCP22_BSOD (0x02A) +#define HDMITX_TOP_DDC_CNTL (0x02B) +#define HDMITX_TOP_DISABLE_NULL (0x030) +#define HDMITX_TOP_HDCP14_UNENCRYPT (0x031) +#define HDMITX_TOP_MISC_CNTL (0x032) +#define HDMITX_TOP_HDCP22_MIN_SIZE (0x035) + +#define HDMITX_TOP_DONT_TOUCH0 (0x0FE) +#define HDMITX_TOP_DONT_TOUCH1 (0x0FF) + +/* DWC_HDMI_TX Controller SEC registers addresses */ +/* Main Controller Registers */ +/* [ 6] hdcpclk_disable */ +/* [ 5] cecclk_disable */ +/* [ 4] cscclk_disable */ +/* [ 3] audclk_disable */ +/* [ 2] prepclk_disable */ +/* [ 1] tmdsclk_disable */ +/* [ 0] pixelclk_disable */ +#define HDMITX_DWC_MC_CLKDIS (0x4001) + +/* HDCP Encryption Engine Registers */ +#define HDMITX_DWC_A_HDCPCFG0 (0x5000) + +/* [ 4] hdcp_lock */ +/* [ 3] dissha1check */ +/* [ 2] ph2upshiftenc */ +/* [ 1] encryptiondisable */ +/* [ 0] swresetn. Write 0 to activate, self-clear to 1. */ +#define HDMITX_DWC_A_HDCPCFG1 (0x5001) + +/* Encrypted DPK Embedded Storage Registers */ +#define HDMITX_DWC_HDCPREG_SEED0 (0x7810) +#define HDMITX_DWC_HDCPREG_SEED1 (0x7811) +#define HDMITX_DWC_HDCPREG_DPK0 (0x7812) +#define HDMITX_DWC_HDCPREG_DPK1 (0x7813) +#define HDMITX_DWC_HDCPREG_DPK2 (0x7814) +#define HDMITX_DWC_HDCPREG_DPK3 (0x7815) +#define HDMITX_DWC_HDCPREG_DPK4 (0x7816) +#define HDMITX_DWC_HDCPREG_DPK5 (0x7817) +#define HDMITX_DWC_HDCPREG_DPK6 (0x7818) + +/* HDCP22 Registers */ +#define HDMITX_DWC_HDCP22REG_CTRL (0x7904) + +/* TOP Block Communication Channel */ +#define HDMITX_TOP_ADDR_REG 0x0 +#define HDMITX_TOP_DATA_REG 0x4 +#define HDMITX_TOP_CTRL_REG 0x8 +#define HDMITX_TOP_G12A_OFFSET 0x8000 +#define HDMITX_TOP_S4_OFFSET 0x8000 + +/* Controller Communication Channel */ +#define HDMITX_DWC_ADDR_REG 0x10 +#define HDMITX_DWC_DATA_REG 0x14 +#define HDMITX_DWC_CTRL_REG 0x18 + +/* HHI Registers */ +#define HHI_MEM_PD_REG0 0x100 /* 0x40 */ +#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */ +#define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 */ +#define HHI_HDMI_PHY_CNTL1 0x3a4 /* 0xe9 */ +#define HHI_HDMI_PHY_CNTL2 0x3a8 /* 0xea */ +#define HHI_HDMI_PHY_CNTL3 0x3ac /* 0xeb */ +#define HHI_HDMI_PHY_CNTL4 0x3b0 /* 0xec */ +#define HHI_HDMI_PHY_CNTL5 0x3b4 /* 0xed */ + +/*ANA Registers */ +/* REG_BASE: REGISTER_BASE_ADDR =3D 0xfe00c000 */ +#define PWRCTRL_MEM_PD11 0x06c /* 0x1b */ + +/* REG_BASE: REGISTER_BASE_ADDR =3D 0xfe000000 */ +#define CLKCTRL_HDMI_CLK_CTRL 0x0e0 /* 0x38 */ + +/* REG_BASE: REGISTER_BASE_ADDR =3D 0xfe008000 */ +#define ANACTRL_HDMIPHY_CTRL0 0x200 /* 0x80 */ +#define ANACTRL_HDMIPHY_CTRL1 0x204 /* 0x81 */ +#define PHY_CNTL1_INIT 0x03900000 +#define PHY_INVERT BIT(17) +#define ANACTRL_HDMIPHY_CTRL2 0x208 /* 0x82 */ +#define ANACTRL_HDMIPHY_CTRL3 0x20c /* 0x83 */ +#define ANACTRL_HDMIPHY_CTRL4 0x210 /* 0x84 */ +#define ANACTRL_HDMIPHY_CTRL5 0x214 /* 0x85 */ +#define ANACTRL_HDMIPHY_STS 0x218 /* 0x86 */ + #endif /* __MESON_DW_HDMI_H */ --=20 2.43.0 From nobody Sun Feb 8 15:46:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 676AF2066E2; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250110-drm-s4-v1-7-cbc2d5edaae8@amlogic.com> References: <20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com> In-Reply-To: <20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com> To: Neil Armstrong , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ao Xu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1736487593; l=6404; i=ao.xu@amlogic.com; s=20250103; h=from:subject:message-id; bh=4USay3QtDuRbS8FCpdm9MAw33ZXb1TEINIc05tyQlYM=; b=VIGGkrGrVQnJ7yCira+Tj6lvZDk0IICJyvIkw2pXvabnZW9xtixF5K9TEzYjPmA2f2/77B6HH qiJXrflCXR7CwEKWaFqO3ADDBw83QA/T5qDaWHC25lkLeHHYbzukJQr X-Developer-Key: i=ao.xu@amlogic.com; a=ed25519; pk=c0TSXrwQuL4EhPVf3lJ676U27ax2yfFTqmRoseP/fA8= X-Endpoint-Received: by B4 Relay for ao.xu@amlogic.com/20250103 with auth_id=308 X-Original-From: Ao Xu Reply-To: ao.xu@amlogic.com From: Ao Xu Adjust the parameters passed to specific API calls in the Meson HDMI encoder to align with hardware requirements. Configure VCLK to use double pixels for 480p and 576p resolutions in the Amlogic S4. Signed-off-by: Ao Xu --- drivers/gpu/drm/meson/meson_encoder_hdmi.c | 19 +++++++++++++++---- drivers/gpu/drm/meson/meson_venc.c | 12 ++++++------ drivers/gpu/drm/meson/meson_venc.h | 4 ++-- 3 files changed, 23 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_encoder_hdmi.c b/drivers/gpu/drm/m= eson/meson_encoder_hdmi.c index 0593a1cde906ffab10c010c40942fb910059b2ab..5fde4cfc79ad66d3bb6c15cedce= 536f1346fce34 100644 --- a/drivers/gpu/drm/meson/meson_encoder_hdmi.c +++ b/drivers/gpu/drm/meson/meson_encoder_hdmi.c @@ -98,7 +98,7 @@ static void meson_encoder_hdmi_set_vclk(struct meson_enco= der_hdmi *encoder_hdmi, hdmi_freq =3D vclk_freq; =20 /* VENC double pixels for 1080i, 720p and YUV420 modes */ - if (meson_venc_hdmi_venc_repeat(vic) || + if (meson_venc_hdmi_venc_repeat(priv, vic) || encoder_hdmi->output_bus_fmt =3D=3D MEDIA_BUS_FMT_UYYVYY8_0_5X24) venc_freq *=3D 2; =20 @@ -107,6 +107,11 @@ static void meson_encoder_hdmi_set_vclk(struct meson_e= ncoder_hdmi *encoder_hdmi, if (mode->flags & DRM_MODE_FLAG_DBLCLK) venc_freq /=3D 2; =20 + /* VCLK double pixels for 480p and 576p on S4 */ + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) + if (vic =3D=3D 2 || vic =3D=3D 3 || vic =3D=3D 17 || vic =3D=3D 18) + vclk_freq *=3D 2; + dev_dbg(priv->dev, "vclk:%d phy=3D%d venc=3D%d hdmi=3D%d enci=3D%d\n", phy_freq, vclk_freq, venc_freq, hdmi_freq, priv->venc.hdmi_use_enci); @@ -146,7 +151,7 @@ static enum drm_mode_status meson_encoder_hdmi_mode_val= id(struct drm_bridge *bri =20 return meson_vclk_dmt_supported_freq(priv, mode->clock); /* Check against supported VIC modes */ - } else if (!meson_venc_hdmi_supported_vic(vic)) + } else if (!meson_venc_hdmi_supported_vic(priv, vic)) return MODE_BAD; =20 vclk_freq =3D mode->clock; @@ -168,7 +173,7 @@ static enum drm_mode_status meson_encoder_hdmi_mode_val= id(struct drm_bridge *bri hdmi_freq =3D vclk_freq; =20 /* VENC double pixels for 1080i, 720p and YUV420 modes */ - if (meson_venc_hdmi_venc_repeat(vic) || + if (meson_venc_hdmi_venc_repeat(priv, vic) || drm_mode_is_420_only(display_info, mode) || (!is_hdmi2_sink && drm_mode_is_420_also(display_info, mode))) @@ -179,6 +184,11 @@ static enum drm_mode_status meson_encoder_hdmi_mode_va= lid(struct drm_bridge *bri if (mode->flags & DRM_MODE_FLAG_DBLCLK) venc_freq /=3D 2; =20 + /* VCLK double pixels for 480p and 576p on S4 */ + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) + if (vic =3D=3D 2 || vic =3D=3D 3 || vic =3D=3D 17 || vic =3D=3D 18) + vclk_freq *=3D 2; + dev_dbg(priv->dev, "%s: vclk:%d phy=3D%d venc=3D%d hdmi=3D%d\n", __func__, phy_freq, vclk_freq, venc_freq, hdmi_freq); =20 @@ -444,7 +454,8 @@ int meson_encoder_hdmi_probe(struct meson_drm *priv) =20 if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL) || meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || - meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A) || + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) drm_connector_attach_hdr_output_metadata_property(meson_encoder_hdmi->co= nnector); =20 drm_connector_attach_max_bpc_property(meson_encoder_hdmi->connector, 8, 8= ); diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/mes= on_venc.c index 3bf0d6e4fc30ae1e06f6ba77157325af416c786f..5c461b27ae49317d8f430dc5560= 6c8e11a536240 100644 --- a/drivers/gpu/drm/meson/meson_venc.c +++ b/drivers/gpu/drm/meson/meson_venc.c @@ -878,7 +878,7 @@ meson_venc_hdmi_supported_mode(const struct drm_display= _mode *mode) } EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_mode); =20 -bool meson_venc_hdmi_supported_vic(int vic) +bool meson_venc_hdmi_supported_vic(struct meson_drm *priv, int vic) { struct meson_hdmi_venc_vic_mode *vmode =3D meson_hdmi_venc_vic_modes; =20 @@ -917,7 +917,7 @@ static void meson_venc_hdmi_get_dmt_vmode(const struct = drm_display_mode *mode, dmt_mode->encp.max_lncnt =3D mode->vtotal - 1; } =20 -static union meson_hdmi_venc_mode *meson_venc_hdmi_get_vic_vmode(int vic) +static union meson_hdmi_venc_mode *meson_venc_hdmi_get_vic_vmode(struct me= son_drm *priv, int vic) { struct meson_hdmi_venc_vic_mode *vmode =3D meson_hdmi_venc_vic_modes; =20 @@ -930,7 +930,7 @@ static union meson_hdmi_venc_mode *meson_venc_hdmi_get_= vic_vmode(int vic) return NULL; } =20 -bool meson_venc_hdmi_venc_repeat(int vic) +bool meson_venc_hdmi_venc_repeat(struct meson_drm *priv, int vic) { /* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */ if (vic =3D=3D 6 || vic =3D=3D 7 || /* 480i */ @@ -989,8 +989,8 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, i= nt vic, venc_hdmi_latency =3D 1; } =20 - if (meson_venc_hdmi_supported_vic(vic)) { - vmode =3D meson_venc_hdmi_get_vic_vmode(vic); + if (meson_venc_hdmi_supported_vic(priv, vic)) { + vmode =3D meson_venc_hdmi_get_vic_vmode(priv, vic); if (!vmode) { dev_err(priv->dev, "%s: Fatal Error, unsupported mode " DRM_MODE_FMT "\n", __func__, @@ -1004,7 +1004,7 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv,= int vic, } =20 /* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */ - if (meson_venc_hdmi_venc_repeat(vic)) + if (meson_venc_hdmi_venc_repeat(priv, vic)) venc_repeat =3D true; =20 eof_lines =3D mode->vsync_start - mode->vdisplay; diff --git a/drivers/gpu/drm/meson/meson_venc.h b/drivers/gpu/drm/meson/mes= on_venc.h index 0f59adb1c6db08ca39d0c556875cf5d0d8df430a..7cc6841f633048364c9880f5d1f= 0e18e3056c9f8 100644 --- a/drivers/gpu/drm/meson/meson_venc.h +++ b/drivers/gpu/drm/meson/meson_venc.h @@ -54,8 +54,8 @@ void meson_encl_load_gamma(struct meson_drm *priv); /* HDMI Clock parameters */ enum drm_mode_status meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode); -bool meson_venc_hdmi_supported_vic(int vic); -bool meson_venc_hdmi_venc_repeat(int vic); +bool meson_venc_hdmi_supported_vic(struct meson_drm *priv, int vic); +bool meson_venc_hdmi_venc_repeat(struct meson_drm *priv, int vic); =20 /* CVBS Timings and Parameters */ extern struct meson_cvbs_enci_mode meson_cvbs_enci_pal; --=20 2.43.0 From nobody Sun Feb 8 15:46:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5ED2C2066DB; Fri, 10 Jan 2025 05:39:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736487596; cv=none; b=IRLxSAzgp99v/IkDHhPS/Bsei+qmKzLucNbuVlPMwQFwWav6GDMxO3ZzB5qtY1fYWzlxgFYXstBcgCcvADhhEh7Oeiel389c6cusRi3PL/rttRgd4Uhux92F5hYYuoUYIoPWWHHHBsK+mE8Ugo5j7SzaxwfNgaGZC6gGUBAP5vE= ARC-Message-Signature: i=1; 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b=LkN4DSzGs6FlTkGFlNGb407Ro6cFmDL89x1QBZIH/zL3lutCt5/HY7EpCDSUdbGqV HN36Ij4tYzJKdaaOI+4Cf+jR4l2lhUdxnCI99S5CqEIrGk+pta2J/n+AFwmaBp7OdZ Wh30MbzZZ5s62XOoXl7TVu4AthZZnA0hv9kXIfCWRf0UV73Cribo0Ju5nJh3Y8IgeK UVT6DWotEy9jLM1UFYPeECYe8xnREnGYnSPck3vFguFcFIbR7n1j20EL20Y+yHAZrM Qxx1AgCpspnS4qH4z5UOqQohHTBgrbG/3w7ZblakF0evQyaGDExnGemo3P1uhgdPwx xqjH8L4Crrqsw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17F16E77188; Fri, 10 Jan 2025 05:39:56 +0000 (UTC) From: Ao Xu via B4 Relay Date: Fri, 10 Jan 2025 13:39:58 +0800 Subject: [PATCH 08/11] drm: meson: add hdmitx vmode timing support for S4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250110-drm-s4-v1-8-cbc2d5edaae8@amlogic.com> References: <20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com> In-Reply-To: <20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com> To: Neil Armstrong , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ao Xu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1736487593; l=13515; i=ao.xu@amlogic.com; s=20250103; h=from:subject:message-id; bh=LUyI3uauXSbgx+44CE2avmgLudmjXAgvYaFzCLYO4dg=; b=b2kywszPo9FhOjdnZxbuQsTAluRutnZmUFDo8KF25E1GNv4T2fnh6TLRqUPuHNDyIWq0QmpDX V6X75yGyvmcBlA/FWBI4oQ+m51rmR48NlnO1h29lGgrUh6URt0qzD/g X-Developer-Key: i=ao.xu@amlogic.com; a=ed25519; pk=c0TSXrwQuL4EhPVf3lJ676U27ax2yfFTqmRoseP/fA8= X-Endpoint-Received: by B4 Relay for ao.xu@amlogic.com/20250103 with auth_id=308 X-Original-From: Ao Xu Reply-To: ao.xu@amlogic.com From: Ao Xu Introduce support for HDMI TX video mode (vmode) timing in the Meson VENC driver for the Amlogic S4 SoC. These updates enable reliable HDMI output with correct timing for S4 devices. Signed-off-by: Ao Xu --- drivers/gpu/drm/meson/meson_venc.c | 334 +++++++++++++++++++++++++++++++++= +++- 1 file changed, 328 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/mes= on_venc.c index 5c461b27ae49317d8f430dc55606c8e11a536240..58e8e3bc854070ba152ee6dd4ab= de38ee1e28266 100644 --- a/drivers/gpu/drm/meson/meson_venc.c +++ b/drivers/gpu/drm/meson/meson_venc.c @@ -68,6 +68,12 @@ #define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbc offset in data sheet */ #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 offset in data sheet */ =20 +/* ANA Registers */ +#define CLKCTRL_SYS_CLK_EN0_REG2 0x04c /* 0x13 offset in data sheet */ +#define ANACTRL_HDMIPHY_CTRL0 0x200 /* 0x80 */ +#define ANACTRL_VDAC_CTRL0 0x2c0 /* 0xb0 offset in data sheet */ +#define ANACTRL_VDAC_CTRL1 0x2c4 /* 0xb1 offset in data sheet */ + struct meson_cvbs_enci_mode meson_cvbs_enci_pal =3D { .mode_tag =3D MESON_VENC_MODE_CVBS_PAL, .hso_begin =3D 3, @@ -228,6 +234,52 @@ static union meson_hdmi_venc_mode meson_hdmi_enci_mode= _576i =3D { }, }; =20 +static union meson_hdmi_venc_mode meson_s4_hdmi_encp_mode_480p =3D { + .encp =3D { + .dvi_settings =3D 0x21, + .video_mode =3D 0x4000, + .video_mode_adv =3D 0x8, + .video_prog_mode =3D 0, + .video_prog_mode_present =3D true, + .video_sync_mode =3D 7, + .video_sync_mode_present =3D true, + /* video_yc_dly */ + /* video_rgb_ctrl */ + .video_filt_ctrl =3D 0x2052, + .video_filt_ctrl_present =3D true, + /* video_ofld_voav_ofst */ + .yfp1_htime =3D 244, + .yfp2_htime =3D 1630, + .max_pxcnt =3D 857, + .hspuls_begin =3D 0x22, + .hspuls_end =3D 0xa0, + .hspuls_switch =3D 88, + .vspuls_begin =3D 0, + .vspuls_end =3D 1589, + .vspuls_bline =3D 0, + .vspuls_eline =3D 5, + .havon_begin =3D 122, + .havon_end =3D 841, + .vavon_bline =3D 36, + .vavon_eline =3D 515, + /* eqpuls_begin */ + /* eqpuls_end */ + /* eqpuls_bline */ + /* eqpuls_eline */ + .hso_begin =3D 0, + .hso_end =3D 62, + .vso_begin =3D 30, + .vso_end =3D 50, + .vso_bline =3D 0, + /* vso_eline */ + .sy_val =3D 8, + .sy_val_present =3D true, + .sy2_val =3D 0x1d8, + .sy2_val_present =3D true, + .max_lncnt =3D 524, + }, +}; + static union meson_hdmi_venc_mode meson_hdmi_encp_mode_480p =3D { .encp =3D { .dvi_settings =3D 0x21, @@ -320,6 +372,52 @@ static union meson_hdmi_venc_mode meson_hdmi_encp_mode= _576p =3D { }, }; =20 +static union meson_hdmi_venc_mode meson_s4_hdmi_encp_mode_576p =3D { + .encp =3D { + .dvi_settings =3D 0x21, + .video_mode =3D 0x4000, + .video_mode_adv =3D 0x8, + .video_prog_mode =3D 0, + .video_prog_mode_present =3D true, + .video_sync_mode =3D 7, + .video_sync_mode_present =3D true, + /* video_yc_dly */ + /* video_rgb_ctrl */ + .video_filt_ctrl =3D 0x52, + .video_filt_ctrl_present =3D true, + /* video_ofld_voav_ofst */ + .yfp1_htime =3D 235, + .yfp2_htime =3D 1674, + .max_pxcnt =3D 863, + .hspuls_begin =3D 0, + .hspuls_end =3D 0x80, + .hspuls_switch =3D 88, + .vspuls_begin =3D 0, + .vspuls_end =3D 1599, + .vspuls_bline =3D 0, + .vspuls_eline =3D 4, + .havon_begin =3D 132, + .havon_end =3D 851, + .vavon_bline =3D 44, + .vavon_eline =3D 619, + /* eqpuls_begin */ + /* eqpuls_end */ + /* eqpuls_bline */ + /* eqpuls_eline */ + .hso_begin =3D 0, + .hso_end =3D 64, + .vso_begin =3D 30, + .vso_end =3D 50, + .vso_bline =3D 5, + /* vso_eline */ + .sy_val =3D 8, + .sy_val_present =3D true, + .sy2_val =3D 0x1d8, + .sy2_val_present =3D true, + .max_lncnt =3D 624, + }, +}; + static union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p60 =3D { .encp =3D { .dvi_settings =3D 0x2029, @@ -362,6 +460,48 @@ static union meson_hdmi_venc_mode meson_hdmi_encp_mode= _720p60 =3D { }, }; =20 +static union meson_hdmi_venc_mode meson_s4_hdmi_encp_mode_720p60 =3D { + .encp =3D { + .dvi_settings =3D 0x2029, + .video_mode =3D 0x4040, + .video_mode_adv =3D 0x18, + /* video_prog_mode */ + /* video_sync_mode */ + /* video_yc_dly */ + /* video_rgb_ctrl */ + /* video_filt_ctrl */ + /* video_ofld_voav_ofst */ + .yfp1_htime =3D 648, + .yfp2_htime =3D 3207, + .max_pxcnt =3D 1649, + .hspuls_begin =3D 80, + .hspuls_end =3D 240, + .hspuls_switch =3D 80, + .vspuls_begin =3D 688, + .vspuls_end =3D 3248, + .vspuls_bline =3D 4, + .vspuls_eline =3D 8, + .havon_begin =3D 260, + .havon_end =3D 1539, + .vavon_bline =3D 29, + .vavon_eline =3D 749, + /* eqpuls_begin */ + /* eqpuls_end */ + /* eqpuls_bline */ + /* eqpuls_eline */ + .hso_begin =3D 0, + .hso_end =3D 168, + .vso_begin =3D 168, + .vso_end =3D 256, + .vso_bline =3D 0, + .vso_eline =3D 5, + .vso_eline_present =3D true, + /* sy_val */ + /* sy2_val */ + .max_lncnt =3D 749, + }, +}; + static union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p50 =3D { .encp =3D { .dvi_settings =3D 0x202d, @@ -407,6 +547,51 @@ static union meson_hdmi_venc_mode meson_hdmi_encp_mode= _720p50 =3D { }, }; =20 +static union meson_hdmi_venc_mode meson_s4_hdmi_encp_mode_720p50 =3D { + .encp =3D { + .dvi_settings =3D 0x202d, + .video_mode =3D 0x4040, + .video_mode_adv =3D 0x18, + .video_prog_mode =3D 0x100, + .video_prog_mode_present =3D true, + .video_sync_mode =3D 0x407, + .video_sync_mode_present =3D true, + .video_yc_dly =3D 0, + .video_yc_dly_present =3D true, + /* video_rgb_ctrl */ + /* video_filt_ctrl */ + /* video_ofld_voav_ofst */ + .yfp1_htime =3D 648, + .yfp2_htime =3D 3207, + .max_pxcnt =3D 1979, + .hspuls_begin =3D 80, + .hspuls_end =3D 240, + .hspuls_switch =3D 80, + .vspuls_begin =3D 688, + .vspuls_end =3D 3248, + .vspuls_bline =3D 4, + .vspuls_eline =3D 8, + .havon_begin =3D 260, + .havon_end =3D 1539, + .vavon_bline =3D 25, + .vavon_eline =3D 744, + /* eqpuls_begin */ + /* eqpuls_end */ + /* eqpuls_bline */ + /* eqpuls_eline */ + .hso_begin =3D 0, + .hso_end =3D 40, + .vso_begin =3D 30, + .vso_end =3D 50, + .vso_bline =3D 0, + .vso_eline =3D 5, + .vso_eline_present =3D true, + /* sy_val */ + /* sy2_val */ + .max_lncnt =3D 749, + }, +}; + static union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i60 =3D { .encp =3D { .dvi_settings =3D 0x2029, @@ -456,6 +641,55 @@ static union meson_hdmi_venc_mode meson_hdmi_encp_mode= _1080i60 =3D { }, }; =20 +static union meson_hdmi_venc_mode meson_s4_hdmi_encp_mode_1080i60 =3D { + .encp =3D { + .dvi_settings =3D 0x2029, + .video_mode =3D 0x5ffc, + .video_mode_adv =3D 0x18, + .video_prog_mode =3D 0x100, + .video_prog_mode_present =3D true, + .video_sync_mode =3D 0x207, + .video_sync_mode_present =3D true, + /* video_yc_dly */ + /* video_rgb_ctrl */ + /* video_filt_ctrl */ + .video_ofld_voav_ofst =3D 0x11, + .video_ofld_voav_ofst_present =3D true, + .yfp1_htime =3D 516, + .yfp2_htime =3D 4355, + .max_pxcnt =3D 2199, + .hspuls_begin =3D 88, + .hspuls_end =3D 264, + .hspuls_switch =3D 88, + .vspuls_begin =3D 440, + .vspuls_end =3D 2200, + .vspuls_bline =3D 0, + .vspuls_eline =3D 4, + .havon_begin =3D 192, + .havon_end =3D 2111, + .vavon_bline =3D 20, + .vavon_eline =3D 559, + .eqpuls_begin =3D 2288, + .eqpuls_begin_present =3D true, + .eqpuls_end =3D 2464, + .eqpuls_end_present =3D true, + .eqpuls_bline =3D 0, + .eqpuls_bline_present =3D true, + .eqpuls_eline =3D 4, + .eqpuls_eline_present =3D true, + .hso_begin =3D 0, + .hso_end =3D 44, + .vso_begin =3D 30, + .vso_end =3D 50, + .vso_bline =3D 0, + .vso_eline =3D 5, + .vso_eline_present =3D true, + /* sy_val */ + /* sy2_val */ + .max_lncnt =3D 1124, + }, +}; + static union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i50 =3D { .encp =3D { .dvi_settings =3D 0x202d, @@ -505,6 +739,55 @@ static union meson_hdmi_venc_mode meson_hdmi_encp_mode= _1080i50 =3D { }, }; =20 +static union meson_hdmi_venc_mode meson_s4_hdmi_encp_mode_1080i50 =3D { + .encp =3D { + .dvi_settings =3D 0x202d, + .video_mode =3D 0x5ffc, + .video_mode_adv =3D 0x18, + .video_prog_mode =3D 0x100, + .video_prog_mode_present =3D true, + .video_sync_mode =3D 0x7, + .video_sync_mode_present =3D true, + /* video_yc_dly */ + /* video_rgb_ctrl */ + /* video_filt_ctrl */ + .video_ofld_voav_ofst =3D 0x11, + .video_ofld_voav_ofst_present =3D true, + .yfp1_htime =3D 526, + .yfp2_htime =3D 4365, + .max_pxcnt =3D 2639, + .hspuls_begin =3D 88, + .hspuls_end =3D 264, + .hspuls_switch =3D 88, + .vspuls_begin =3D 440, + .vspuls_end =3D 2200, + .vspuls_bline =3D 0, + .vspuls_eline =3D 4, + .havon_begin =3D 192, + .havon_end =3D 2111, + .vavon_bline =3D 20, + .vavon_eline =3D 559, + .eqpuls_begin =3D 2288, + .eqpuls_begin_present =3D true, + .eqpuls_end =3D 2464, + .eqpuls_end_present =3D true, + .eqpuls_bline =3D 0, + .eqpuls_bline_present =3D true, + .eqpuls_eline =3D 4, + .eqpuls_eline_present =3D true, + .hso_begin =3D 0, + .hso_end =3D 44, + .vso_begin =3D 30, + .vso_end =3D 50, + .vso_bline =3D 0, + .vso_eline =3D 5, + .vso_eline_present =3D true, + /* sy_val */ + /* sy2_val */ + .max_lncnt =3D 1124, + }, +}; + static union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p24 =3D { .encp =3D { .dvi_settings =3D 0xd, @@ -816,10 +1099,12 @@ static union meson_hdmi_venc_mode meson_hdmi_encp_mo= de_2160p30 =3D { }, }; =20 -static struct meson_hdmi_venc_vic_mode { +struct meson_hdmi_venc_vic_mode { unsigned int vic; union meson_hdmi_venc_mode *mode; -} meson_hdmi_venc_vic_modes[] =3D { +}; + +static struct meson_hdmi_venc_vic_mode meson_hdmi_venc_vic_modes[] =3D { { 6, &meson_hdmi_enci_mode_480i }, { 7, &meson_hdmi_enci_mode_480i }, { 21, &meson_hdmi_enci_mode_576i }, @@ -845,6 +1130,23 @@ static struct meson_hdmi_venc_vic_mode { { 0, NULL}, /* sentinel */ }; =20 +static struct meson_hdmi_venc_vic_mode meson_s4_hdmi_venc_vic_modes[] =3D { + { 2, &meson_s4_hdmi_encp_mode_480p }, + { 3, &meson_s4_hdmi_encp_mode_480p }, + { 17, &meson_s4_hdmi_encp_mode_576p }, + { 18, &meson_s4_hdmi_encp_mode_576p }, + { 4, &meson_s4_hdmi_encp_mode_720p60 }, + { 19, &meson_s4_hdmi_encp_mode_720p50 }, + { 5, &meson_s4_hdmi_encp_mode_1080i60 }, + { 20, &meson_s4_hdmi_encp_mode_1080i50 }, + { 32, &meson_hdmi_encp_mode_1080p24 }, + { 33, &meson_hdmi_encp_mode_1080p50 }, + { 34, &meson_hdmi_encp_mode_1080p30 }, + { 31, &meson_hdmi_encp_mode_1080p50 }, + { 16, &meson_hdmi_encp_mode_1080p60 }, + { 0, NULL}, /* sentinel */ +}; + static signed int to_signed(unsigned int a) { if (a <=3D 7) @@ -882,6 +1184,9 @@ bool meson_venc_hdmi_supported_vic(struct meson_drm *p= riv, int vic) { struct meson_hdmi_venc_vic_mode *vmode =3D meson_hdmi_venc_vic_modes; =20 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) + vmode =3D meson_s4_hdmi_venc_vic_modes; + while (vmode->vic && vmode->mode) { if (vmode->vic =3D=3D vic) return true; @@ -921,6 +1226,9 @@ static union meson_hdmi_venc_mode *meson_venc_hdmi_get= _vic_vmode(struct meson_dr { struct meson_hdmi_venc_vic_mode *vmode =3D meson_hdmi_venc_vic_modes; =20 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) + vmode =3D meson_s4_hdmi_venc_vic_modes; + while (vmode->vic && vmode->mode) { if (vmode->vic =3D=3D vic) return vmode->mode; @@ -932,6 +1240,8 @@ static union meson_hdmi_venc_mode *meson_venc_hdmi_get= _vic_vmode(struct meson_dr =20 bool meson_venc_hdmi_venc_repeat(struct meson_drm *priv, int vic) { + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) + return false; /* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */ if (vic =3D=3D 6 || vic =3D=3D 7 || /* 480i */ vic =3D=3D 21 || vic =3D=3D 22 || /* 576i */ @@ -1957,12 +2267,19 @@ void meson_venc_enable_vsync(struct meson_drm *priv) writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN, priv->io_base + _REG(VENC_INTCTRL)); } - regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25)); + + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) + regmap_update_bits(priv->clkctrl, CLKCTRL_SYS_CLK_EN0_REG2, BIT(4), BIT(= 4)); + else + regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25)); } =20 void meson_venc_disable_vsync(struct meson_drm *priv) { - regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0); + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) + regmap_update_bits(priv->clkctrl, CLKCTRL_SYS_CLK_EN0_REG2, BIT(4), 0); + else + regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0); writel_relaxed(0, priv->io_base + _REG(VENC_INTCTRL)); } =20 @@ -1972,6 +2289,9 @@ void meson_venc_init(struct meson_drm *priv) if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0); regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 8); + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { + regmap_write(priv->hhi, ANACTRL_VDAC_CTRL0, 0); + regmap_write(priv->hhi, ANACTRL_VDAC_CTRL1, 8); } else { regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0); regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8); @@ -1981,8 +2301,10 @@ void meson_venc_init(struct meson_drm *priv) writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING)); =20 /* Disable HDMI PHY */ - regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0); - + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) + regmap_write(priv->hhi, ANACTRL_HDMIPHY_CTRL0, 0); + else + regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0); /* Disable HDMI */ writel_bits_relaxed(VPU_HDMI_ENCI_DATA_TO_HDMI | VPU_HDMI_ENCP_DATA_TO_HDMI, 0, --=20 2.43.0 From nobody Sun Feb 8 15:46:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D2C92066D9; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="d2Qk3eO1" Received: by smtp.kernel.org (Postfix) with ESMTPS id 324BCC4CED6; Fri, 10 Jan 2025 05:39:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736487596; bh=A4KxmvopAA+Hm/kYNJV9mPMn0fwfIEGmJrGcIKh2zkI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=d2Qk3eO1hUR2UYk8mN/k52zAtcs6G4Fud5/iQ0jM2KOEMEl5HofUHpjTWZDpTRYax IFjzxq7vAn3fF4CdW4g/a8Qab9W18XwfTmo8CR+BFI7bbZBHKSwABEvfS6egPqByXO R9rrPZ0qSc85x1PVKcgJeiuEgMzd96vZntQ0s0xjX3Jbs5H+Ur18KY7hTZMxvOWeQz JKJqc8i1kHyJwmxbnFMc7IIAXo2h0eB4y9ZDe6H+c1ETzhE2uJckOzI16DftzVc4nD XyCGWnHxq0lbispcACobtjadg1GjHznOyNvBftd2ZpXx9z00Ha5H1Fy4pWyBQXyJp+ ouuPVMa1sW36Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BB8EE7719D; Fri, 10 Jan 2025 05:39:56 +0000 (UTC) From: Ao Xu via B4 Relay Date: Fri, 10 Jan 2025 13:39:59 +0800 Subject: [PATCH 09/11] drm: meson: add vpu clk setting for S4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250110-drm-s4-v1-9-cbc2d5edaae8@amlogic.com> References: <20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com> In-Reply-To: <20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com> To: Neil Armstrong , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ao Xu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1736487593; l=43875; i=ao.xu@amlogic.com; s=20250103; h=from:subject:message-id; bh=f6o59xzgL5AIXyJBq/G+Mt5LS+R9oNyy1GZNtQlTZRg=; b=2Hn5s539SFAvUsFAS1lBuCgh2BvSs3dZcYAgI/uf1nyd/4PNtzejCxAe81oJGmSnaps+MJmXv wz8gCF/dFUqCVUDsmlgMi8Qehr434Q8crDwbrpxjT0QSp6GGmFg+fIT X-Developer-Key: i=ao.xu@amlogic.com; a=ed25519; pk=c0TSXrwQuL4EhPVf3lJ676U27ax2yfFTqmRoseP/fA8= X-Endpoint-Received: by B4 Relay for ao.xu@amlogic.com/20250103 with auth_id=308 X-Original-From: Ao Xu Reply-To: ao.xu@amlogic.com From: Ao Xu The S4-series splits the HIU into `sys_ctrl`, `pwr_ctrl`, and `clk_ctrl`. Introduce VPU clock settings specific to the Amlogic S4 SoC, which differ from the configurations used for G12. Signed-off-by: Ao Xu --- drivers/gpu/drm/meson/meson_vclk.c | 1018 +++++++++++++++++++++++++-------= ---- 1 file changed, 720 insertions(+), 298 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/mes= on_vclk.c index 2a942dc6a6dc23561ec26a54139b27acf8009ccb..b2707af2a5283874936658d2749= cecb4ef86beb5 100644 --- a/drivers/gpu/drm/meson/meson_vclk.c +++ b/drivers/gpu/drm/meson/meson_vclk.c @@ -87,8 +87,11 @@ #define CTS_VDAC_EN BIT(4) #define HDMI_TX_PIXEL_EN BIT(5) #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */ -#define HDMI_TX_PIXEL_SEL_MASK (0xf << 16) +#define HDMI_TX_PIXEL_SEL_MASK GENMASK(19, 16) #define HDMI_TX_PIXEL_SEL_SHIFT 16 + +#define HDMI_TX_FE_SEL_MASK GENMASK(23, 20) +#define HDMI_TX_FE_SEL_SHIFT 20 #define CTS_HDMI_SYS_SEL_MASK (0x7 << 9) #define CTS_HDMI_SYS_DIV_MASK (0x7f) #define CTS_HDMI_SYS_EN BIT(8) @@ -110,6 +113,30 @@ #define HDMI_PLL_LOCK BIT(31) #define HDMI_PLL_LOCK_G12A (3 << 30) =20 +/* ANA Registers */ +/* REG_BASE: REGISTER_BASE_ADDR =3D 0xfe000000 */ +#define CLKCTRL_VID_CLK_CTRL 0x0c0 /* 0x30 offset in data sheet */ +#define CLKCTRL_VID_CLK_CTRL2 0x0c4 /* 0x31 offset in data sheet */ +#define CLKCTRL_VID_CLK_DIV 0x0c8 /* 0x32 offset in data sheet */ +#define CLKCTRL_VIID_CLK_DIV 0x0cc /* 0x33 offset in data sheet */ +#define CLKCTRL_VIID_CLK_CTRL 0x0d0 /* 0x34 offset in data sheet */ + +#define CLKCTRL_VID_PLL_CLK_DIV 0x0e4 /* 0x39 offset in data sheet */ +#define CLKCTRL_HDMI_CLK_CTRL 0x0e0 /* 0x38 */ + +/* REG_BASE: REGISTER_BASE_ADDR =3D 0xfe008000 */ +#define ANACTRL_HDMIPLL_CTRL0 0x1c0 /* 0x70 offset in data sheet */ +#define ANACTRL_HDMIPLL_CTRL1 0x1c4 /* 0x71 offset in data sheet */ +#define ANACTRL_HDMIPLL_CTRL2 0x1c8 /* 0x72 offset in data sheet */ +#define ANACTRL_HDMIPLL_CTRL3 0x1cc /* 0x73 offset in data sheet */ +#define ANACTRL_HDMIPLL_CTRL4 0x1d0 /* 0x74 offset in data sheet */ +#define ANACTRL_HDMIPLL_CTRL5 0x1d4 /* 0x75 offset in data sheet */ +#define ANACTRL_HDMIPLL_CTRL6 0x1d8 /* 0x76 offset in data sheet */ +#define ANACTRL_HDMIPLL_STS 0x1dc /* 0x77 offset in data sheet */ +#define ANACTRL_HDMIPLL_VLOCK 0x1e4 /* 0x79 offset in data sheet */ +#define HDMI_PLL_RESET_S4 BIT(29) +#define HDMI_PLL_LOCK_S4 (3 << 30) + #define FREQ_1000_1001(_freq) DIV_ROUND_CLOSEST(_freq * 1000, 1001) =20 /* VID PLL Dividers */ @@ -137,8 +164,13 @@ static void meson_vid_pll_set(struct meson_drm *priv, = unsigned int div) unsigned int shift_sel =3D 0; =20 /* Disable vid_pll output clock */ - regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0); - regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0); + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV, VID_PLL_EN, 0= ); + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV, VID_PLL_PRESE= T, 0); + } else { + regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0); + regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0); + } =20 switch (div) { case VID_PLL_DIV_2: @@ -199,37 +231,71 @@ static void meson_vid_pll_set(struct meson_drm *priv,= unsigned int div) break; } =20 - if (div =3D=3D VID_PLL_DIV_1) - /* Enable vid_pll bypass to HDMI pll */ - regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, - VID_PLL_BYPASS, VID_PLL_BYPASS); - else { - /* Disable Bypass */ - regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, - VID_PLL_BYPASS, 0); - /* Clear sel */ - regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, - 3 << 16, 0); - regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, - VID_PLL_PRESET, 0); - regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, - 0x7fff, 0); + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { + if (div =3D=3D VID_PLL_DIV_1) { + /* Enable vid_pll bypass to HDMI pll */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV, + VID_PLL_BYPASS, VID_PLL_BYPASS); + } else { + /* Disable Bypass */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV, + VID_PLL_BYPASS, 0); + /* Clear sel */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV, + 3 << 16, 0); + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV, + VID_PLL_PRESET, 0); + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV, + 0x7fff, 0); + + /* Setup sel and val */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV, + 3 << 16, shift_sel << 16); + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV, + VID_PLL_PRESET, VID_PLL_PRESET); + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV, + 0x7fff, shift_val); + + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV, + VID_PLL_PRESET, 0); + } =20 - /* Setup sel and val */ - regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, - 3 << 16, shift_sel << 16); - regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, - VID_PLL_PRESET, VID_PLL_PRESET); - regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, - 0x7fff, shift_val); + /* Enable the vid_pll output clock */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_PLL_CLK_DIV, + VID_PLL_EN, VID_PLL_EN); + } else { + if (div =3D=3D VID_PLL_DIV_1) { + /* Enable vid_pll bypass to HDMI pll */ + regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, + VID_PLL_BYPASS, VID_PLL_BYPASS); + } else { + /* Disable Bypass */ + regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, + VID_PLL_BYPASS, 0); + /* Clear sel */ + regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, + 3 << 16, 0); + regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, + VID_PLL_PRESET, 0); + regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, + 0x7fff, 0); + + /* Setup sel and val */ + regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, + 3 << 16, shift_sel << 16); + regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, + VID_PLL_PRESET, VID_PLL_PRESET); + regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, + 0x7fff, shift_val); + + regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, + VID_PLL_PRESET, 0); + } =20 + /* Enable the vid_pll output clock */ regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, - VID_PLL_PRESET, 0); + VID_PLL_EN, VID_PLL_EN); } - - /* Enable the vid_pll output clock */ - regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, - VID_PLL_EN, VID_PLL_EN); } =20 /* @@ -287,56 +353,117 @@ static void meson_venci_cvbs_clock_config(struct mes= on_drm *priv) regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, ((val & HDMI_PLL_LOCK_G12A) =3D=3D HDMI_PLL_LOCK_G12A), 10, 0); + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { + regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL0, 0x3b01047b); + regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL1, 0x00018000); + regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL2, 0x00000000); + regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL3, 0x0a691c00); + regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL4, 0x33771290); + regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL5, 0x39270000); + regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL6, 0x50540000); + regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL0, 0x1b01047b); + + /* Poll for lock bit */ + regmap_read_poll_timeout(priv->hhi, ANACTRL_HDMIPLL_CTRL0, val, + ((val & HDMI_PLL_LOCK) =3D=3D HDMI_PLL_LOCK), + 10, 0); } + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { + /* Disable VCLK2 */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VIID_CLK_CTRL, VCLK2_EN, 0); =20 - /* Disable VCLK2 */ - regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0); + /* Setup vid_pll to /1 */ + meson_vid_pll_set(priv, VID_PLL_DIV_1); =20 - /* Setup vid_pll to /1 */ - meson_vid_pll_set(priv, VID_PLL_DIV_1); + /* Setup the VCLK2 divider value to achieve 27MHz */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VIID_CLK_DIV, + VCLK2_DIV_MASK, (55 - 1)); =20 - /* Setup the VCLK2 divider value to achieve 27MHz */ - regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, - VCLK2_DIV_MASK, (55 - 1)); + /* select vid_pll for vclk2 */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VIID_CLK_CTRL, + VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); =20 - /* select vid_pll for vclk2 */ - if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) + /* enable vclk2 gate */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VIID_CLK_CTRL, VCLK2_EN, VCLK2= _EN); + + /* select vclk_div1 for enci */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV, + CTS_ENCI_SEL_MASK, (8 << CTS_ENCI_SEL_SHIFT)); + /* select vclk_div1 for vdac */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VIID_CLK_DIV, + CTS_VDAC_SEL_MASK, (8 << CTS_VDAC_SEL_SHIFT)); + + /* release vclk2_div_reset and enable vclk2_div */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VIID_CLK_DIV, + VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN); + + /* enable vclk2_div1 gate */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VIID_CLK_CTRL, + VCLK2_DIV1_EN, VCLK2_DIV1_EN); + + /* reset vclk2 */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VIID_CLK_CTRL, + VCLK2_SOFT_RESET, VCLK2_SOFT_RESET); + regmap_update_bits(priv->clkctrl, CLKCTRL_VIID_CLK_CTRL, + VCLK2_SOFT_RESET, 0); + + /* enable enci_clk */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL2, + CTS_ENCI_EN, CTS_ENCI_EN); + /* enable vdac_clk */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL2, + CTS_VDAC_EN, CTS_VDAC_EN); + + } else { + /* Disable VCLK2 */ + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0); + + /* Setup vid_pll to /1 */ + meson_vid_pll_set(priv, VID_PLL_DIV_1); + + /* Setup the VCLK2 divider value to achieve 27MHz */ + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, + VCLK2_DIV_MASK, (55 - 1)); + + /* select vid_pll for vclk2 */ + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, + VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); + else + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, + VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); + + /* enable vclk2 gate */ + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN); + + /* select vclk_div1 for enci */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, + CTS_ENCI_SEL_MASK, (8 << CTS_ENCI_SEL_SHIFT)); + /* select vclk_div1 for vdac */ + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, + CTS_VDAC_SEL_MASK, (8 << CTS_VDAC_SEL_SHIFT)); + + /* release vclk2_div_reset and enable vclk2_div */ + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, + VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN); + + /* enable vclk2_div1 gate */ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, - VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); - else + VCLK2_DIV1_EN, VCLK2_DIV1_EN); + + /* reset vclk2 */ + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, + VCLK2_SOFT_RESET, VCLK2_SOFT_RESET); regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, - VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); - - /* enable vclk2 gate */ - regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN); - - /* select vclk_div1 for enci */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, - CTS_ENCI_SEL_MASK, (8 << CTS_ENCI_SEL_SHIFT)); - /* select vclk_div1 for vdac */ - regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, - CTS_VDAC_SEL_MASK, (8 << CTS_VDAC_SEL_SHIFT)); - - /* release vclk2_div_reset and enable vclk2_div */ - regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, - VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN); - - /* enable vclk2_div1 gate */ - regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, - VCLK2_DIV1_EN, VCLK2_DIV1_EN); - - /* reset vclk2 */ - regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, - VCLK2_SOFT_RESET, VCLK2_SOFT_RESET); - regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, - VCLK2_SOFT_RESET, 0); - - /* enable enci_clk */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, - CTS_ENCI_EN, CTS_ENCI_EN); - /* enable vdac_clk */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, - CTS_VDAC_EN, CTS_VDAC_EN); + VCLK2_SOFT_RESET, 0); + + /* enable enci_clk */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, + CTS_ENCI_EN, CTS_ENCI_EN); + /* enable vdac_clk */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, + CTS_VDAC_EN, CTS_VDAC_EN); + } } =20 enum { @@ -357,6 +484,8 @@ enum { MESON_VCLK_HDMI_594000, /* 2970 /1 /1 /1 /5 /1 =3D> /1 /2 */ MESON_VCLK_HDMI_594000_YUV420, +/* 4320 /4 /4 /1 /5 /1 =3D> /2 /2 */ + MESON_VCLK_HDMI_27000, }; =20 struct meson_vclk_params { @@ -467,6 +596,18 @@ struct meson_vclk_params { .vid_pll_div =3D VID_PLL_DIV_5, .vclk_div =3D 1, }, + [MESON_VCLK_HDMI_27000] =3D { + .pll_freq =3D 4320000, + .phy_freq =3D 270000, + .vclk_freq =3D 54000, + .venc_freq =3D 27000, + .pixel_freq =3D 27000, + .pll_od1 =3D 4, + .pll_od2 =3D 4, + .pll_od3 =3D 1, + .vid_pll_div =3D VID_PLL_DIV_5, + .vclk_div =3D 1, + }, { /* sentinel */ }, }; =20 @@ -487,136 +628,226 @@ static inline unsigned int pll_od_to_reg(unsigned i= nt od) return 0; } =20 -static void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int= m, +static void gxbb_pll_set_params(struct meson_drm *priv, unsigned int m, unsigned int frac, unsigned int od1, unsigned int od2, unsigned int od3) { unsigned int val; =20 - if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) { - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000200 | m); - if (frac) - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, - 0x00004000 | frac); - else - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, - 0x00000000); - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091); - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c); - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980); - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000200 | m); + if (frac) + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, + 0x00004000 | frac); + else + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, + 0x00000000); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55); + + /* Enable and unreset */ + regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, + 0x7 << 28, HHI_HDMI_PLL_CNTL_EN); + + /* Poll for lock bit */ + regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, + val, (val & HDMI_PLL_LOCK), 10, 0); + + regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, + 3 << 16, pll_od_to_reg(od1) << 16); + regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, + 3 << 22, pll_od_to_reg(od2) << 22); + regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, + 3 << 18, pll_od_to_reg(od3) << 18); +} =20 - /* Enable and unreset */ - regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, - 0x7 << 28, HHI_HDMI_PLL_CNTL_EN); +static void gxm_pll_set_params(struct meson_drm *priv, unsigned int m, + unsigned int frac, unsigned int od1, + unsigned int od2, unsigned int od3) +{ + unsigned int val; =20 - /* Poll for lock bit */ - regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, - val, (val & HDMI_PLL_LOCK), 10, 0); - } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || - meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) { - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000200 | m); - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac); - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4); - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000); - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729); - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000200 | m); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500); =20 - /* Reset PLL */ - regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, - HDMI_PLL_RESET, HDMI_PLL_RESET); - regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, - HDMI_PLL_RESET, 0); + /* Reset PLL */ + regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, + HDMI_PLL_RESET, HDMI_PLL_RESET); + regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, + HDMI_PLL_RESET, 0); =20 - /* Poll for lock bit */ - regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, - (val & HDMI_PLL_LOCK), 10, 0); - } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x0b3a0400 | m); + /* Poll for lock bit */ + regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, + (val & HDMI_PLL_LOCK), 10, 0); =20 - /* Enable and reset */ - /* TODO: add specific macro for g12a here */ - regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, - 0x3 << 28, 0x3 << 28); + regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, + 3 << 21, pll_od_to_reg(od1) << 21); + regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, + 3 << 23, pll_od_to_reg(od2) << 23); + regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, + 3 << 19, pll_od_to_reg(od3) << 19); +} =20 - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, frac); - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x00000000); +static void g12a_pll_set_params(struct meson_drm *priv, unsigned int m, + unsigned int frac, unsigned int od1, + unsigned int od2, unsigned int od3) +{ + unsigned int val; + + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x0b3a0400 | m); + + /* Enable and reset */ + /* TODO: add specific macro for g12a here */ + regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, + 0x3 << 28, 0x3 << 28); =20 - /* G12A HDMI PLL Needs specific parameters for 5.4GHz */ - if (m >=3D 0xf7) { - if (frac < 0x10000) { - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, - 0x6a685c00); - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, - 0x11551293); - } else { - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, - 0xea68dc00); - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, - 0x65771290); - } - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000); - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x55540000); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, frac); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x00000000); + + /* G12A HDMI PLL Needs specific parameters for 5.4GHz */ + if (m >=3D 0xf7) { + if (frac < 0x10000) { + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, + 0x6a685c00); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, + 0x11551293); } else { - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0a691c00); - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x33771290); - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39270000); - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x50540000); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, + 0xea68dc00); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, + 0x65771290); } - - do { - /* Reset PLL */ - regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, - HDMI_PLL_RESET_G12A, HDMI_PLL_RESET_G12A); - - /* UN-Reset PLL */ - regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, - HDMI_PLL_RESET_G12A, 0); - - /* Poll for lock bits */ - if (!regmap_read_poll_timeout(priv->hhi, - HHI_HDMI_PLL_CNTL, val, - ((val & HDMI_PLL_LOCK_G12A) - =3D=3D HDMI_PLL_LOCK_G12A), - 10, 100)) - break; - } while(1); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x55540000); + } else { + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0a691c00); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x33771290); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39270000); + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x50540000); } =20 - if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) - regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, - 3 << 16, pll_od_to_reg(od1) << 16); - else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || - meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) - regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, - 3 << 21, pll_od_to_reg(od1) << 21); - else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) + do { + /* Reset PLL */ regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, - 3 << 16, pll_od_to_reg(od1) << 16); + HDMI_PLL_RESET_G12A, HDMI_PLL_RESET_G12A); =20 - if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) - regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, - 3 << 22, pll_od_to_reg(od2) << 22); - else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || - meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) - regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, - 3 << 23, pll_od_to_reg(od2) << 23); - else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) + /* UN-Reset PLL */ regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, - 3 << 18, pll_od_to_reg(od2) << 18); + HDMI_PLL_RESET_G12A, 0); + + /* Poll for lock bits */ + if (!regmap_read_poll_timeout(priv->hhi, + HHI_HDMI_PLL_CNTL, val, + ((val & HDMI_PLL_LOCK_G12A) + =3D=3D HDMI_PLL_LOCK_G12A), + 10, 100)) + break; + } while (1); =20 - if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) - regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, - 3 << 18, pll_od_to_reg(od3) << 18); - else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || - meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) - regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, - 3 << 19, pll_od_to_reg(od3) << 19); - else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) - regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, + regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, + 3 << 16, pll_od_to_reg(od1) << 16); + regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, + 3 << 18, pll_od_to_reg(od2) << 18); + regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, + 3 << 20, pll_od_to_reg(od3) << 20); +} + +static void s4_pll_set_params(struct meson_drm *priv, unsigned int m, + unsigned int frac, unsigned int od1, + unsigned int od2, unsigned int od3) +{ + unsigned int val; + + DRM_DEBUG_DRIVER("%s: m =3D %d, frac =3D %d, od1 =3D %d, od2 =3D %d, od3 = =3D %d\n", + __func__, m, frac, od1, od2, od3); + + regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL0, 0x0b3a0400 | m); + + /* Enable and reset */ + /* TODO: add specific macro for g12a here */ + regmap_update_bits(priv->hhi, ANACTRL_HDMIPLL_CTRL0, + 0x3 << 28, 0x3 << 28); + + regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL1, frac); + regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL2, 0x00000000); + + /* S4 HDMI PLL Needs specific parameters for 5.4GHz */ + if (m >=3D 0xf7) { + if (frac < 0x10000) { + regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL3, + 0x6a685c00); + regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL4, + 0x11551293); + } else { + regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL3, + 0x6a685c00); + regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL4, + 0x44331290); + } + regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL5, 0x39272008); + regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL6, 0x56540000); + } else { + regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL3, 0x6a68dc00); + regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL4, 0x65771290); + regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL5, 0x39272008); + regmap_write(priv->hhi, ANACTRL_HDMIPLL_CTRL6, 0x56540000); + } + + do { + //todo, need confir rst and lock bit + /* Reset PLL */ + regmap_update_bits(priv->hhi, ANACTRL_HDMIPLL_CTRL0, + HDMI_PLL_RESET_S4, HDMI_PLL_RESET_S4); + + /* UN-Reset PLL */ + regmap_update_bits(priv->hhi, ANACTRL_HDMIPLL_CTRL0, + HDMI_PLL_RESET_S4, 0); + + /* Poll for lock bits */ + if (!regmap_read_poll_timeout(priv->hhi, + ANACTRL_HDMIPLL_CTRL0, val, + ((val & HDMI_PLL_LOCK_S4) + =3D=3D HDMI_PLL_LOCK_S4), + 10, 100)) + break; + } while (1); + + regmap_update_bits(priv->hhi, ANACTRL_HDMIPLL_CTRL0, + 3 << 16, pll_od_to_reg(od1) << 16); + regmap_update_bits(priv->hhi, ANACTRL_HDMIPLL_CTRL0, + 3 << 18, pll_od_to_reg(od2) << 18); + regmap_update_bits(priv->hhi, ANACTRL_HDMIPLL_CTRL0, 3 << 20, pll_od_to_reg(od3) << 20); } =20 +static void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int= m, + unsigned int frac, unsigned int od1, + unsigned int od2, unsigned int od3) +{ + switch (priv->compat) { + case VPU_COMPATIBLE_GXBB: + gxbb_pll_set_params(priv, m, frac, od1, od2, od3); + break; + case VPU_COMPATIBLE_GXM: + case VPU_COMPATIBLE_GXL: + gxm_pll_set_params(priv, m, frac, od1, od2, od3); + break; + case VPU_COMPATIBLE_G12A: + g12a_pll_set_params(priv, m, frac, od1, od2, od3); + break; + case VPU_COMPATIBLE_S4: + s4_pll_set_params(priv, m, frac, od1, od2, od3); + break; + default: + break; + } +} + #define XTAL_FREQ 24000 =20 static unsigned int meson_hdmi_pll_get_m(struct meson_drm *priv, @@ -632,6 +863,7 @@ static unsigned int meson_hdmi_pll_get_m(struct meson_d= rm *priv, #define HDMI_FRAC_MAX_GXBB 4096 #define HDMI_FRAC_MAX_GXL 1024 #define HDMI_FRAC_MAX_G12A 131072 +#define HDMI_FRAC_MAX_S4 131072 =20 static unsigned int meson_hdmi_pll_get_frac(struct meson_drm *priv, unsigned int m, @@ -651,6 +883,9 @@ static unsigned int meson_hdmi_pll_get_frac(struct meso= n_drm *priv, if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) frac_max =3D HDMI_FRAC_MAX_G12A; =20 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) + frac_max =3D HDMI_FRAC_MAX_S4; + /* We can have a perfect match !*/ if (pll_freq / m =3D=3D parent_freq && pll_freq % m =3D=3D 0) @@ -688,6 +923,12 @@ static bool meson_hdmi_pll_validate_params(struct meso= n_drm *priv, return false; if (frac >=3D HDMI_FRAC_MAX_G12A) return false; + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { + /* Empiric supported min/max dividers */ + if (m < 106 || m > 247) + return false; + if (frac >=3D HDMI_FRAC_MAX_S4) + return false; } =20 return true; @@ -813,14 +1054,22 @@ static void meson_vclk_set(struct meson_drm *priv, u= nsigned int pll_base_freq, { unsigned int m =3D 0, frac =3D 0; =20 - /* Set HDMI-TX sys clock */ - regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, - CTS_HDMI_SYS_SEL_MASK, 0); - regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, - CTS_HDMI_SYS_DIV_MASK, 0); - regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, - CTS_HDMI_SYS_EN, CTS_HDMI_SYS_EN); - + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { + regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL, + CTS_HDMI_SYS_SEL_MASK, 0); + regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL, + CTS_HDMI_SYS_DIV_MASK, 0); + regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL, + CTS_HDMI_SYS_EN, CTS_HDMI_SYS_EN); + } else { + /* Set HDMI-TX sys clock */ + regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, + CTS_HDMI_SYS_SEL_MASK, 0); + regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, + CTS_HDMI_SYS_DIV_MASK, 0); + regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, + CTS_HDMI_SYS_EN, CTS_HDMI_SYS_EN); + } /* Set HDMI PLL rate */ if (!od1 && !od2 && !od3) { meson_hdmi_pll_generic_set(priv, pll_base_freq); @@ -875,6 +1124,22 @@ static void meson_vclk_set(struct meson_drm *priv, un= signed int pll_base_freq, break; } =20 + meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3); + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { + switch (pll_base_freq) { + case 2970000: + m =3D 0x7b; + frac =3D vic_alternate_clock ? 0x140b4 : 0x18000; + break; + case 4320000: + m =3D vic_alternate_clock ? 0xb3 : 0xb4; + frac =3D vic_alternate_clock ? 0x1a3ee : 0; + break; + case 5940000: + m =3D 0xf7; + frac =3D vic_alternate_clock ? 0x8148 : 0x10000; + break; + } meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3); } =20 @@ -882,146 +1147,303 @@ static void meson_vclk_set(struct meson_drm *priv,= unsigned int pll_base_freq, meson_vid_pll_set(priv, vid_pll_div); =20 /* Set VCLK div */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, - VCLK_SEL_MASK, 0); - regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, - VCLK_DIV_MASK, vclk_div - 1); + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL, + VCLK_SEL_MASK, 0); + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV, + VCLK_DIV_MASK, vclk_div - 1); + } else { + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, + VCLK_SEL_MASK, 0); + regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, + VCLK_DIV_MASK, vclk_div - 1); + } =20 /* Set HDMI-TX source */ switch (hdmi_tx_div) { case 1: - /* enable vclk_div1 gate */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, - VCLK_DIV1_EN, VCLK_DIV1_EN); + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { + /* enable vclk_div1 gate */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL, + VCLK_DIV1_EN, VCLK_DIV1_EN); + + /* select vclk_div1 for HDMI-TX */ + regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL, + HDMI_TX_PIXEL_SEL_MASK, 0); + regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL, + HDMI_TX_FE_SEL_MASK, 0); + } else { + /* enable vclk_div1 gate */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, + VCLK_DIV1_EN, VCLK_DIV1_EN); =20 - /* select vclk_div1 for HDMI-TX */ - regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, - HDMI_TX_PIXEL_SEL_MASK, 0); + /* select vclk_div1 for HDMI-TX */ + regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, + HDMI_TX_PIXEL_SEL_MASK, 0); + } break; case 2: - /* enable vclk_div2 gate */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, - VCLK_DIV2_EN, VCLK_DIV2_EN); + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { + /* enable vclk_div2 gate */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL, + VCLK_DIV2_EN, VCLK_DIV2_EN); + + /* select vclk_div2 for HDMI-TX */ + regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL, + HDMI_TX_PIXEL_SEL_MASK, 1 << HDMI_TX_PIXEL_SEL_SHIFT); + regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL, + HDMI_TX_FE_SEL_MASK, 1 << HDMI_TX_FE_SEL_SHIFT); + } else { + /* enable vclk_div2 gate */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, + VCLK_DIV2_EN, VCLK_DIV2_EN); =20 - /* select vclk_div2 for HDMI-TX */ - regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, - HDMI_TX_PIXEL_SEL_MASK, 1 << HDMI_TX_PIXEL_SEL_SHIFT); + /* select vclk_div2 for HDMI-TX */ + regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, + HDMI_TX_PIXEL_SEL_MASK, 1 << HDMI_TX_PIXEL_SEL_SHIFT); + } break; case 4: - /* enable vclk_div4 gate */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, - VCLK_DIV4_EN, VCLK_DIV4_EN); + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { + /* enable vclk_div4 gate */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL, + VCLK_DIV4_EN, VCLK_DIV4_EN); + + /* select vclk_div4 for HDMI-TX */ + regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL, + HDMI_TX_PIXEL_SEL_MASK, 2 << HDMI_TX_PIXEL_SEL_SHIFT); + regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL, + HDMI_TX_FE_SEL_MASK, 2 << HDMI_TX_FE_SEL_SHIFT); + } else { + /* enable vclk_div4 gate */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, + VCLK_DIV4_EN, VCLK_DIV4_EN); =20 - /* select vclk_div4 for HDMI-TX */ - regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, - HDMI_TX_PIXEL_SEL_MASK, 2 << HDMI_TX_PIXEL_SEL_SHIFT); + /* select vclk_div4 for HDMI-TX */ + regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, + HDMI_TX_PIXEL_SEL_MASK, 2 << HDMI_TX_PIXEL_SEL_SHIFT); + } break; case 6: - /* enable vclk_div6 gate */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, - VCLK_DIV6_EN, VCLK_DIV6_EN); + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { + /* enable vclk_div6 gate */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL, + VCLK_DIV6_EN, VCLK_DIV6_EN); + + /* select vclk_div6 for HDMI-TX */ + regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL, + HDMI_TX_PIXEL_SEL_MASK, 3 << HDMI_TX_PIXEL_SEL_SHIFT); + regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL, + HDMI_TX_FE_SEL_MASK, 3 << HDMI_TX_FE_SEL_SHIFT); + } else { + /* enable vclk_div6 gate */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, + VCLK_DIV6_EN, VCLK_DIV6_EN); =20 - /* select vclk_div6 for HDMI-TX */ - regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, - HDMI_TX_PIXEL_SEL_MASK, 3 << HDMI_TX_PIXEL_SEL_SHIFT); + /* select vclk_div6 for HDMI-TX */ + regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, + HDMI_TX_PIXEL_SEL_MASK, 3 << HDMI_TX_PIXEL_SEL_SHIFT); + } break; case 12: - /* enable vclk_div12 gate */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, - VCLK_DIV12_EN, VCLK_DIV12_EN); + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { + /* enable vclk_div12 gate */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL, + VCLK_DIV12_EN, VCLK_DIV12_EN); + + /* select vclk_div12 for HDMI-TX */ + regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL, + HDMI_TX_PIXEL_SEL_MASK, 4 << HDMI_TX_PIXEL_SEL_SHIFT); + regmap_update_bits(priv->clkctrl, CLKCTRL_HDMI_CLK_CTRL, + HDMI_TX_FE_SEL_MASK, 4 << HDMI_TX_FE_SEL_SHIFT); + } else { + /* enable vclk_div12 gate */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, + VCLK_DIV12_EN, VCLK_DIV12_EN); =20 - /* select vclk_div12 for HDMI-TX */ - regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, - HDMI_TX_PIXEL_SEL_MASK, 4 << HDMI_TX_PIXEL_SEL_SHIFT); + /* select vclk_div12 for HDMI-TX */ + regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, + HDMI_TX_PIXEL_SEL_MASK, 4 << HDMI_TX_PIXEL_SEL_SHIFT); + } break; } - regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL2, + HDMI_TX_PIXEL_EN, HDMI_TX_PIXEL_EN); + else + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, HDMI_TX_PIXEL_EN, HDMI_TX_PIXEL_EN); =20 /* Set ENCI/ENCP Source */ - switch (venc_div) { - case 1: - /* enable vclk_div1 gate */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, - VCLK_DIV1_EN, VCLK_DIV1_EN); - - if (hdmi_use_enci) - /* select vclk_div1 for enci */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, - CTS_ENCI_SEL_MASK, 0); - else - /* select vclk_div1 for encp */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, - CTS_ENCP_SEL_MASK, 0); - break; - case 2: - /* enable vclk_div2 gate */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, - VCLK_DIV2_EN, VCLK_DIV2_EN); - - if (hdmi_use_enci) - /* select vclk_div2 for enci */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, - CTS_ENCI_SEL_MASK, 1 << CTS_ENCI_SEL_SHIFT); - else - /* select vclk_div2 for encp */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, - CTS_ENCP_SEL_MASK, 1 << CTS_ENCP_SEL_SHIFT); - break; - case 4: - /* enable vclk_div4 gate */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, - VCLK_DIV4_EN, VCLK_DIV4_EN); + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { + switch (venc_div) { + case 1: + /* enable vclk_div1 gate */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL, + VCLK_DIV1_EN, VCLK_DIV1_EN); + + if (hdmi_use_enci) + /* select vclk_div1 for enci */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV, + CTS_ENCI_SEL_MASK, 0); + else + /* select vclk_div1 for encp */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV, + CTS_ENCP_SEL_MASK, 0); + break; + case 2: + /* enable vclk_div2 gate */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL, + VCLK_DIV2_EN, VCLK_DIV2_EN); + + if (hdmi_use_enci) + /* select vclk_div2 for enci */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV, + CTS_ENCI_SEL_MASK, 1 << CTS_ENCI_SEL_SHIFT); + else + /* select vclk_div2 for encp */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV, + CTS_ENCP_SEL_MASK, 1 << CTS_ENCP_SEL_SHIFT); + break; + case 4: + /* enable vclk_div4 gate */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL, + VCLK_DIV4_EN, VCLK_DIV4_EN); + + if (hdmi_use_enci) + /* select vclk_div4 for enci */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV, + CTS_ENCI_SEL_MASK, 2 << CTS_ENCI_SEL_SHIFT); + else + /* select vclk_div4 for encp */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV, + CTS_ENCP_SEL_MASK, 2 << CTS_ENCP_SEL_SHIFT); + break; + case 6: + /* enable vclk_div6 gate */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL, + VCLK_DIV6_EN, VCLK_DIV6_EN); + + if (hdmi_use_enci) + /* select vclk_div6 for enci */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV, + CTS_ENCI_SEL_MASK, 3 << CTS_ENCI_SEL_SHIFT); + else + /* select vclk_div6 for encp */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV, + CTS_ENCP_SEL_MASK, 3 << CTS_ENCP_SEL_SHIFT); + break; + case 12: + /* enable vclk_div12 gate */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL, + VCLK_DIV12_EN, VCLK_DIV12_EN); + + if (hdmi_use_enci) + /* select vclk_div12 for enci */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV, + CTS_ENCI_SEL_MASK, 4 << CTS_ENCI_SEL_SHIFT); + else + /* select vclk_div12 for encp */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_DIV, + CTS_ENCP_SEL_MASK, 4 << CTS_ENCP_SEL_SHIFT); + break; + } =20 if (hdmi_use_enci) - /* select vclk_div4 for enci */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, - CTS_ENCI_SEL_MASK, 2 << CTS_ENCI_SEL_SHIFT); + /* Enable ENCI clock gate */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL2, + CTS_ENCI_EN, CTS_ENCI_EN); else - /* select vclk_div4 for encp */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, - CTS_ENCP_SEL_MASK, 2 << CTS_ENCP_SEL_SHIFT); - break; - case 6: - /* enable vclk_div6 gate */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, - VCLK_DIV6_EN, VCLK_DIV6_EN); + /* Enable ENCP clock gate */ + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL2, + CTS_ENCP_EN, CTS_ENCP_EN); + + regmap_update_bits(priv->clkctrl, CLKCTRL_VID_CLK_CTRL, VCLK_EN, VCLK_EN= ); + } else { + switch (venc_div) { + case 1: + /* enable vclk_div1 gate */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, + VCLK_DIV1_EN, VCLK_DIV1_EN); + + if (hdmi_use_enci) + /* select vclk_div1 for enci */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, + CTS_ENCI_SEL_MASK, 0); + else + /* select vclk_div1 for encp */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, + CTS_ENCP_SEL_MASK, 0); + break; + case 2: + /* enable vclk_div2 gate */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, + VCLK_DIV2_EN, VCLK_DIV2_EN); + + if (hdmi_use_enci) + /* select vclk_div2 for enci */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, + CTS_ENCI_SEL_MASK, 1 << CTS_ENCI_SEL_SHIFT); + else + /* select vclk_div2 for encp */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, + CTS_ENCP_SEL_MASK, 1 << CTS_ENCP_SEL_SHIFT); + break; + case 4: + /* enable vclk_div4 gate */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, + VCLK_DIV4_EN, VCLK_DIV4_EN); + + if (hdmi_use_enci) + /* select vclk_div4 for enci */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, + CTS_ENCI_SEL_MASK, 2 << CTS_ENCI_SEL_SHIFT); + else + /* select vclk_div4 for encp */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, + CTS_ENCP_SEL_MASK, 2 << CTS_ENCP_SEL_SHIFT); + break; + case 6: + /* enable vclk_div6 gate */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, + VCLK_DIV6_EN, VCLK_DIV6_EN); + + if (hdmi_use_enci) + /* select vclk_div6 for enci */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, + CTS_ENCI_SEL_MASK, 3 << CTS_ENCI_SEL_SHIFT); + else + /* select vclk_div6 for encp */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, + CTS_ENCP_SEL_MASK, 3 << CTS_ENCP_SEL_SHIFT); + break; + case 12: + /* enable vclk_div12 gate */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, + VCLK_DIV12_EN, VCLK_DIV12_EN); + + if (hdmi_use_enci) + /* select vclk_div12 for enci */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, + CTS_ENCI_SEL_MASK, 4 << CTS_ENCI_SEL_SHIFT); + else + /* select vclk_div12 for encp */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, + CTS_ENCP_SEL_MASK, 4 << CTS_ENCP_SEL_SHIFT); + break; + } =20 if (hdmi_use_enci) - /* select vclk_div6 for enci */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, - CTS_ENCI_SEL_MASK, 3 << CTS_ENCI_SEL_SHIFT); + /* Enable ENCI clock gate */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, + CTS_ENCI_EN, CTS_ENCI_EN); else - /* select vclk_div6 for encp */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, - CTS_ENCP_SEL_MASK, 3 << CTS_ENCP_SEL_SHIFT); - break; - case 12: - /* enable vclk_div12 gate */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, - VCLK_DIV12_EN, VCLK_DIV12_EN); + /* Enable ENCP clock gate */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, + CTS_ENCP_EN, CTS_ENCP_EN); =20 - if (hdmi_use_enci) - /* select vclk_div12 for enci */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, - CTS_ENCI_SEL_MASK, 4 << CTS_ENCI_SEL_SHIFT); - else - /* select vclk_div12 for encp */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, - CTS_ENCP_SEL_MASK, 4 << CTS_ENCP_SEL_SHIFT); - break; + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN); } - - if (hdmi_use_enci) - /* Enable ENCI clock gate */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, - CTS_ENCI_EN, CTS_ENCI_EN); - else - /* Enable ENCP clock gate */ - regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, - CTS_ENCP_EN, CTS_ENCP_EN); - - regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN); } =20 void meson_vclk_setup(struct meson_drm *priv, unsigned int target, --=20 2.43.0 From nobody Sun Feb 8 15:46:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EBC12066F5; Fri, 10 Jan 2025 05:39:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250110-drm-s4-v1-10-cbc2d5edaae8@amlogic.com> References: <20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com> In-Reply-To: <20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com> To: Neil Armstrong , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ao Xu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1736487593; l=1984; i=ao.xu@amlogic.com; s=20250103; h=from:subject:message-id; bh=ksJtH4UxnpEi7M4UkQGZERM6UKX2oS80vckfy1Q9IKE=; b=rmzddFL21GrVnJWT/GWsDudRTQRE6oO9H55qODD4VTAuFAr4RaVDt8+uZUOTfYRY7VK/OYwY3 PrV0mS4uywOBSA/hF0LAwYxgqPPvR4uPeVjWkxv68lOF7sP4Wa38bCT X-Developer-Key: i=ao.xu@amlogic.com; a=ed25519; pk=c0TSXrwQuL4EhPVf3lJ676U27ax2yfFTqmRoseP/fA8= X-Endpoint-Received: by B4 Relay for ao.xu@amlogic.com/20250103 with auth_id=308 X-Original-From: Ao Xu Reply-To: ao.xu@amlogic.com From: Ao Xu Add support for Composite Video Baseband Signal (CVBS) in the Meson encoder driver for the Amlogic S4 SoC. Signed-off-by: Ao Xu --- drivers/gpu/drm/meson/meson_encoder_cvbs.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/meson/meson_encoder_cvbs.c b/drivers/gpu/drm/m= eson/meson_encoder_cvbs.c index d1191de855d910f9845bf2d5aef336e391982ba2..45ed800173c1754b23fdc8b53e9= 487530bcae5a3 100644 --- a/drivers/gpu/drm/meson/meson_encoder_cvbs.c +++ b/drivers/gpu/drm/meson/meson_encoder_cvbs.c @@ -30,6 +30,10 @@ #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ #define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbe offset in data sheet */ =20 +/* ANA VDAC Registers */ +#define ANACTRL_VDAC_CTRL0 0x2c0 /* 0xb0 offset in data sheet */ +#define ANACTRL_VDAC_CTRL1 0x2c4 /* 0xb1 offset in data sheet */ + struct meson_encoder_cvbs { struct drm_encoder encoder; struct drm_bridge bridge; @@ -187,6 +191,9 @@ static void meson_encoder_cvbs_atomic_enable(struct drm= _bridge *bridge, } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0x906001); regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0); + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { + regmap_write(priv->hhi, ANACTRL_VDAC_CTRL0, 0x406802); + regmap_write(priv->hhi, ANACTRL_VDAC_CTRL1, 0xc4); } } =20 @@ -201,6 +208,9 @@ static void meson_encoder_cvbs_atomic_disable(struct dr= m_bridge *bridge, if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0); regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0); + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { + regmap_write(priv->hhi, ANACTRL_VDAC_CTRL0, 0); + regmap_write(priv->hhi, ANACTRL_VDAC_CTRL1, 0); } else { regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0); regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8); --=20 2.43.0 From nobody Sun Feb 8 15:46:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E1A42066F4; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250110-drm-s4-v1-11-cbc2d5edaae8@amlogic.com> References: <20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com> In-Reply-To: <20250110-drm-s4-v1-0-cbc2d5edaae8@amlogic.com> To: Neil Armstrong , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ao Xu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1736487593; l=6247; i=ao.xu@amlogic.com; s=20250103; h=from:subject:message-id; bh=XuHerOPR1COry4ixXJL2bKpILc0PgbExEjuuK22BMs8=; b=PJJmhdfuiVW6iCkU5sshDWKvx3mCxxGLTp2FuK353sgQWkCzjibuRHzv/pfGySXCJx4j4+VVW wPBh2MRtFvvCW5LiVkBYILuGYfU6rDpUG5mlAT/xe/vVK7vzU4tPPrU X-Developer-Key: i=ao.xu@amlogic.com; a=ed25519; pk=c0TSXrwQuL4EhPVf3lJ676U27ax2yfFTqmRoseP/fA8= X-Endpoint-Received: by B4 Relay for ao.xu@amlogic.com/20250103 with auth_id=308 X-Original-From: Ao Xu Reply-To: ao.xu@amlogic.com From: Ao Xu Add Device Tree support for the DRM subsystem on the Amlogic S4 SoC. Enable nodes for canvas, vpu, and HDMI controllers. Enable nodes for CVBS and HDMI bridge connector components. Signed-off-by: Ao Xu --- .../boot/dts/amlogic/meson-s4-s805x2-aq222.dts | 39 +++++++ arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 121 +++++++++++++++++= ++++ 2 files changed, 160 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts b/arch/a= rm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts index 6730c44642d2910d42ec0c4adf49fefc3514dbec..e40206192ac0f7b80da23e629aa= 3044c04f7e969 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts +++ b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts @@ -129,6 +129,27 @@ vddcpu: regulator-vddcpu { <699000 98>, <689000 100>; }; + + cvbs-connector { + compatible =3D "composite-video-connector"; + + port { + cvbs_connector_in: endpoint { + remote-endpoint =3D <&cvbs_vdac_out>; + }; + }; + }; + + hdmi-connector { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint =3D <&hdmi_tx_tmds_out>; + }; + }; + }; }; =20 &pwm_ef { @@ -235,3 +256,21 @@ ðmac { phy-handle =3D <&internal_ephy>; phy-mode =3D "rmii"; }; + +&cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint =3D <&cvbs_connector_in>; + }; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint =3D <&hdmi_connector_in>; + }; +}; + +&hdmi_tx { + status =3D "okay"; + pinctrl-0 =3D <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; + pinctrl-names =3D "default"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dt= s/amlogic/meson-s4.dtsi index 957577d986c0675a503115e1ccbc4387c2051620..ce4a24f0880c09cf4fd06d2046b= 520335d62a6cd 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include =20 @@ -102,6 +103,50 @@ apb4: bus@fe000000 { #size-cells =3D <2>; ranges =3D <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; =20 + dmc: bus@36000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x0 0x0 0x0 0x36000 0x0 0x2000>; + + canvas: video-lut@48 { + compatible =3D "amlogic,canvas"; + reg =3D <0x0 0x48 0x0 0x14>; + }; + }; + + hdmi_tx: hdmi-tx@300000 { + compatible =3D "amlogic,meson-s4-dw-hdmi"; + reg =3D <0x0 0x300000 0x0 0x10000>; + interrupts =3D ; + resets =3D <&reset RESET_HDMITX_APB>, + <&reset RESET_HDMITXPHY>, + <&reset RESET_HDMI_TX>; + reset-names =3D "hdmitx_apb", "hdmitx", "hdmitx_phy"; + clocks =3D <&clkc_periphs CLKID_HDMI>, + <&clkc_periphs CLKID_HDMITX_APB>, + <&clkc_periphs CLKID_VPU_INTR>; + clock-names =3D "isfr", "iahb", "venci"; + #address-cells =3D <1>; + #size-cells =3D <0>; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + + /* VPU VENC Input */ + hdmi_tx_venc_port: port@0 { + reg =3D <0>; + + hdmi_tx_in: endpoint { + remote-endpoint =3D <&hdmi_tx_out>; + }; + }; + + /* TMDS Output */ + hdmi_tx_tmds_port: port@1 { + reg =3D <1>; + }; + }; + clkc_periphs: clock-controller@0 { compatible =3D "amlogic,s4-peripherals-clkc"; reg =3D <0x0 0x0 0x0 0x49c>; @@ -584,6 +629,24 @@ mux { }; }; =20 + hdmitx_hpd_pins: hdmitx-hpd { + mux { + groups =3D "hdmitx_hpd_in"; + function =3D "hdmitx"; + bias-disable; + }; + }; + + hdmitx_ddc_pins: hdmitx-ddc { + mux { + groups =3D "hdmitx_sda", + "hdmitx_sck"; + function =3D "hdmitx"; + bias-disable; + drive-strength-microamp =3D <4000>; + }; + }; + }; =20 gpio_intc: interrupt-controller@4080 { @@ -848,5 +911,63 @@ emmc: mmc@fe08c000 { no-sd; status =3D "disabled"; }; + + vpu: vpu@ff000000 { + compatible =3D "amlogic,meson-s4-vpu"; + reg =3D <0x0 0xff000000 0x0 0x40000>, + <0x0 0xfe008000 0x0 0x2000>, + <0x0 0xfe000000 0x0 0x2000>, + <0x0 0xfe00c000 0x0 0x0800>, + <0x0 0xfe010000 0x0 0x0100>; + reg-names =3D "vpu", "hhi", "clkctrl", "pwrctrl", "sysctrl"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + amlogic,canvas =3D <&canvas>; + power-domains =3D <&pwrc PWRC_S4_VPU_HDMI_ID>; + + clocks =3D <&clkc_periphs CLKID_VPU>, + <&clkc_periphs CLKID_VAPB>; + clock-names =3D "vpu", "vapb"; + + /* + * VPU clocking is provided by two identical clock paths + * VPU_0 and VPU_1 muxed to a single clock by a glitch + * free mux to safely change frequency while running. + * Same for VAPB but with a final gate after the glitch free mux. + */ + assigned-clocks =3D <&clkc_periphs CLKID_VPU_0_SEL>, + <&clkc_periphs CLKID_VPU_0>, + <&clkc_periphs CLKID_VPU>, /* Glitch free mux */ + <&clkc_periphs CLKID_VAPB_0_SEL>, + <&clkc_periphs CLKID_VAPB_0>, + <&clkc_periphs CLKID_VAPB>; /* Glitch free mux */ + assigned-clock-parents =3D <&clkc_periphs CLKID_FCLK_DIV3>, + <0>, /* Do Nothing */ + <&clkc_periphs CLKID_VPU_0>, + <&clkc_periphs CLKID_FCLK_DIV4>, + <0>, /* Do Nothing */ + <&clkc_periphs CLKID_VAPB_0>; + assigned-clock-rates =3D <0>, /* Do Nothing */ + <666666666>, + <0>, /* Do Nothing */ + <0>, /* Do Nothing */ + <250000000>, + <0>; /* Do Nothing */ + + /* CVBS VDAC output port */ + cvbs_vdac_port: port@0 { + reg =3D <0>; + }; + + /* HDMI-TX output port */ + hdmi_tx_port: port@1 { + reg =3D <1>; + + hdmi_tx_out: endpoint { + remote-endpoint =3D <&hdmi_tx_in>; + }; + }; + }; }; }; --=20 2.43.0