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[2001:14ba:a0c3:3a00::782]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5428bec06e1sm73866e87.191.2025.01.08.20.35.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jan 2025 20:35:58 -0800 (PST) From: Dmitry Baryshkov Date: Thu, 09 Jan 2025 06:35:48 +0200 Subject: [PATCH v4 4/5] nvmem: qfprom: switch to 4-byte aligned reads Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250109-sar2130p-nvmem-v4-4-633739fe5f11@linaro.org> References: <20250109-sar2130p-nvmem-v4-0-633739fe5f11@linaro.org> In-Reply-To: <20250109-sar2130p-nvmem-v4-0-633739fe5f11@linaro.org> To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Akhil P Oommen , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2302; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=Weli6Ud1pnhnVMQNhXbarzN29phyH4B6NUF7IDp6kk8=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnf1IkACTJK3+cbEVvQiLITbU/iuCdV9QIf923Z +4gR8kMz82JAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZ39SJAAKCRAU23LtvoBl uCbOD/9y3o9U+3IKjSZHvf0PVEnBIh5ablg36IJ6zcIvPqMEWb9e/IrHB9i/hxb+Ndi5oOxY96A a+o0PchHna8jfEfQOdlO4sX1ZFDR4rXEN9vlq3js96XRsbeyE6Qj0uD+4Z6wkmDmi0Ux19uAGkd zaHC8mfrito3xE9Rke3bivnJz620TW0eTAWBHOiICk7NjV4KpVXYK6b1vpLoiAAT60JDdihI69A ZaYdPtj61kHUVrhD0+Z1WNixvu4pfropDa7qA1gSpdn+GChXJONzjKrq2SZCPkhRmhcm6SRJ1vc mQTQMILV9ZQzc3Apqn82tZKXwQ/0amgx2fOxQngAPQW1YsloCmN8Zq/PY19mtrDH7uwMIE8h9PC nzhkXRumB61iQVYiKbZ1MzHPv1xGX8oB8zzT2XuLBNDnF2anv6GG9Km2ucqC7tCaYXSu2lQBejB hJkVsmm3JNVwiGkNQ4GnU3FdWly0eLEItkFC9IGM61wTITSCa7QV5dDpaYaJpl7lzYz61oABBct 5RTQkxajL9rDkpdZ0vFEycIpfQbWVGs3KDZ3J/sprYSJlZAljWVrgqpkvHstnAZpVqzN+PQMtTp SX3834e1v1is/rP1Lndu+/hQR8MOEUnyBMlCRXbrhqBSMZdCR3DNZpsHFl/X8ElvGlOrTLMKA7u xF5aUi3mvdjawDw== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A All platforms since Snapdragon 8 Gen1 (SM8450) require using 4-byte reads to access QFPROM data. While older platforms were more than happy with 1-byte reads, change the qfprom driver to use 4-byte reads for all the platforms. Specify stride and word size of 4 bytes. To retain compatibility with the existing DT and to simplify porting data from vendor kernels, use fixup_dt_cell_info in order to bump alignment requirements. Signed-off-by: Dmitry Baryshkov --- drivers/nvmem/qfprom.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c index 116a39e804c70b4a0374f8ea3ac6ba1dd612109d..a872c640b8c5a558da9ea00e380= 4c904f8987247 100644 --- a/drivers/nvmem/qfprom.c +++ b/drivers/nvmem/qfprom.c @@ -321,19 +321,32 @@ static int qfprom_reg_read(void *context, unsigned int reg, void *_val, size_t bytes) { struct qfprom_priv *priv =3D context; - u8 *val =3D _val; - int i =3D 0, words =3D bytes; + u32 *val =3D _val; void __iomem *base =3D priv->qfpcorrected; + int words =3D DIV_ROUND_UP(bytes, sizeof(u32)); + int i; =20 if (read_raw_data && priv->qfpraw) base =3D priv->qfpraw; =20 - while (words--) - *val++ =3D readb(base + reg + i++); + for (i =3D 0; i < words; i++) + *val++ =3D readl(base + reg + i * sizeof(u32)); =20 return 0; } =20 +/* Align reads to word boundary */ +static void qfprom_fixup_dt_cell_info(struct nvmem_device *nvmem, + struct nvmem_cell_info *cell) +{ + unsigned int byte_offset =3D cell->offset % sizeof(u32); + + cell->bit_offset +=3D byte_offset * BITS_PER_BYTE; + cell->offset -=3D byte_offset; + if (byte_offset && !cell->nbits) + cell->nbits =3D cell->bytes * BITS_PER_BYTE; +} + static void qfprom_runtime_disable(void *data) { pm_runtime_disable(data); @@ -358,10 +371,11 @@ static int qfprom_probe(struct platform_device *pdev) struct nvmem_config econfig =3D { .name =3D "qfprom", .add_legacy_fixed_of_cells =3D true, - .stride =3D 1, - .word_size =3D 1, + .stride =3D 4, + .word_size =3D 4, .id =3D NVMEM_DEVID_AUTO, .reg_read =3D qfprom_reg_read, + .fixup_dt_cell_info =3D qfprom_fixup_dt_cell_info, }; struct device *dev =3D &pdev->dev; struct resource *res; --=20 2.39.5