From nobody Fri Dec 19 20:54:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D53251FC7CC for ; Wed, 8 Jan 2025 13:56:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736344576; cv=none; b=Rk2r21dXkatLlFsXEiQzlNcCLm5n5EYCuR4LuDmJK8BzW3Vwk5Hj+3yYffzRwIxfstfxO3YGwwRLqPb7tZ9wTZE5Vh9pn/WXyadLX0kdJlW1Z88v8UJLEkypWWQ9BM2lJn21p3jcUIHPwnhV3uJK0jypxztGZeR+3DlwswHYq/c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736344576; c=relaxed/simple; bh=gCGrKfy44DuK3ojOPo53zmzXYchsT39nqWovJGtKx04=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Yd5f30jsJR8HRE0FdrYi8fDwXyiQ/Kz2GHGNijNRliJJGqAaqlOnCJ0zJ1hzMkW6cMkJavMLJhrKr2Bp1AEnZbJcVO2GpnzpWMkD2NMJk1MZpYQypB1QPnYlDh6s/1jgGkhUD2EZ56AIF8DPdUeSK9gpSYTx322CnVkT7irUybc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=KSFqrs4S; arc=none smtp.client-ip=192.198.163.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="KSFqrs4S" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1736344575; x=1767880575; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=gCGrKfy44DuK3ojOPo53zmzXYchsT39nqWovJGtKx04=; b=KSFqrs4SPY2hzW6aVxSOlp0yuEUM+QV6CvSDGQzIlFORwXCGKGqQI7D1 Ys5/T/qlZcjYeN81qKV95d1NB6J1B1AqNCxq0haqj+xH5jbEFla/W2fqe 6Wj8z6fGM0tLXm/GnGLasBOiNRzMqmFT0HBbVcL3T0RYJsjguaF9p2cZK a1hEaKPtrSG6I40O5U7C6xtMQBefpYld05WqOg9ZM+9H3FzWsYliF0rdD /va/1HcXMhtq6MkNKtXl1cbOCKOMfd6ThZzsh4bN7+sXGklMU3JC8N2jF XquBBkZwQw/5DoOvCjy6r8VJEQYLJ//FKBceW82Tls48SMO7dBDidyzU3 A==; X-CSE-ConnectionGUID: T+O7lf4ITVOa5veQudzN8A== X-CSE-MsgGUID: mru9HAjSTI6WbZg4VZZ0xw== X-IronPort-AV: E=McAfee;i="6700,10204,11309"; a="61948166" X-IronPort-AV: E=Sophos;i="6.12,298,1728975600"; d="scan'208";a="61948166" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2025 05:56:14 -0800 X-CSE-ConnectionGUID: rx3b5rnbQYqE0JpUBhsS7A== X-CSE-MsgGUID: uXhv/PzkQqaNzxcdFkBDLw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="102971639" Received: from pg15swiplab1181.png.altera.com ([10.244.232.167]) by orviesa010.jf.intel.com with ESMTP; 08 Jan 2025 05:56:11 -0800 From: niravkumar.l.rabara@intel.com To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Niravkumar L Rabara , linux@treblig.org, Shen Lichuan , Jinjie Ruan , u.kleine-koenig@baylibre.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] mtd: rawnand: cadence: use dma_map_resource for sdma address Date: Wed, 8 Jan 2025 21:52:33 +0800 Message-Id: <20250108135234.3107502-3-niravkumar.l.rabara@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250108135234.3107502-1-niravkumar.l.rabara@intel.com> References: <20250108135234.3107502-1-niravkumar.l.rabara@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Niravkumar L Rabara Map the slave DMA I/O address using dma_map_resource. When ARM SMMU is enabled, using a direct physical address of SDMA results in DMA transaction failure. Signed-off-by: Niravkumar L Rabara --- .../mtd/nand/raw/cadence-nand-controller.c | 29 ++++++++++++++++--- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/cadence-nand-controller.c b/drivers/mtd/n= and/raw/cadence-nand-controller.c index 5e27f5546f1b..8281151cf869 100644 --- a/drivers/mtd/nand/raw/cadence-nand-controller.c +++ b/drivers/mtd/nand/raw/cadence-nand-controller.c @@ -471,6 +471,8 @@ struct cdns_nand_ctrl { struct { void __iomem *virt; dma_addr_t dma; + dma_addr_t iova_dma; + u32 size; } io; =20 int irq; @@ -1835,11 +1837,11 @@ static int cadence_nand_slave_dma_transfer(struct c= dns_nand_ctrl *cdns_ctrl, } =20 if (dir =3D=3D DMA_FROM_DEVICE) { - src_dma =3D cdns_ctrl->io.dma; + src_dma =3D cdns_ctrl->io.iova_dma; dst_dma =3D buf_dma; } else { src_dma =3D buf_dma; - dst_dma =3D cdns_ctrl->io.dma; + dst_dma =3D cdns_ctrl->io.iova_dma; } =20 tx =3D dmaengine_prep_dma_memcpy(cdns_ctrl->dmac, dst_dma, src_dma, len, @@ -2869,6 +2871,7 @@ cadence_nand_irq_cleanup(int irqnum, struct cdns_nand= _ctrl *cdns_ctrl) static int cadence_nand_init(struct cdns_nand_ctrl *cdns_ctrl) { dma_cap_mask_t mask; + struct dma_device *dma_dev =3D cdns_ctrl->dmac->device; int ret; =20 cdns_ctrl->cdma_desc =3D dma_alloc_coherent(cdns_ctrl->dev, @@ -2913,6 +2916,16 @@ static int cadence_nand_init(struct cdns_nand_ctrl *= cdns_ctrl) } } =20 + cdns_ctrl->io.iova_dma =3D dma_map_resource(dma_dev->dev, cdns_ctrl->io.d= ma, + cdns_ctrl->io.size, + DMA_BIDIRECTIONAL, 0); + + ret =3D dma_mapping_error(dma_dev->dev, cdns_ctrl->io.iova_dma); + if (ret) { + dev_err(cdns_ctrl->dev, "Failed to map I/O resource to DMA\n"); + goto dma_release_chnl; + } + nand_controller_init(&cdns_ctrl->controller); INIT_LIST_HEAD(&cdns_ctrl->chips); =20 @@ -2923,18 +2936,22 @@ static int cadence_nand_init(struct cdns_nand_ctrl = *cdns_ctrl) if (ret) { dev_err(cdns_ctrl->dev, "Failed to register MTD: %d\n", ret); - goto dma_release_chnl; + goto unmap_dma_resource; } =20 kfree(cdns_ctrl->buf); cdns_ctrl->buf =3D kzalloc(cdns_ctrl->buf_size, GFP_KERNEL); if (!cdns_ctrl->buf) { ret =3D -ENOMEM; - goto dma_release_chnl; + goto unmap_dma_resource; } =20 return 0; =20 +unmap_dma_resource: + dma_unmap_resource(dma_dev->dev, cdns_ctrl->io.iova_dma, + cdns_ctrl->io.size, DMA_BIDIRECTIONAL, 0); + dma_release_chnl: if (cdns_ctrl->dmac) dma_release_channel(cdns_ctrl->dmac); @@ -2956,6 +2973,8 @@ static int cadence_nand_init(struct cdns_nand_ctrl *c= dns_ctrl) static void cadence_nand_remove(struct cdns_nand_ctrl *cdns_ctrl) { cadence_nand_chips_cleanup(cdns_ctrl); + dma_unmap_resource(cdns_ctrl->dmac->device->dev, cdns_ctrl->io.iova_dma, + cdns_ctrl->io.size, DMA_BIDIRECTIONAL, 0); cadence_nand_irq_cleanup(cdns_ctrl->irq, cdns_ctrl); kfree(cdns_ctrl->buf); dma_free_coherent(cdns_ctrl->dev, sizeof(struct cadence_nand_cdma_desc), @@ -3020,7 +3039,9 @@ static int cadence_nand_dt_probe(struct platform_devi= ce *ofdev) cdns_ctrl->io.virt =3D devm_platform_get_and_ioremap_resource(ofdev, 1, &= res); if (IS_ERR(cdns_ctrl->io.virt)) return PTR_ERR(cdns_ctrl->io.virt); + cdns_ctrl->io.dma =3D res->start; + cdns_ctrl->io.size =3D resource_size(res); =20 dt->clk =3D devm_clk_get(cdns_ctrl->dev, "nf_clk"); if (IS_ERR(dt->clk)) --=20 2.25.1