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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250108-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v2-9-2dac02f04638@baylibre.com> References: <20250108-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v2-0-2dac02f04638@baylibre.com> In-Reply-To: <20250108-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v2-0-2dac02f04638@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Mihail Chindris , Nuno Sa , David Lechner Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.1 From: Angelo Dureghello Update ad3552r_qspi_update_reg_bits function name to a more generic name, since used mode can be SIMPLE/DUAL/QUAD SPI. Signed-off-by: Angelo Dureghello --- drivers/iio/dac/ad3552r-hs.c | 58 ++++++++++++++++++++--------------------= ---- 1 file changed, 26 insertions(+), 32 deletions(-) diff --git a/drivers/iio/dac/ad3552r-hs.c b/drivers/iio/dac/ad3552r-hs.c index 5995bab6a9b1..53ab912eea11 100644 --- a/drivers/iio/dac/ad3552r-hs.c +++ b/drivers/iio/dac/ad3552r-hs.c @@ -56,9 +56,9 @@ struct ad3552r_hs_state { u32 config_d; }; =20 -static int ad3552r_qspi_update_reg_bits(struct ad3552r_hs_state *st, - u32 reg, u32 mask, u32 val, - size_t xfer_size) +static int ad3552r_update_reg_bits(struct ad3552r_hs_state *st, + u32 reg, u32 mask, u32 val, + size_t xfer_size) { u32 rval; int ret; @@ -206,9 +206,8 @@ static int ad3552r_hs_buffer_postenable(struct iio_dev = *indio_dev) */ =20 /* Primary region access, set streaming mode (now in SPI + SDR). */ - ret =3D ad3552r_qspi_update_reg_bits(st, - AD3552R_REG_ADDR_INTERFACE_CONFIG_B, - AD3552R_MASK_SINGLE_INST, 0, 1); + ret =3D ad3552r_update_reg_bits(st, AD3552R_REG_ADDR_INTERFACE_CONFIG_B, + AD3552R_MASK_SINGLE_INST, 0, 1); if (ret) return ret; =20 @@ -217,10 +216,9 @@ static int ad3552r_hs_buffer_postenable(struct iio_dev= *indio_dev) * and keeping loop len value so it's not cleared hereafter when * enabling streaming mode (cleared by CS_ up). */ - ret =3D ad3552r_qspi_update_reg_bits(st, - AD3552R_REG_ADDR_TRANSFER_REGISTER, - AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, - AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1); + ret =3D ad3552r_update_reg_bits(st, AD3552R_REG_ADDR_TRANSFER_REGISTER, + AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, + AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1); if (ret) goto exit_err_streaming; =20 @@ -247,7 +245,6 @@ static int ad3552r_hs_buffer_postenable(struct iio_dev = *indio_dev) ret =3D st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_INTERFACE_CONFIG_D, st->config_d, 1); - if (ret) goto exit_err_streaming; =20 @@ -257,7 +254,7 @@ static int ad3552r_hs_buffer_postenable(struct iio_dev = *indio_dev) =20 /* * From here onward mode is DDR, so reading any register is not - * possible anymore, including calling "ad3552r_qspi_update_reg_bits" + * possible anymore, including calling "ad3552r_update_reg_bits" * function. */ =20 @@ -359,10 +356,9 @@ static int ad3552r_hs_buffer_predisable(struct iio_dev= *indio_dev) * Back to simple SPI for secondary region too now, * so to be able to dump/read registers there too if needed. */ - ret =3D ad3552r_qspi_update_reg_bits(st, - AD3552R_REG_ADDR_TRANSFER_REGISTER, - AD3552R_MASK_MULTI_IO_MODE, - AD3552R_SPI, 1); + ret =3D ad3552r_update_reg_bits(st, AD3552R_REG_ADDR_TRANSFER_REGISTER, + AD3552R_MASK_MULTI_IO_MODE, + AD3552R_SPI, 1); if (ret) return ret; =20 @@ -386,10 +382,10 @@ static inline int ad3552r_hs_set_output_range(struct = ad3552r_hs_state *st, else val =3D FIELD_PREP(AD3552R_MASK_CH1_RANGE, mode); =20 - return ad3552r_qspi_update_reg_bits(st, - AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE, - AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch), - val, 1); + return ad3552r_update_reg_bits(st, + AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE, + AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch), + val, 1); } =20 static int ad3552r_hs_reset(struct ad3552r_hs_state *st) @@ -405,10 +401,10 @@ static int ad3552r_hs_reset(struct ad3552r_hs_state *= st) fsleep(10); gpiod_set_value_cansleep(st->reset_gpio, 0); } else { - ret =3D ad3552r_qspi_update_reg_bits(st, - AD3552R_REG_ADDR_INTERFACE_CONFIG_A, - AD3552R_MASK_SOFTWARE_RESET, - AD3552R_MASK_SOFTWARE_RESET, 1); + ret =3D ad3552r_update_reg_bits(st, + AD3552R_REG_ADDR_INTERFACE_CONFIG_A, + AD3552R_MASK_SOFTWARE_RESET, + AD3552R_MASK_SOFTWARE_RESET, 1); if (ret) return ret; } @@ -541,19 +537,17 @@ static int ad3552r_hs_setup(struct ad3552r_hs_state *= st) =20 val =3D ret; =20 - ret =3D ad3552r_qspi_update_reg_bits(st, - AD3552R_REG_ADDR_SH_REFERENCE_CONFIG, - AD3552R_MASK_REFERENCE_VOLTAGE_SEL, - val, 1); + ret =3D ad3552r_update_reg_bits(st, AD3552R_REG_ADDR_SH_REFERENCE_CONFIG, + AD3552R_MASK_REFERENCE_VOLTAGE_SEL, + val, 1); if (ret) return ret; =20 ret =3D ad3552r_get_drive_strength(st->dev, &val); if (!ret) { - ret =3D ad3552r_qspi_update_reg_bits(st, - AD3552R_REG_ADDR_INTERFACE_CONFIG_D, - AD3552R_MASK_SDO_DRIVE_STRENGTH, - val, 1); + ret =3D ad3552r_update_reg_bits(st, + AD3552R_REG_ADDR_INTERFACE_CONFIG_D, + AD3552R_MASK_SDO_DRIVE_STRENGTH, val, 1); if (ret) return ret; } --=20 2.47.0