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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250108-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v2-4-2dac02f04638@baylibre.com> References: <20250108-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v2-0-2dac02f04638@baylibre.com> In-Reply-To: <20250108-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v2-0-2dac02f04638@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Mihail Chindris , Nuno Sa , David Lechner Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.1 From: Angelo Dureghello The ad354xr requires DSPI mode (2 data lanes) to work in buffering mode, so backend needs to allow a mode selection between: SPI (entire ad35xxr family), DSPI (ad354xr), QSPI (ad355xr). Signed-off-by: Angelo Dureghello --- drivers/iio/dac/ad3552r-hs.h | 8 ++++++++ drivers/iio/dac/adi-axi-dac.c | 26 +++++++++++++++++++++++++- 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/iio/dac/ad3552r-hs.h b/drivers/iio/dac/ad3552r-hs.h index 724261d38dea..4a9e35234124 100644 --- a/drivers/iio/dac/ad3552r-hs.h +++ b/drivers/iio/dac/ad3552r-hs.h @@ -8,11 +8,19 @@ =20 struct iio_backend; =20 +enum ad3552r_io_mode { + AD3552R_IO_MODE_SPI, + AD3552R_IO_MODE_DSPI, + AD3552R_IO_MODE_QSPI, +}; + struct ad3552r_hs_platform_data { int (*bus_reg_read)(struct iio_backend *back, u32 reg, u32 *val, size_t data_size); int (*bus_reg_write)(struct iio_backend *back, u32 reg, u32 val, size_t data_size); + int (*bus_set_io_mode)(struct iio_backend *back, + enum ad3552r_io_mode mode); u32 bus_sample_data_clock_hz; }; =20 diff --git a/drivers/iio/dac/adi-axi-dac.c b/drivers/iio/dac/adi-axi-dac.c index d02eb535b648..79ca158c1ad9 100644 --- a/drivers/iio/dac/adi-axi-dac.c +++ b/drivers/iio/dac/adi-axi-dac.c @@ -64,7 +64,7 @@ #define AXI_DAC_UI_STATUS_IF_BUSY BIT(4) #define AXI_DAC_CUSTOM_CTRL_REG 0x008C #define AXI_DAC_CUSTOM_CTRL_ADDRESS GENMASK(31, 24) -#define AXI_DAC_CUSTOM_CTRL_SYNCED_TRANSFER BIT(2) +#define AXI_DAC_CUSTOM_CTRL_MULTI_IO_MODE GENMASK(3, 2) #define AXI_DAC_CUSTOM_CTRL_STREAM BIT(1) #define AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA BIT(0) =20 @@ -725,6 +725,29 @@ static int axi_dac_bus_reg_read(struct iio_backend *ba= ck, u32 reg, u32 *val, return regmap_read(st->regmap, AXI_DAC_CUSTOM_RD_REG, val); } =20 +static int axi_dac_bus_set_io_mode(struct iio_backend *back, + enum ad3552r_io_mode mode) +{ + struct axi_dac_state *st =3D iio_backend_get_priv(back); + int ival, ret; + + ret =3D regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, + AXI_DAC_CUSTOM_CTRL_MULTI_IO_MODE, + FIELD_PREP(AXI_DAC_CUSTOM_CTRL_MULTI_IO_MODE, mode)); + if (ret) + return ret; + + ret =3D regmap_read_poll_timeout(st->regmap, + AXI_DAC_UI_STATUS_REG, ival, + FIELD_GET(AXI_DAC_UI_STATUS_IF_BUSY, ival) =3D=3D 0, + 10, 100 * KILO); + + if (ret =3D=3D -ETIMEDOUT) + dev_err(st->dev, "AXI read timeout\n"); + + return ret; +} + static void axi_dac_child_remove(void *data) { platform_device_unregister(data); @@ -736,6 +759,7 @@ static int axi_dac_create_platform_device(struct axi_da= c_state *st, struct ad3552r_hs_platform_data pdata =3D { .bus_reg_read =3D axi_dac_bus_reg_read, .bus_reg_write =3D axi_dac_bus_reg_write, + .bus_set_io_mode =3D axi_dac_bus_set_io_mode, .bus_sample_data_clock_hz =3D st->dac_clk_rate, }; struct platform_device_info pi =3D { --=20 2.47.0