From nobody Fri Dec 19 19:18:44 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3567B2054F7; Wed, 8 Jan 2025 22:53:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736376791; cv=none; b=ZvR6Wlf2mDZXqYTPcJqJmhuzqSQhy8VNyhjmjVQ4WAbzj6+H9m2N36WqgVSFVW6mRflfG+uI9LezKL8jCVOSLU2rkE5HvpuvUbEDb3oYt6JXl/lQbNU9/Qp42HAqkcM0Lh53+Frxhx3gSXUtj7WADCCNBSiNqUECH2kHCnzYn1c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736376791; c=relaxed/simple; bh=9zjr0PfSafrvP01TZ+70pbAdUxS74CrMPxKjkg4gfL0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=XnCjYAFjUG2J7aUEI5+HNXOBHicvRXXUj0RVquzvGXp3pMRyJJ6lUrfAbLcsaEw1AJr1O5bl1qEBWH+sxPBd1K3SRCyp8ua5kubuHN628TIEjKRVkAVLye6kd0PntzyL7bX9srFShVUnzdYsKW9My2kne0kNmkkPujKNkBUOzFk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Zcnos1hV; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Zcnos1hV" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 508MqDwv081041; Wed, 8 Jan 2025 16:52:13 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1736376733; bh=B9mvSUZhe0Gs54mE7MNJ44HT1A+T/9sT90UthccBd5g=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=Zcnos1hVIL9p58Nrt4+8ae4JuYezcAdOHGqMqKq2dKtSw1H+DBfKN6C++l0xqaQd4 lqjvw7QdNxPtc3SYTVOLHoqkOgIYj568lYwU+XHucGDVgtD0N5pMXfe+Z+7mHNNIbO lZYkUrvnEp80CxNbjuNQVq+CMof4GecEFOBurSTs= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 508MqDhv080915 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 8 Jan 2025 16:52:13 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 8 Jan 2025 16:52:12 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 8 Jan 2025 16:52:12 -0600 Received: from localhost (bb.dhcp.ti.com [128.247.81.12]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 508MqCNw019025; Wed, 8 Jan 2025 16:52:12 -0600 From: Bryan Brattlof Date: Wed, 8 Jan 2025 16:51:53 -0600 Subject: [PATCH v2 1/3] dt-bindings: arm: ti: Add binding for AM62L SoCs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250108-am62lx-v2-1-581285a37d8f@ti.com> References: <20250108-am62lx-v2-0-581285a37d8f@ti.com> In-Reply-To: <20250108-am62lx-v2-0-581285a37d8f@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Bryan Brattlof X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=890; i=bb@ti.com; h=from:subject:message-id; bh=9zjr0PfSafrvP01TZ+70pbAdUxS74CrMPxKjkg4gfL0=; b=owNCWmg5MUFZJlNZI8PS+QAAYf///v5txq1/7/+1nuXF392TnNd/9teT7///3O/+/9Nv8c2wA RswIeoGgNDQ0AGgyBoNNDRkBkGhpkAaAAaaGhoANBpk0BoNDRoNPUyBkyaaMTGmUQaZDTRpo2oM gNBkAAyMjQYgaMhkAyZpND1GjIAAaBpoAA0NMEA0GhpoyaZNCGRiMIGgyNBkAMjBDENNGmQ0BkN GmhgIZGgaMgYQABkGgyA0yNAAADAQLBDVQNPh3PkBPQYlRDxc7bjgiHaNBpCNEwBwa6ALVsmV1r rKO9wDQCT3m6/Uw3tKgJEoXoOY4BXgRmujnRrqRhZ39kv2u6YChMSsq+9A9IQTzz2/F028fVXkX nsqXiAWG64LLwPn9qFgJdzctFQ7zJcqSjVtclqrzriFUcIWXKhE9xw0APaChMlJpl2QIr4+tsHO Px9GxjbEhsUCh2PEloxOdGOGUUjpsUoKSLSiir7FISr1Larnq5ktqBENOgOEQmuc4CP+Biozpoi ogGag72BB2Cl+JYaHaPo0LsDMZXU7HD5Ty8WrI/hzueWwO6iKm25dd9qQycCLucdIfljDUQaCzF FzjcmAyXymYA4Gm2SFymWDRwRZstAqrPBJNUBhwcQ4Wk2sAxCI8q6CtmYYpOI6OhSoSUCHF5wPm JvC2Z10IJ/i7kinChIEeHpfIA== X-Developer-Key: i=bb@ti.com; a=openpgp; fpr=D3D177E40A38DF4D1853FEEF41B90D5D71D56CE0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Add the binding for TI's AM62L family of devices. Signed-off-by: Bryan Brattlof Acked-by: Krzysztof Kozlowski --- Changes in v1: - separated out devicetree bindings --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentati= on/devicetree/bindings/arm/ti/k3.yaml index 18f155cd06c84..b109e854879cb 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -31,6 +31,12 @@ properties: - const: phytec,am62a-phycore-som - const: ti,am62a7 =20 + - description: K3 AM62L3 SoC and Boards + items: + - enum: + - ti,am62l3-evm + - const: ti,am62l3 + - description: K3 AM62P5 SoC and Boards items: - enum: --=20 2.47.1 From nobody Fri Dec 19 19:18:44 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36F2E205502; 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Wed, 8 Jan 2025 16:52:13 -0600 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 8 Jan 2025 16:52:12 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 8 Jan 2025 16:52:13 -0600 Received: from localhost (bb.dhcp.ti.com [128.247.81.12]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 508MqCRb038349; Wed, 8 Jan 2025 16:52:12 -0600 From: Bryan Brattlof Date: Wed, 8 Jan 2025 16:51:54 -0600 Subject: [PATCH v2 2/3] arm64: dts: ti: k3-am62l: add initial infrastructure Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250108-am62lx-v2-2-581285a37d8f@ti.com> References: <20250108-am62lx-v2-0-581285a37d8f@ti.com> In-Reply-To: <20250108-am62lx-v2-0-581285a37d8f@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Bryan Brattlof X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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ALl of which can be found in the Technical Reference Manual (TRM) located here: https://www.ti.com/lit/ug/sprujb4/sprujb4.pdf Signed-off-by: Vignesh Raghavendra Signed-off-by: Bryan Brattlof --- Changes in v1: - switched to non-direct links to TRM updates are automatic - fixed white space indent issues with a few nodes - separated out device tree bindings --- arch/arm64/boot/dts/ti/Makefile | 3 + arch/arm64/boot/dts/ti/k3-am62l-main.dtsi | 52 +++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi | 33 +++++++++++ arch/arm64/boot/dts/ti/k3-am62l.dtsi | 89 +++++++++++++++++++++++++= ++++ arch/arm64/boot/dts/ti/k3-am62l3.dtsi | 67 ++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-pinctrl.h | 2 + 6 files changed, 246 insertions(+) diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index f71360f14f233..6745f779b1e6e 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -32,6 +32,9 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-am62-lp-sk-nand.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am62a7-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am62a7-phyboard-lyra-rdk.dtb =20 +# Boards with AM62Lx SoCs +dtb-$(CONFIG_ARCH_K3) +=3D k3-am62l3-evm.dtb + # Boards with AM62Px SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am62p5-sk.dtb =20 diff --git a/arch/arm64/boot/dts/ti/k3-am62l-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62l-main.dtsi new file mode 100644 index 0000000000000..3fc3474df3dba --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62l-main.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree file for the AM62L main domain peripherals + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +&cbass_main { + gic500: interrupt-controller@1800000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x00 0x01800000 0x00 0x10000>, /* GICD */ + <0x00 0x01840000 0x00 0xc0000>, /* GICR */ + <0x01 0x00000000 0x00 0x2000>, /* GICC */ + <0x01 0x00010000 0x00 0x1000>, /* GICH */ + <0x01 0x00020000 0x00 0x2000>; /* GICV */ + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + #interrupt-cells =3D <3>; + interrupt-controller; + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts =3D ; + + gic_its: msi-controller@1820000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its =3D <0x1000000 0x400000>; + msi-controller; + #msi-cells =3D <1>; + }; + }; + + main_uart0: serial@2800000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02800000 0x00 0x100>; + interrupts =3D ; + clock-frequency =3D <48000000>; + status =3D "disabled"; + }; + + oc_sram: sram@70800000 { + compatible =3D "mmio-sram"; + reg =3D <0x00 0x70800000 0x00 0x10000>; + ranges =3D <0x0 0x00 0x70800000 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi b/arch/arm64/boot/= dts/ti/k3-am62l-wakeup.dtsi new file mode 100644 index 0000000000000..b09b7c679d0b9 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree file for the AM62L wakeup domain peripherals + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +&cbass_wakeup { + pmx0: pinctrl@4084000 { + compatible =3D "pinctrl-single"; + reg =3D <0x00 0x4084000 0x00 0x8000>; + pinctrl-single,register-width =3D <32>; + pinctrl-single,function-mask =3D <0xffffffff>; + #pinctrl-cells =3D <1>; + bootph-all; + }; + + wkup_conf: bus@43000000 { + compatible =3D "simple-bus"; + reg =3D <0x00 0x43000000 0x00 0x20000>; + ranges =3D <0x0 0x00 0x43000000 0x20000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + chipid: chipid@14 { + compatible =3D "ti,am654-chipid"; + reg =3D <0x14 0x4>; + bootph-all; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/ti/k3-am62l.dtsi b/arch/arm64/boot/dts/ti/= k3-am62l.dtsi new file mode 100644 index 0000000000000..5a77f32d1eb18 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62l.dtsi @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree Source for AM62L SoC Family + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +#include +#include +#include + +#include "k3-pinctrl.h" + +/ { + model =3D "Texas Instruments K3 AM62L3 SoC"; + compatible =3D "ti,am62l3"; + interrupt-parent =3D <&gic500>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + firmware { + optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible =3D "arm,armv8-timer"; + interrupts =3D , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + }; + + pmu: pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D ; + }; + + cbass_main: bus@f0000 { + compatible =3D "simple-bus"; + ranges =3D <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router = */ + <0x00 0x00a80000 0x00 0x00a80000 0x00 0x00040000>, /* GTC */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral= window */ + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* CPSW */ + <0x00 0x09000000 0x00 0x09000000 0x00 0x00400000>, /* CTRL MMRs */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x0bd28000>, /* Second periphera= l window */ + <0x00 0x30200000 0x00 0x30200000 0x00 0x00400000>, /* DSS */ + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core w= indow */ + <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core w= indow */ + <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00001000>, /* GPMC0 */ + <0x00 0x47000000 0x00 0x47000000 0x00 0x02000000>, /* DMSS */ + <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC DATA */ + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ + <0x00 0x70800000 0x00 0x70800000 0x00 0x00010000>, /* OCSRAM */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ + + /* Wakeup Domain Range */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */ + <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDCFG */ + <0x00 0x04201000 0x00 0x04201000 0x00 0x00008000>, /* GPIO */ + <0x00 0x2b100000 0x00 0x2b000000 0x00 0x00200400>, /* TIMER */ + <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */ + #address-cells =3D <2>; + #size-cells =3D <2>; + + cbass_wakeup: bus@43000000 { + compatible =3D "simple-bus"; + ranges =3D <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */ + <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDCFG */ + <0x00 0x04201000 0x00 0x04201000 0x00 0x00008000>, /* GPIO */ + <0x00 0x2b100000 0x00 0x2b000000 0x00 0x00200400>, /* TIMER */ + <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */ + #address-cells =3D <2>; + #size-cells =3D <2>; + bootph-all; + }; + }; +}; + +/* Now include peripherals for each bus segment */ +#include "k3-am62l-main.dtsi" +#include "k3-am62l-wakeup.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62l3.dtsi b/arch/arm64/boot/dts/ti= /k3-am62l3.dtsi new file mode 100644 index 0000000000000..aa679e8e6a9c2 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62l3.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree file for the AM62L3 SoC family (Dual Core A53) + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +/dts-v1/; + +#include "k3-am62l.dtsi" + +/ { + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x000>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + }; + + cpu1: cpu@1 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x001>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + }; + }; + + l2_0: l2-cache0 { + compatible =3D "cache"; + cache-unified; + cache-level =3D <2>; + cache-size =3D <0x40000>; + cache-line-size =3D <64>; + cache-sets =3D <256>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k= 3-pinctrl.h index cac7cccc11121..0121413399d63 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -66,6 +66,8 @@ #define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) #define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mux= mode)) =20 +#define AM62LX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) + #define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode= )) #define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxm= ode)) =20 --=20 2.47.1 From nobody Fri Dec 19 19:18:44 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3872D205507; Wed, 8 Jan 2025 22:53:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Vignesh Raghavendra Signed-off-by: Bryan Brattlof --- Changes in v1: - switched to non-direct links so TRM updates are automatic - removed current-speed property from main_uart0 - removed empty reserved-memory{} node - removed serial2 from aliases{} node - corrected main_uart0 pinmux --- arch/arm64/boot/dts/ti/k3-am62l3-evm.dts | 43 ++++++++++++++++++++++++++++= ++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts b/arch/arm64/boot/dts= /ti/k3-am62l3-evm.dts new file mode 100644 index 0000000000000..ed0148ce1bea6 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree file for the AM62L3 Evaluation Module + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +/dts-v1/; + +#include "k3-am62l3.dtsi" + +/ { + compatible =3D "ti,am62l3-evm", "ti,am62l3"; + model =3D "Texas Instruments AM62L3 Evaluation Module"; + + chosen { + stdout-path =3D &main_uart0; + }; + + memory@80000000 { + reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>; + device_type =3D "memory"; + bootph-all; + }; +}; + +&pmx0 { + main_uart0_pins_default: main_uart0-default-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x01b4, PIN_INPUT, 0) /* (D13) UART0_RXD */ + AM62PX_IOPAD(0x01b8, PIN_OUTPUT, 0) /* (C13) UART0_TXD */ + >; + bootph-all; + }; +}; + +&main_uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_uart0_pins_default>; + status =3D "okay"; + bootph-all; +}; --=20 2.47.1