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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jan 2025 22:29:11.4956 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 99ef55e5-7978-4fcf-8ec5-08dd2f6ab59d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066E7.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8939 Content-Type: text/plain; charset="utf-8" There are more than one SMN index/data pair available for software use. The register offsets are different, but the protocol is the same. Use defines for the SMN offset values and allow the index/data offsets to be passed to the read/write helper function. This eases code reuse with other SMN users in the kernel. Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov (AMD) Link: https://lore.kernel.org/r/20241206161210.163701-14-yazen.ghannam@amd.= com --- arch/x86/kernel/amd_node.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/amd_node.c b/arch/x86/kernel/amd_node.c index 45077e2e6f2f..d2ec7fd555c5 100644 --- a/arch/x86/kernel/amd_node.c +++ b/arch/x86/kernel/amd_node.c @@ -94,6 +94,9 @@ static struct pci_dev **amd_roots; /* Protect the PCI config register pairs used for SMN. */ static DEFINE_MUTEX(smn_mutex); =20 +#define SMN_INDEX_OFFSET 0x60 +#define SMN_DATA_OFFSET 0x64 + /* * SMN accesses may fail in ways that are difficult to detect here in the = called * functions amd_smn_read() and amd_smn_write(). Therefore, callers must do @@ -131,7 +134,7 @@ static DEFINE_MUTEX(smn_mutex); * the operation is considered a success, and the caller does their own * checking. */ -static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write) +static int __amd_smn_rw(u8 i_off, u8 d_off, u16 node, u32 address, u32 *va= lue, bool write) { struct pci_dev *root; int err =3D -ENODEV; @@ -145,21 +148,21 @@ static int __amd_smn_rw(u16 node, u32 address, u32 *v= alue, bool write) =20 guard(mutex)(&smn_mutex); =20 - err =3D pci_write_config_dword(root, 0x60, address); + err =3D pci_write_config_dword(root, i_off, address); if (err) { pr_warn("Error programming SMN address 0x%x.\n", address); return pcibios_err_to_errno(err); } =20 - err =3D (write ? pci_write_config_dword(root, 0x64, *value) - : pci_read_config_dword(root, 0x64, value)); + err =3D (write ? pci_write_config_dword(root, d_off, *value) + : pci_read_config_dword(root, d_off, value)); =20 return pcibios_err_to_errno(err); } =20 int __must_check amd_smn_read(u16 node, u32 address, u32 *value) { - int err =3D __amd_smn_rw(node, address, value, false); + int err =3D __amd_smn_rw(SMN_INDEX_OFFSET, SMN_DATA_OFFSET, node, address= , value, false); =20 if (PCI_POSSIBLE_ERROR(*value)) { err =3D -ENODEV; @@ -172,7 +175,7 @@ EXPORT_SYMBOL_GPL(amd_smn_read); =20 int __must_check amd_smn_write(u16 node, u32 address, u32 value) { - return __amd_smn_rw(node, address, &value, true); + return __amd_smn_rw(SMN_INDEX_OFFSET, SMN_DATA_OFFSET, node, address, &va= lue, true); } EXPORT_SYMBOL_GPL(amd_smn_write); =20 --=20 2.43.0