From nobody Wed Dec 17 16:18:02 2025 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 842961F7069 for ; Tue, 7 Jan 2025 20:08:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736280494; cv=none; b=a7bB1ypyapAoRSh6gHGQ4e59n2/7+HivDmGQklP1kkbFWsACkl0XVzyNh5SchLDzSX8+aH50sVYod/TesBnMyi6l8m48NnnnC+xWgNEtj4mgd8LOVwyD/eBI2yHdwFcS81AO0e77cHXE/BAo5Fq6JAq1hn6+WW3EDfbANsp/V2Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736280494; c=relaxed/simple; bh=4/CkRjq9kcUokUjRmbo9S34/t4UeumZJsbesld2STWQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=J90eOeqCZ7coR2Lgz65Oi8yl47v4PuJnoMLh0EJa8wo7m+ZKseShRssCwqwXE14TC/CAMZLn4lKlOq3BZW6jV91PPJpdbtueXhL/zvaFKbrl+gR0ISu3xzWx+ryly5wvA8/l+DmZnpOnEwwqa5G98+QlyWMUdjnXPBbb750cIXA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=ROePip+n; arc=none smtp.client-ip=209.85.214.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="ROePip+n" Received: by mail-pl1-f175.google.com with SMTP id d9443c01a7336-21669fd5c7cso239545325ad.3 for ; Tue, 07 Jan 2025 12:08:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1736280490; x=1736885290; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0KrxwWdw54K0Yj+RKR+q5UWCVF10MxJgob7ZMKnFuvw=; b=ROePip+nHNwLAIrpFg+8tCzs0mL0XCNKxdWTETBa5ccyD7IC50fw45pgflCDLr4oME IwUbRt3pUa/4FcO43ZfuqO7RJ4/+mJQP9EM0Afy2WPPBQ9oBuF+6eV+fkPtH2UrQFNmU 0en5z+fIWWEAP4RSqaMqWD0catzTAQyc8rxnc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736280490; x=1736885290; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0KrxwWdw54K0Yj+RKR+q5UWCVF10MxJgob7ZMKnFuvw=; b=sqy4XlGioChIqKAa+XAnmiJZG+T4wtcXkwg4EWSW0bWRWioGvYMfQZ+Q0CrEZ+q8a5 sd98dBAIuQwVxuHFoC2RaZTOgOkk8lofqd75/F5u+9ucl8CiWvN3KTkUut3xndABpco/ a7kA9HzEyW8cl/r+IF7jwG+BqT+nVzPgPFNmKBR3aKpEoOGq/Q2acjEbew9UpJlh3+jW +UVL2IO9A6k2M89uFBMjTheJQHPgIDLZli76x5UKAiMbrTVhEozPsxPsu0vXg/iIOxxC pfoTbQbea3uH56r4hHwE4vnx2BiZGsAXWGmym+bG7ILssmZd1Elf9ejZt5DlBIhqd1IV ++0w== X-Forwarded-Encrypted: i=1; AJvYcCX7R6L5V/szLexKyNpMAkdtqAajQkVVdF+gbaDQ2gHPOLP4IHlpgrGSaJPuQQnrfYG2r67E2IF3rHL1OQA=@vger.kernel.org X-Gm-Message-State: AOJu0Yx3ObeKuFWP/xQmqw5q7pSFOCHwZR/YprP+uBzr46C3YSpIp04w plYukj7sG57Q1rqUAyc5bnV1IzYRkRlwyHZe5TF9eh31qJy7To7PmNgC5TgSIA== X-Gm-Gg: ASbGncsOO6/l0M/QMrXNTG6BE1pAoZ5pXJ13VXCtaazW10Tg4PiamzRXFzHrsRkMlWO HPRpMHiuaW9L9McRg8sooXYSt99BezqTM0u2n+GbGFVGIP3F6gx3gX8SywL0FOhDFG+wH1J8T9d 8h8rYa6j35CFxb+lCjvFjxKAo5pgGbM+cC8Bat9u7xKtiyPxKmQHLc8qCDt0442hQbKHWhkv83s RmzLwid7EaZN5khCMSdPL2m1OHh/9eABrE7DIAL2PwLv6aN+UeMdDKyTF+kvSUNcX6oAJfF6Zb+ X-Google-Smtp-Source: AGHT+IGlYlv+o4b4M4lfyay2yfIQhWPrIig5AxGmXyZ7/rDfeJh96vHrE9iSzFs341VZqJN1Vu/LmA== X-Received: by 2002:a17:902:d48b:b0:216:2bd7:1c2f with SMTP id d9443c01a7336-21a83f5510emr4528055ad.18.1736280489913; Tue, 07 Jan 2025 12:08:09 -0800 (PST) Received: from dianders.sjc.corp.google.com ([2620:15c:9d:2:2961:4bbc:5703:5820]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc962d47sm314263425ad.55.2025.01.07.12.08.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jan 2025 12:08:09 -0800 (PST) From: Douglas Anderson To: Catalin Marinas , Will Deacon , Mark Rutland Cc: Roxana Bradescu , Julius Werner , bjorn.andersson@oss.qualcomm.com, Trilok Soni , linux-arm-msm@vger.kernel.org, Florian Fainelli , linux-arm-kernel@lists.infradead.org, Jeffrey Hugo , Scott Bauer , Douglas Anderson , stable@vger.kernel.org, James Morse , linux-kernel@vger.kernel.org Subject: [PATCH v4 1/5] arm64: errata: Add QCOM_KRYO_4XX_GOLD to the spectre_bhb_k24_list Date: Tue, 7 Jan 2025 12:05:58 -0800 Message-ID: <20250107120555.v4.1.Ie4ef54abe02e7eb0eee50f830575719bf23bda48@changeid> X-Mailer: git-send-email 2.47.1.613.gc27f4b7a9f-goog In-Reply-To: <20250107200715.422172-1-dianders@chromium.org> References: <20250107200715.422172-1-dianders@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Qualcomm Kryo 400-series Gold cores have a derivative of an ARM Cortex A76 in them. Since A76 needs Spectre mitigation via looping then the Kyro 400-series Gold cores also need Spectre mitigation via looping. Qualcomm has confirmed that the proper "k" value for Kryo 400-series Gold cores is 24. Fixes: 558c303c9734 ("arm64: Mitigate spectre style branch history side cha= nnels") Cc: stable@vger.kernel.org Cc: Scott Bauer Signed-off-by: Douglas Anderson Acked-by: Trilok Soni --- Changes in v4: - Re-added QCOM_KRYO_4XX_GOLD k24 patch after Qualcomm confirmed. Changes in v3: - Removed QCOM_KRYO_4XX_GOLD k24 patch. Changes in v2: - Slight change to wording and notes of KRYO_4XX_GOLD patch arch/arm64/kernel/proton-pack.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pac= k.c index da53722f95d4..e149efadff20 100644 --- a/arch/arm64/kernel/proton-pack.c +++ b/arch/arm64/kernel/proton-pack.c @@ -866,6 +866,7 @@ u8 spectre_bhb_loop_affected(int scope) MIDR_ALL_VERSIONS(MIDR_CORTEX_A76), MIDR_ALL_VERSIONS(MIDR_CORTEX_A77), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), + MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_GOLD), {}, }; static const struct midr_range spectre_bhb_k11_list[] =3D { --=20 2.47.1.613.gc27f4b7a9f-goog From nobody Wed Dec 17 16:18:02 2025 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C45AD1F709C for ; Tue, 7 Jan 2025 20:08:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736280497; cv=none; b=hlG69yFc/IHUVzxOCOdl84zNjjB8frUjcyw2DHigaSzSlf1YryfyAKNlABwUGO67YZ3Eb6BZrtNr4VlFjv4BVDrc5A+t/krvbKh+w8nyvMOHrf8WxWjEhhxXJFm/THl77agMZPXNq9UxvsywIFqJeFthLhcLOeJQzGjyEAg99rI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736280497; c=relaxed/simple; bh=MRkbf/QMZ2Xws76DUZvOddSWdEn9he72mIsqwKwolEA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hc2WxMQXryt5dKsh9ii4oujZ7rVQGFEnX9MSup1XxN4arcNzDnvYuniz9BuEmmT9d0u1Y8w7dLdTLQXG/ShB7E3nkwp/Bi2WmBWXuzveGbMPwVEtmpVKb15BjyBsRSrWgFsuaI2HBG8HgWe70VHp3aRHArlhFB+3KeUAOrglPhc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=RhA7FK08; arc=none smtp.client-ip=209.85.214.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="RhA7FK08" Received: by mail-pl1-f171.google.com with SMTP id d9443c01a7336-2166f1e589cso18267055ad.3 for ; Tue, 07 Jan 2025 12:08:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1736280492; x=1736885292; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VyuPoGoas0FXrrfma5oME99Ny+q0qNNG5nUGFTCnZN8=; b=RhA7FK08i7SDwuPkB/tAExQPmVzXtuCU3N623gajAXV1oql6O8VgnJUe6BfThXChOE RWNA9WmkeMxuVGS02tEQTso5KcNLDbAUdQJzELyG1PojW1+VV3E+YzD2pXqXxR05T06R 88xAZWw2NG3H4h6MH4Pi9KaD5dfSwfn2CzdDA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736280492; x=1736885292; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VyuPoGoas0FXrrfma5oME99Ny+q0qNNG5nUGFTCnZN8=; b=jKXsvoVo9IztebEZcnLekIYSiP7T4VBJiu5hr2YZp2xLa2qxo7Cb+6mPPkZ3xFmty1 EPeWS3eXD0dGh0/ImkMopdHNHwZC4a9U4FG79KXgXwuj2TAjJsaBB0Yo2m0BwCegYItP Vr55VvESzVhZ7j0B3Ak21VsxPXD9y3G4eAArHN70ALC3MqnthmA1adw9qGI5YB0J+mM6 ZePYTyU15WksyORCnP2KosX5sXDGMrc1TZUa0W5WveTN0ujJVyqTWS6iNSUo3q2WG7eW xTJKPBmo1BzhylopV3gjlPk73GI6fUdWGXEFGbAVxs2UbSjbuESK75XGGbaMpdctR2VQ yORg== X-Forwarded-Encrypted: i=1; AJvYcCWXSo2wK5LiAtUy7cVMpnl2pDDgCWBP3B+gazldHFndxuVEeG5s5GlUziQ6dWI1YIHDZZqKdESEKjhBOIo=@vger.kernel.org X-Gm-Message-State: AOJu0Yyk2ipa3BCxTVMFGeSLWMCYq4Uc0Ly31sSTmG3CdrckyQMNMGkq gfU8faYZbhq/kZwHzJwiwOqDGhjf8qFCxYYe3ofEnoL9345v0FfUrUG1mf5SoA== X-Gm-Gg: ASbGncvgqsuv9CDWoMIOL3RON1UNBWMT684AICyP8HSvjzXENEuIQqupL6xq5dvqtY7 Hf/iMHBrexoqhlA4D9Atc+r2mChxDRhuMHQa8jLxhXrQ1OlqGX1yVfD0cyEjQ3YoQMuRBteuShR 1T3eb2/99hlehNrsu9jNVu6ogm3s4MMS/td18IrYrGX4py0HswNLwBrcC4KvZ/lTanPliSG2cmZ aB+NOGkSpLqWMb2kwfPFQqZ/eri0zcvtJKOMWfNtF5jpkYSfLT4NRJ3BmULtpeV4hoFHZAwWDX2 X-Google-Smtp-Source: AGHT+IH9SDkWGRhHf89AC8Lyy6Me9FNM2MneEbrONqwNlFgWCin4uJi7+v53aHD2Xs3q0+CE3HhNxg== X-Received: by 2002:a17:903:32cf:b0:216:644f:bc0e with SMTP id d9443c01a7336-21a83f502aemr4816215ad.24.1736280492102; Tue, 07 Jan 2025 12:08:12 -0800 (PST) Received: from dianders.sjc.corp.google.com ([2620:15c:9d:2:2961:4bbc:5703:5820]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc962d47sm314263425ad.55.2025.01.07.12.08.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jan 2025 12:08:11 -0800 (PST) From: Douglas Anderson To: Catalin Marinas , Will Deacon , Mark Rutland Cc: Roxana Bradescu , Julius Werner , bjorn.andersson@oss.qualcomm.com, Trilok Soni , linux-arm-msm@vger.kernel.org, Florian Fainelli , linux-arm-kernel@lists.infradead.org, Jeffrey Hugo , Scott Bauer , Douglas Anderson , stable@vger.kernel.org, James Morse , linux-kernel@vger.kernel.org Subject: [PATCH v4 2/5] arm64: errata: Assume that unknown CPUs _are_ vulnerable to Spectre BHB Date: Tue, 7 Jan 2025 12:05:59 -0800 Message-ID: <20250107120555.v4.2.I2040fa004dafe196243f67ebcc647cbedbb516e6@changeid> X-Mailer: git-send-email 2.47.1.613.gc27f4b7a9f-goog In-Reply-To: <20250107200715.422172-1-dianders@chromium.org> References: <20250107200715.422172-1-dianders@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The code for detecting CPUs that are vulnerable to Spectre BHB was based on a hardcoded list of CPU IDs that were known to be affected. Unfortunately, the list mostly only contained the IDs of standard ARM cores. The IDs for many cores that are minor variants of the standard ARM cores (like many Qualcomm Kyro CPUs) weren't listed. This led the code to assume that those variants were not affected. Flip the code on its head and instead assume that a core is vulnerable if it doesn't have CSV2_3 but is unrecognized as being safe. This involves creating a "Spectre BHB safe" list. As of right now, the only CPU IDs added to the "Spectre BHB safe" list are ARM Cortex A35, A53, A55, A510, and A520. This list was created by looking for cores that weren't listed in ARM's list [1] as per review feedback on v2 of this patch [2]. Additionally Brahma A53 is added as per mailing list feedback [3]. NOTE: this patch will not actually _mitigate_ anyone, it will simply cause them to report themselves as vulnerable. If any cores in the system are reported as vulnerable but not mitigated then the whole system will be reported as vulnerable though the system will attempt to mitigate with the information it has about the known cores. [1] https://developer.arm.com/Arm%20Security%20Center/Spectre-BHB [2] https://lore.kernel.org/r/20241219175128.GA25477@willie-the-truck [3] https://lore.kernel.org/r/18dbd7d1-a46c-4112-a425-320c99f67a8d@broadcom= .com Fixes: 558c303c9734 ("arm64: Mitigate spectre style branch history side cha= nnels") Cc: stable@vger.kernel.org Reviewed-by: Julius Werner Signed-off-by: Douglas Anderson --- Changes in v4: - Add MIDR_BRAHMA_B53 as safe. - Get rid of `spectre_bhb_firmware_mitigated_list`. Changes in v3: - Don't guess the mitigation; just report unknown cores as vulnerable. - Restructure the code since is_spectre_bhb_affected() defaults to true Changes in v2: - New arch/arm64/include/asm/spectre.h | 1 - arch/arm64/kernel/proton-pack.c | 203 ++++++++++++++++--------------- 2 files changed, 102 insertions(+), 102 deletions(-) diff --git a/arch/arm64/include/asm/spectre.h b/arch/arm64/include/asm/spec= tre.h index 0c4d9045c31f..f1524cdeacf1 100644 --- a/arch/arm64/include/asm/spectre.h +++ b/arch/arm64/include/asm/spectre.h @@ -97,7 +97,6 @@ enum mitigation_state arm64_get_meltdown_state(void); =20 enum mitigation_state arm64_get_spectre_bhb_state(void); bool is_spectre_bhb_affected(const struct arm64_cpu_capabilities *entry, i= nt scope); -u8 spectre_bhb_loop_affected(int scope); void spectre_bhb_enable_mitigation(const struct arm64_cpu_capabilities *__= unused); bool try_emulate_el1_ssbs(struct pt_regs *regs, u32 instr); =20 diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pac= k.c index e149efadff20..17aa836fe46d 100644 --- a/arch/arm64/kernel/proton-pack.c +++ b/arch/arm64/kernel/proton-pack.c @@ -845,53 +845,70 @@ static unsigned long system_bhb_mitigations; * This must be called with SCOPE_LOCAL_CPU for each type of CPU, before a= ny * SCOPE_SYSTEM call will give the right answer. */ -u8 spectre_bhb_loop_affected(int scope) +static bool is_spectre_bhb_safe(int scope) +{ + static const struct midr_range spectre_bhb_safe_list[] =3D { + MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A510), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A520), + MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), + {}, + }; + static bool all_safe =3D true; + + if (scope !=3D SCOPE_LOCAL_CPU) + return all_safe; + + if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_safe_list)) + return true; + + all_safe =3D false; + + return false; +} + +static u8 spectre_bhb_loop_affected(void) { u8 k =3D 0; - static u8 max_bhb_k; - - if (scope =3D=3D SCOPE_LOCAL_CPU) { - static const struct midr_range spectre_bhb_k32_list[] =3D { - MIDR_ALL_VERSIONS(MIDR_CORTEX_A78), - MIDR_ALL_VERSIONS(MIDR_CORTEX_A78AE), - MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C), - MIDR_ALL_VERSIONS(MIDR_CORTEX_X1), - MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), - MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), - MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), - MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), - {}, - }; - static const struct midr_range spectre_bhb_k24_list[] =3D { - MIDR_ALL_VERSIONS(MIDR_CORTEX_A76), - MIDR_ALL_VERSIONS(MIDR_CORTEX_A77), - MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), - MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_GOLD), - {}, - }; - static const struct midr_range spectre_bhb_k11_list[] =3D { - MIDR_ALL_VERSIONS(MIDR_AMPERE1), - {}, - }; - static const struct midr_range spectre_bhb_k8_list[] =3D { - MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), - MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), - {}, - }; - - if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k32_list)) - k =3D 32; - else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k24_list)) - k =3D 24; - else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k11_list)) - k =3D 11; - else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k8_list)) - k =3D 8; - - max_bhb_k =3D max(max_bhb_k, k); - } else { - k =3D max_bhb_k; - } + + static const struct midr_range spectre_bhb_k32_list[] =3D { + MIDR_ALL_VERSIONS(MIDR_CORTEX_A78), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A78AE), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X1), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), + {}, + }; + static const struct midr_range spectre_bhb_k24_list[] =3D { + MIDR_ALL_VERSIONS(MIDR_CORTEX_A76), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A77), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), + MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_GOLD), + {}, + }; + static const struct midr_range spectre_bhb_k11_list[] =3D { + MIDR_ALL_VERSIONS(MIDR_AMPERE1), + {}, + }; + static const struct midr_range spectre_bhb_k8_list[] =3D { + MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), + {}, + }; + + if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k32_list)) + k =3D 32; + else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k24_list)) + k =3D 24; + else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k11_list)) + k =3D 11; + else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k8_list)) + k =3D 8; =20 return k; } @@ -917,29 +934,13 @@ static enum mitigation_state spectre_bhb_get_cpu_fw_m= itigation_state(void) } } =20 -static bool is_spectre_bhb_fw_affected(int scope) +static bool has_spectre_bhb_fw_mitigation(void) { - static bool system_affected; enum mitigation_state fw_state; bool has_smccc =3D arm_smccc_1_1_get_conduit() !=3D SMCCC_CONDUIT_NONE; - static const struct midr_range spectre_bhb_firmware_mitigated_list[] =3D { - MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), - MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), - {}, - }; - bool cpu_in_list =3D is_midr_in_range_list(read_cpuid_id(), - spectre_bhb_firmware_mitigated_list); - - if (scope !=3D SCOPE_LOCAL_CPU) - return system_affected; =20 fw_state =3D spectre_bhb_get_cpu_fw_mitigation_state(); - if (cpu_in_list || (has_smccc && fw_state =3D=3D SPECTRE_MITIGATED)) { - system_affected =3D true; - return true; - } - - return false; + return has_smccc && fw_state =3D=3D SPECTRE_MITIGATED; } =20 static bool supports_ecbhb(int scope) @@ -955,6 +956,8 @@ static bool supports_ecbhb(int scope) ID_AA64MMFR1_EL1_ECBHB_SHIFT); } =20 +static u8 max_bhb_k; + bool is_spectre_bhb_affected(const struct arm64_cpu_capabilities *entry, int scope) { @@ -963,16 +966,18 @@ bool is_spectre_bhb_affected(const struct arm64_cpu_c= apabilities *entry, if (supports_csv2p3(scope)) return false; =20 - if (supports_clearbhb(scope)) - return true; - - if (spectre_bhb_loop_affected(scope)) - return true; + if (is_spectre_bhb_safe(scope)) + return false; =20 - if (is_spectre_bhb_fw_affected(scope)) - return true; + /* + * At this point the core isn't known to be "safe" so we're going to + * assume it's vulnerable. We still need to update `max_bhb_k` though, + * but only if we aren't mitigating with clearbhb though. + */ + if (scope =3D=3D SCOPE_LOCAL_CPU && !supports_clearbhb(SCOPE_LOCAL_CPU)) + max_bhb_k =3D max(max_bhb_k, spectre_bhb_loop_affected()); =20 - return false; + return true; } =20 static void this_cpu_set_vectors(enum arm64_bp_harden_el1_vectors slot) @@ -1003,7 +1008,7 @@ early_param("nospectre_bhb", parse_spectre_bhb_param); void spectre_bhb_enable_mitigation(const struct arm64_cpu_capabilities *en= try) { bp_hardening_cb_t cpu_cb; - enum mitigation_state fw_state, state =3D SPECTRE_VULNERABLE; + enum mitigation_state state =3D SPECTRE_VULNERABLE; struct bp_hardening_data *data =3D this_cpu_ptr(&bp_hardening_data); =20 if (!is_spectre_bhb_affected(entry, SCOPE_LOCAL_CPU)) @@ -1029,7 +1034,7 @@ void spectre_bhb_enable_mitigation(const struct arm64= _cpu_capabilities *entry) this_cpu_set_vectors(EL1_VECTOR_BHB_CLEAR_INSN); state =3D SPECTRE_MITIGATED; set_bit(BHB_INSN, &system_bhb_mitigations); - } else if (spectre_bhb_loop_affected(SCOPE_LOCAL_CPU)) { + } else if (spectre_bhb_loop_affected()) { /* * Ensure KVM uses the indirect vector which will have the * branchy-loop added. A57/A72-r0 will already have selected @@ -1042,32 +1047,29 @@ void spectre_bhb_enable_mitigation(const struct arm= 64_cpu_capabilities *entry) this_cpu_set_vectors(EL1_VECTOR_BHB_LOOP); state =3D SPECTRE_MITIGATED; set_bit(BHB_LOOP, &system_bhb_mitigations); - } else if (is_spectre_bhb_fw_affected(SCOPE_LOCAL_CPU)) { - fw_state =3D spectre_bhb_get_cpu_fw_mitigation_state(); - if (fw_state =3D=3D SPECTRE_MITIGATED) { - /* - * Ensure KVM uses one of the spectre bp_hardening - * vectors. The indirect vector doesn't include the EL3 - * call, so needs upgrading to - * HYP_VECTOR_SPECTRE_INDIRECT. - */ - if (!data->slot || data->slot =3D=3D HYP_VECTOR_INDIRECT) - data->slot +=3D 1; - - this_cpu_set_vectors(EL1_VECTOR_BHB_FW); - - /* - * The WA3 call in the vectors supersedes the WA1 call - * made during context-switch. Uninstall any firmware - * bp_hardening callback. - */ - cpu_cb =3D spectre_v2_get_sw_mitigation_cb(); - if (__this_cpu_read(bp_hardening_data.fn) !=3D cpu_cb) - __this_cpu_write(bp_hardening_data.fn, NULL); - - state =3D SPECTRE_MITIGATED; - set_bit(BHB_FW, &system_bhb_mitigations); - } + } else if (has_spectre_bhb_fw_mitigation()) { + /* + * Ensure KVM uses one of the spectre bp_hardening + * vectors. The indirect vector doesn't include the EL3 + * call, so needs upgrading to + * HYP_VECTOR_SPECTRE_INDIRECT. + */ + if (!data->slot || data->slot =3D=3D HYP_VECTOR_INDIRECT) + data->slot +=3D 1; + + this_cpu_set_vectors(EL1_VECTOR_BHB_FW); + + /* + * The WA3 call in the vectors supersedes the WA1 call + * made during context-switch. Uninstall any firmware + * bp_hardening callback. + */ + cpu_cb =3D spectre_v2_get_sw_mitigation_cb(); + if (__this_cpu_read(bp_hardening_data.fn) !=3D cpu_cb) + __this_cpu_write(bp_hardening_data.fn, NULL); + + state =3D SPECTRE_MITIGATED; + set_bit(BHB_FW, &system_bhb_mitigations); } =20 update_mitigation_state(&spectre_bhb_state, state); @@ -1101,7 +1103,6 @@ void noinstr spectre_bhb_patch_loop_iter(struct alt_i= nstr *alt, { u8 rd; u32 insn; - u16 loop_count =3D spectre_bhb_loop_affected(SCOPE_SYSTEM); =20 BUG_ON(nr_inst !=3D 1); /* MOV -> MOV */ =20 @@ -1110,7 +1111,7 @@ void noinstr spectre_bhb_patch_loop_iter(struct alt_i= nstr *alt, =20 insn =3D le32_to_cpu(*origptr); rd =3D aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, insn); - insn =3D aarch64_insn_gen_movewide(rd, loop_count, 0, + insn =3D aarch64_insn_gen_movewide(rd, max_bhb_k, 0, AARCH64_INSN_VARIANT_64BIT, AARCH64_INSN_MOVEWIDE_ZERO); *updptr++ =3D cpu_to_le32(insn); --=20 2.47.1.613.gc27f4b7a9f-goog From nobody Wed Dec 17 16:18:02 2025 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FD7B1F7572 for ; Tue, 7 Jan 2025 20:08:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736280499; cv=none; b=QvMf+NidMd1p0k0Wu9Qu5xYIjmUGgddfNUphxt/pdLTPBfMmBPMAJ+EiBdAuvBFOmS9oJw5eJCGgDZ9zWsKRPWQ4bHOYw4BJgKqF0FiVtQn41cT7yGhC5pK3rALf5EFjUAoa8aVCfW39SzeSdpPg6xIFgKlo0NMqxR9X94/6Phs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736280499; c=relaxed/simple; bh=iXSbvGK/GRKHVLZGDgeu68FgJ3g7CX4QZMvsuVny4LY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Z48futB3X5zJyTTml454DNmScm9wt9Sfnp+aVjPfCQuVgiYxcGWmoFCRYdRpSBM/ADGGOZ8ZutzLfkT7ZW5XbrY1c2SU4F05GtdgSWxtxjgOAwCCKxr61G5mcaHjwixRpiBfa01Zo36UUSNMZy1j1HSRxUDJcKED+wxgboix/EU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=BMnr8HJf; arc=none smtp.client-ip=209.85.214.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="BMnr8HJf" Received: by mail-pl1-f173.google.com with SMTP id d9443c01a7336-216395e151bso2081525ad.0 for ; Tue, 07 Jan 2025 12:08:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1736280494; x=1736885294; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B7JIcKoOn+aj6A6FGmZdKgBjeiVX3ZBuDhppF1K0+s8=; b=BMnr8HJf1jqrZaYD7eZY9Q2pEFXjZ8d31+ELyOgj4QfxO8LId0Pyc1QxNwR2HZgeGJ 1aPZzMLb57M4eqIgrvT/qduiZiW0KmiHz0l82GgQ6l+KX2bHlL7Udlujk12Kt2ZAtbNA SAsQ8Q8V3QvqfKIuKcHkjaRm8kky+ffL4Tyhs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736280494; x=1736885294; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B7JIcKoOn+aj6A6FGmZdKgBjeiVX3ZBuDhppF1K0+s8=; b=o0SLXcF/mEwkrUFnvRBhfQTNe/Oy1Sn+Vr3tbqFWsamaBL5adQxGGYjSYSaED5Erem PDOP0NwTWflwMJ0DkUiVQExx4YbNNZLSh6nwgy2wf6plx39BLjHEVPviaslM1qtABYFJ IDESlqjw0UFleZOxBXmRbAIPnk7i7xi0LuXpiwhIXh6o2psOzvNu5PyaeRSx4Foc3rpt wPF/3vi6AvsDYrqGKUytu465+wKJvFhUmN2CCgMteLPx+PXaH5LpSZmF4KajWk2pByRs qpoLNNiQC+R6nq/LAlW+sRQ8AznLRAOvpiVrlOL4FnDiihMODq5sUE8vXhZysP/EP8R2 69RA== X-Forwarded-Encrypted: i=1; AJvYcCUPwicnBueyPCN94w0M/h2kA2TcR8YmNKdJkvZ19qHzqk9lTx+oAWrxTQbr76UHe6hrEDtfWSSkSRNf3V8=@vger.kernel.org X-Gm-Message-State: AOJu0YyGONHZ9JZjx8HOkR9i2X/k836q2TgweRAZUEe083FbSpjsMlps o5Jk/ZfuWNv+IokHm8UstcpcjgmR1EaDLfq3rB9GCmImzDWy5M//BY4bq6MYIA== X-Gm-Gg: ASbGnct4Wx3OcLZJI9Jfimdy8fCgbOzleZxbgTTHKwUl9P2Y1xgN60+t9TzifNL30Uv 2rrm87tMmwavMHtYzCY3so2NGBwI8T3jJsSgJ0/8TpQUzY5IVQr8CecW/AbMhQU5x3A5LrGghsH AAve0qKubdBKh251R5vKSGGmI3vZeHaOL8QDY9L9XW0gsXlxCAYaTTbrpfHLIZY3fgQx2uivr7R BDbE1zC9OOcE1mxRifRL3jYJ+4wWIhVFFIftEyK4BK4qU/fPf/dx+f+WxJpkJf+pi7nb9MzFoJX X-Google-Smtp-Source: AGHT+IFYwu/b5vkXAi4S+EzyiEJNxnfulDMZqRNb7srUjlr5I3jIs0W0BPEczm+Ttsn4js6vyxWAkQ== X-Received: by 2002:a17:903:41c6:b0:215:758c:52e8 with SMTP id d9443c01a7336-21a83c148abmr5723375ad.12.1736280494447; Tue, 07 Jan 2025 12:08:14 -0800 (PST) Received: from dianders.sjc.corp.google.com ([2620:15c:9d:2:2961:4bbc:5703:5820]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc962d47sm314263425ad.55.2025.01.07.12.08.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jan 2025 12:08:13 -0800 (PST) From: Douglas Anderson To: Catalin Marinas , Will Deacon , Mark Rutland Cc: Roxana Bradescu , Julius Werner , bjorn.andersson@oss.qualcomm.com, Trilok Soni , linux-arm-msm@vger.kernel.org, Florian Fainelli , linux-arm-kernel@lists.infradead.org, Jeffrey Hugo , Scott Bauer , Douglas Anderson , stable@vger.kernel.org, James Morse , linux-kernel@vger.kernel.org Subject: [PATCH v4 3/5] arm64: errata: Add KRYO 2XX/3XX/4XX silver cores to Spectre BHB safe list Date: Tue, 7 Jan 2025 12:06:00 -0800 Message-ID: <20250107120555.v4.3.Iab8dbfb5c9b1e143e7a29f410bce5f9525a0ba32@changeid> X-Mailer: git-send-email 2.47.1.613.gc27f4b7a9f-goog In-Reply-To: <20250107200715.422172-1-dianders@chromium.org> References: <20250107200715.422172-1-dianders@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Qualcomm has confirmed that, much like Cortex A53 and A55, KRYO 2XX/3XX/4XX silver cores are unaffected by Spectre BHB. Add them to the safe list. Fixes: 558c303c9734 ("arm64: Mitigate spectre style branch history side cha= nnels") Cc: stable@vger.kernel.org Cc: Scott Bauer Signed-off-by: Douglas Anderson Acked-by: Trilok Soni --- Changes in v4: - Re-added KRYO 2XX/3XX/4XX silver patch after Qualcomm confirmed. Changes in v3: - Removed KRYO 2XX/3XX/4XX silver patch. Changes in v2: - New arch/arm64/kernel/proton-pack.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pac= k.c index 17aa836fe46d..89405be53d8f 100644 --- a/arch/arm64/kernel/proton-pack.c +++ b/arch/arm64/kernel/proton-pack.c @@ -854,6 +854,9 @@ static bool is_spectre_bhb_safe(int scope) MIDR_ALL_VERSIONS(MIDR_CORTEX_A510), MIDR_ALL_VERSIONS(MIDR_CORTEX_A520), MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), + MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), + MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), + MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), {}, }; static bool all_safe =3D true; --=20 2.47.1.613.gc27f4b7a9f-goog From nobody Wed Dec 17 16:18:02 2025 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0F201F76C1 for ; Tue, 7 Jan 2025 20:08:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736280502; cv=none; b=OaNkvYjS5bG+18WUYrwyBZlHapR0d7NZiZQnPvrKtx5dddlsAhMXA/LJXopcXWGPEZJnX2QPYdQH1Evvt7+Fpb72z0+XNr8mO30PcoQxK3BVRj/G0KopT6UcavNUrYFC1EUB6Rx1dLBKzS9Wkg5KYn/77LIL6C3gCSjV7kzvtPM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736280502; c=relaxed/simple; bh=s20fIlw9p2A8MPpe7e1vf1OBRFsKifSYci/GqL1Eyhc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZGBZ2XGGFyBVW+PEfVKiORqRxRldQAOB+ZVSfjTryt59mi6pPB1+Zp/e8b6CyNvikmwrAz6YgbE0YpjW6KpEgBMWkza8iduZMk/951Lxid3f/mmBxxq8qBQbn9yhzowoxjqpZdvfJHo1gwo5ZxECy9+b3SivAtLbKHAuMSKDeUA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=ApAeMSWM; arc=none smtp.client-ip=209.85.214.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="ApAeMSWM" Received: by mail-pl1-f175.google.com with SMTP id d9443c01a7336-2167141dfa1so2658865ad.1 for ; Tue, 07 Jan 2025 12:08:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1736280497; x=1736885297; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+J3uEvrodRrvpIjWWGDgko7jtoYydXF7C2qPRbL5eTY=; b=ApAeMSWM6XnlVDKRWubk9k4yx2jI6/PrZXI79PUb4hYY9C9OfuIicjjZhmHCv+Zq+g Ixwdh56bkSDXgXhx7PTx2YP4W6M0GotkvP2w9c2aWgVvLjidPsPVqyF0STewevwyKZWo ZieDni9/yxDwrtkqCMvM+PVMo2sSQG3odyRC0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736280497; x=1736885297; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+J3uEvrodRrvpIjWWGDgko7jtoYydXF7C2qPRbL5eTY=; b=YPZnPfIyDTJV4v8xHQIUIESu1DVm6sf//g9y4GmU+G3JHYSPXEdcJ8FrylyXUEmU+Z yGXoD1TgasMJnC0ou40uXTcZLb9A/DkPIYI6pnj5QM0MV0h9oU7ANqmsHJm5RCF1p2xi o3UA13/nYzNHntWzhVt4fEHcts57k8wBtK04IiMGX2mlJQzCSivd+q2zhjV++Mhgpqwf coJmAqSUSz0WfLdGgEBfAKb86NS2NHPP6P9wXeb0k1P1+Mj23CI8TCLLSqdbAYqTDu+5 Z1dsn4h12nUX8LMyPCF58yLoqsXlqXUJDCwOS5YlyYHMqRGswAigJYY5x41kWI3Dlu5r /gfQ== X-Forwarded-Encrypted: i=1; AJvYcCVzZoe9Ow/P/iMg/dnfO5fFYnT5GwjWcT7QhjGLVssb4aApO5539DRssSJ5cPc0rdojJPHclJNPm8UGos4=@vger.kernel.org X-Gm-Message-State: AOJu0YxZYN8Bq+LMcoFQDO90InKbr0aixuPih0Uxf8QeoFR7FUzbdo0M 3dhyxRretbmUmQ4//SJTT4Fp9Xqp0x6m//5oLWhz2DiXoDhLldUAxCohniVTqw== X-Gm-Gg: ASbGnctZOcH7zmQP5cPa4MpMkoIf2rTqaFFjXSc8CaBascZfv363oEEAuAKX70fbrA+ MkSP6eaF/Kp0MpGNPGjz4Xo8GnquuWVyoKdqcEB77yzhc5jAis9e0/ZelGmAwHFcKXDKIjQy9c1 znXKLx77tYtAgYHAL3j5xIybdHJoI5WM8zdMoc4HFa5JKSM0te/1YnlrpQzuc8IaPYM/yGnAIvl xizjrpxtd/ZApYMnL3f4hxFqHjEGx4F8HXHbycFlF8zJRp2MiqtUGXT5GISeyTgNyjtA3OivPn6 X-Google-Smtp-Source: AGHT+IERsInGKvMTJwDEekT7zUQ/SqNr1OWxECv7WnReZ50o5l0ZIy479qmOPxldyGbLGh45fTS6jg== X-Received: by 2002:a17:902:da85:b0:216:4676:dfb5 with SMTP id d9443c01a7336-21a83c721c1mr6200665ad.21.1736280496985; Tue, 07 Jan 2025 12:08:16 -0800 (PST) Received: from dianders.sjc.corp.google.com ([2620:15c:9d:2:2961:4bbc:5703:5820]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc962d47sm314263425ad.55.2025.01.07.12.08.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jan 2025 12:08:16 -0800 (PST) From: Douglas Anderson To: Catalin Marinas , Will Deacon , Mark Rutland Cc: Roxana Bradescu , Julius Werner , bjorn.andersson@oss.qualcomm.com, Trilok Soni , linux-arm-msm@vger.kernel.org, Florian Fainelli , linux-arm-kernel@lists.infradead.org, Jeffrey Hugo , Scott Bauer , Douglas Anderson , stable@vger.kernel.org, Anshuman Khandual , Besar Wicaksono , D Scott Phillips , Easwar Hariharan , Oliver Upton , linux-kernel@vger.kernel.org Subject: [PATCH v4 4/5] arm64: cputype: Add MIDR_CORTEX_A76AE Date: Tue, 7 Jan 2025 12:06:01 -0800 Message-ID: <20250107120555.v4.4.I151f3b7ee323bcc3082179b8c60c3cd03308aa94@changeid> X-Mailer: git-send-email 2.47.1.613.gc27f4b7a9f-goog In-Reply-To: <20250107200715.422172-1-dianders@chromium.org> References: <20250107200715.422172-1-dianders@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From the TRM, MIDR_CORTEX_A76AE has a partnum of 0xDOE and an implementor of 0x41 (ARM). Add the values. Cc: stable@vger.kernel.org # dependency of the next fix in the series Signed-off-by: Douglas Anderson --- (no changes since v3) Changes in v3: - New arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cput= ype.h index 488f8e751349..a345628fce51 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -75,6 +75,7 @@ #define ARM_CPU_PART_CORTEX_A76 0xD0B #define ARM_CPU_PART_NEOVERSE_N1 0xD0C #define ARM_CPU_PART_CORTEX_A77 0xD0D +#define ARM_CPU_PART_CORTEX_A76AE 0xD0E #define ARM_CPU_PART_NEOVERSE_V1 0xD40 #define ARM_CPU_PART_CORTEX_A78 0xD41 #define ARM_CPU_PART_CORTEX_A78AE 0xD42 @@ -158,6 +159,7 @@ #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTE= X_A76) #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOV= ERSE_N1) #define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTE= X_A77) +#define MIDR_CORTEX_A76AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_COR= TEX_A76AE) #define MIDR_NEOVERSE_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOV= ERSE_V1) #define MIDR_CORTEX_A78 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTE= X_A78) #define MIDR_CORTEX_A78AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_COR= TEX_A78AE) --=20 2.47.1.613.gc27f4b7a9f-goog From nobody Wed Dec 17 16:18:02 2025 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B20D1F76D6 for ; Tue, 7 Jan 2025 20:08:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736280504; cv=none; b=gHpTuL5ocj20AEuPX6Xe+qmUSr7F60eQZCYgKCdQ5xZOLhis5sJ8s4rOBMYt3IK7k/fOXhfQUcdzL5TOKAJ/+P6wkukUpFzoceGLuqnT7jsSbFdCe9dWjjgS5jsu5HZ7K33cdC1RqnHat03UdvoA6p46hCa97UqdNIJzxaJtZiI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736280504; c=relaxed/simple; bh=Duq+INKIqNPUgvYTHZsJkbkyGq8prfurW6VmwQI5pbU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=q6pCt9UgJ40SiN893MEcQIwhF8VlcClYikNgQhgza29TcDMciBCX7Di1Jd9JNL8xWuY/B7flqqzv3AcJVIUN+X9hnpFkosOrsWLGckclciAyEW8zdEsSXshom+Jyn9lJCFZTDc5QauYJVxn2JhQtJoIt/gvyej1LYB5kGIzf/OY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=PgCPJ6l+; arc=none smtp.client-ip=209.85.214.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="PgCPJ6l+" Received: by mail-pl1-f171.google.com with SMTP id d9443c01a7336-21a7ed0155cso16138865ad.3 for ; Tue, 07 Jan 2025 12:08:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1736280499; x=1736885299; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OfHdG1ANNWPpZE2kjiBnSExD56hP6zWfFTzaWahyQ5I=; b=PgCPJ6l+mNt/l80HE6BzyNgX5kWGIe/m4WTXfKM8m5wD2+39y3c61K4xoE0zVtp1Pv kUsAIwZWBmVYy1/u9FsCzjpoGtNN6bJ8/WceueyFjrC5I8w8bTDxfoEvkWcmVK7CBcLc Wsxsi3arNIqeeKatGBHHXfyQk429zXACrhRpQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736280499; x=1736885299; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OfHdG1ANNWPpZE2kjiBnSExD56hP6zWfFTzaWahyQ5I=; b=tlAtXta3yIg8wpOJEFuURwk1791IuAWtRNvoSl6XlIvXNU4Bu5aLF3m90NY+NU773C 9+EN9bLHPdD7yTN/GzKbj6tIQL/fNDRfkhY9MUb9FpfRWjMVfgRVOQYf1kv1X5asuY1s S+vxIyTrOx2zLrlGjm3uWI9vpA042AFudqmFt39W9EojdcfXul/5dDwfsx+OJWckGO6W WMjwMU7w10o0nnis7yrA9W7ac2ZD9z/OTsbyY1B4rwuMMBLbm1OzrAkLRgygBtnXjt1p NoDxQm3/4N6lfZrgCazThfCBS2/gvcqgTleTZGKevzDTLNJqUTgy/tdFWlLZGobhOJjX aSug== X-Forwarded-Encrypted: i=1; AJvYcCWmnGn+bSQjG/n4THY4hpRpMgnwrfzLYJ3F5kJejcM4RDnglNM8iB2iLMfGaNDrM6qw+jyKmwveIn5cjGg=@vger.kernel.org X-Gm-Message-State: AOJu0YzQ2glfY3FbcyhfbdFHxdRijZuIDAg6nL2L/bvHoeyzi0CuIAYx hVoEnT5F+RMPEoje2vk9Xt4GZsANroRufYJ/RTL/QwR7bkJMt+uUubOBw9+HSQ== X-Gm-Gg: ASbGncvwbh1UGtk6gmb2+ZjjDUnUoZdOy1KR3BmMz8Ks/Jzz1N20CDIR9+t6fwV2fe6 RiZL2LgqQIWu3V4SJLrOJzxKaB1eei2n27AdiVXd4TBDXEUwfGaNrwUqV3nkyoutTqOvnFb2Ekh Xv2aY3Hh1IpWDX746oRBgjgb22fZ5UZkeGV8GZltdy9c0NUBnH/GBkDjARETuEEC2+5C2ffI4kA Qzyb2YvwvvX2hZmTjk5r0pp9lp0m1p5dtxSoD3myo39HT9ScTEx9rFdvO4ABJTm8mNtZiWZFLiZ X-Google-Smtp-Source: AGHT+IFu7otqKCCIAbXozs9Yi25BzurouHYPRUn+yFnfSXfUKFQHp3WyFH7S4/kldp390+NNufFNOg== X-Received: by 2002:a17:902:ccc2:b0:216:4165:c05e with SMTP id d9443c01a7336-21a83f67982mr5749945ad.24.1736280499600; Tue, 07 Jan 2025 12:08:19 -0800 (PST) Received: from dianders.sjc.corp.google.com ([2620:15c:9d:2:2961:4bbc:5703:5820]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc962d47sm314263425ad.55.2025.01.07.12.08.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jan 2025 12:08:18 -0800 (PST) From: Douglas Anderson To: Catalin Marinas , Will Deacon , Mark Rutland Cc: Roxana Bradescu , Julius Werner , bjorn.andersson@oss.qualcomm.com, Trilok Soni , linux-arm-msm@vger.kernel.org, Florian Fainelli , linux-arm-kernel@lists.infradead.org, Jeffrey Hugo , Scott Bauer , Douglas Anderson , stable@vger.kernel.org, James Morse , linux-kernel@vger.kernel.org Subject: [PATCH v4 5/5] arm64: errata: Add newer ARM cores to the spectre_bhb_loop_affected() lists Date: Tue, 7 Jan 2025 12:06:02 -0800 Message-ID: <20250107120555.v4.5.I4a9a527e03f663040721c5401c41de587d015c82@changeid> X-Mailer: git-send-email 2.47.1.613.gc27f4b7a9f-goog In-Reply-To: <20250107200715.422172-1-dianders@chromium.org> References: <20250107200715.422172-1-dianders@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When comparing to the ARM list [1], it appears that several ARM cores were missing from the lists in spectre_bhb_loop_affected(). Add them. NOTE: for some of these cores it may not matter since other ways of clearing the BHB may be used (like the CLRBHB instruction or ECBHB), but it still seems good to have all the info from ARM's whitepaper included. [1] https://developer.arm.com/Arm%20Security%20Center/Spectre-BHB Fixes: 558c303c9734 ("arm64: Mitigate spectre style branch history side cha= nnels") Cc: stable@vger.kernel.org Signed-off-by: Douglas Anderson Reviewed-by: James Morse --- (no changes since v3) Changes in v3: - New arch/arm64/kernel/proton-pack.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pac= k.c index 89405be53d8f..0f51fd10b4b0 100644 --- a/arch/arm64/kernel/proton-pack.c +++ b/arch/arm64/kernel/proton-pack.c @@ -876,6 +876,14 @@ static u8 spectre_bhb_loop_affected(void) { u8 k =3D 0; =20 + static const struct midr_range spectre_bhb_k132_list[] =3D { + MIDR_ALL_VERSIONS(MIDR_CORTEX_X3), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), + }; + static const struct midr_range spectre_bhb_k38_list[] =3D { + MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A720), + }; static const struct midr_range spectre_bhb_k32_list[] =3D { MIDR_ALL_VERSIONS(MIDR_CORTEX_A78), MIDR_ALL_VERSIONS(MIDR_CORTEX_A78AE), @@ -889,6 +897,7 @@ static u8 spectre_bhb_loop_affected(void) }; static const struct midr_range spectre_bhb_k24_list[] =3D { MIDR_ALL_VERSIONS(MIDR_CORTEX_A76), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A76AE), MIDR_ALL_VERSIONS(MIDR_CORTEX_A77), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_GOLD), @@ -904,7 +913,11 @@ static u8 spectre_bhb_loop_affected(void) {}, }; =20 - if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k32_list)) + if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k132_list)) + k =3D 132; + else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k38_list)) + k =3D 38; + else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k32_list)) k =3D 32; else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k24_list)) k =3D 24; --=20 2.47.1.613.gc27f4b7a9f-goog