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client-ip=172.205.89.229; helo=nebula.arm.com; Received: from nebula.arm.com (172.205.89.229) by AM3PEPF0000A78D.mail.protection.outlook.com (10.167.16.116) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8335.7 via Frontend Transport; Tue, 7 Jan 2025 17:28:08 +0000 Received: from AZ-NEU-EX02.Emea.Arm.com (10.251.26.5) by AZ-NEU-EX05.Arm.com (10.240.25.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 7 Jan 2025 17:28:07 +0000 Received: from AZ-NEU-EX06.Arm.com (10.240.25.134) by AZ-NEU-EX02.Emea.Arm.com (10.251.26.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 7 Jan 2025 17:28:06 +0000 Received: from e121164.cambridge.arm.com (10.2.10.32) by mail.arm.com (10.240.25.134) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Tue, 7 Jan 2025 17:28:06 +0000 From: Florent Tomasin To: Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter CC: Florent Tomasin , , , Subject: [PATCH] drm/panthor: Fix invalid handling of AS_LOCKADDR Date: Tue, 7 Jan 2025 17:27:31 +0000 Message-ID: <20250107172732.87044-1-florent.tomasin@arm.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM3PEPF0000A78D:EE_|DB3PR08MB8964:EE_ X-MS-Office365-Filtering-Correlation-Id: 5333fa34-4513-4cfa-f8e3-08dd2f40a761 X-LD-Processed: f34e5979-57d9-4aaa-ad4d-b122a662184d,ExtAddr x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jan 2025 17:28:08.8637 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5333fa34-4513-4cfa-f8e3-08dd2f40a761 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[172.205.89.229];Helo=[nebula.arm.com] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF0000A78D.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR08MB8964 Content-Type: text/plain; charset="utf-8" Arm Mali GPUs require AS_LOCKADDR region to be 32KB aligned, and does not support a size greater than the one specified by the HW property: `GPU_MMU_FEATURES_VA_BITS()`. NOTES: - The size limitation is implementation defined. - Invalid alignment or size can result in an HW undefined behaviour. This patch modifies `lock_region()` to retrieve the maximum region size based on the HW property: `mmu_features`, and returns an error code if the requested size is not compliant with the HW limitation. In addition, the function will guaranty the region is always 32KB aligned. Signed-off-by: Florent Tomasin --- drivers/gpu/drm/panthor/panthor_mmu.c | 37 ++++++++++++++++++++------- 1 file changed, 28 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/panthor/panthor_mmu.c b/drivers/gpu/drm/pantho= r/panthor_mmu.c index c39e3eb1c15d..e834bc4d9a52 100644 --- a/drivers/gpu/drm/panthor/panthor_mmu.c +++ b/drivers/gpu/drm/panthor/panthor_mmu.c @@ -533,15 +533,20 @@ static int write_cmd(struct panthor_device *ptdev, u3= 2 as_nr, u32 cmd) return status; } =20 -static void lock_region(struct panthor_device *ptdev, u32 as_nr, - u64 region_start, u64 size) +static int lock_region(struct panthor_device *ptdev, u32 as_nr, + u64 region_start, u64 size) { + u32 va_bits =3D GPU_MMU_FEATURES_VA_BITS(ptdev->gpu_info.mmu_features); + u64 full_va_range =3D 1ull << va_bits; u8 region_width; u64 region; u64 region_end =3D region_start + size; =20 if (!size) - return; + return 0; + + if (drm_WARN_ON(&ptdev->base, region_end > full_va_range)) + return -EFAULT; =20 /* * The locked region is a naturally aligned power of 2 block encoded as @@ -552,7 +557,8 @@ static void lock_region(struct panthor_device *ptdev, u= 32 as_nr, * zeroed and ends with the bit (and subsequent bits) set to one. */ region_width =3D max(fls64(region_start ^ (region_end - 1)), - const_ilog2(AS_LOCK_REGION_MIN_SIZE)) - 1; + const_ilog2(AS_LOCK_REGION_MIN_SIZE)); + =20 /* * Mask off the low bits of region_start (which would be ignored by @@ -560,21 +566,25 @@ static void lock_region(struct panthor_device *ptdev,= u32 as_nr, */ region_start &=3D GENMASK_ULL(63, region_width); =20 - region =3D region_width | region_start; + region =3D (region_width - 1) | region_start; =20 /* Lock the region that needs to be updated */ gpu_write(ptdev, AS_LOCKADDR_LO(as_nr), lower_32_bits(region)); gpu_write(ptdev, AS_LOCKADDR_HI(as_nr), upper_32_bits(region)); write_cmd(ptdev, as_nr, AS_COMMAND_LOCK); + + return 0; } =20 static int mmu_hw_do_operation_locked(struct panthor_device *ptdev, int as= _nr, u64 iova, u64 size, u32 op) { + int ret =3D 0; + lockdep_assert_held(&ptdev->mmu->as.slots_lock); =20 if (as_nr < 0) - return 0; + return ret; =20 /* * If the AS number is greater than zero, then we can be sure @@ -583,7 +593,10 @@ static int mmu_hw_do_operation_locked(struct panthor_d= evice *ptdev, int as_nr, */ =20 if (op !=3D AS_COMMAND_UNLOCK) - lock_region(ptdev, as_nr, iova, size); + ret =3D lock_region(ptdev, as_nr, iova, size); + + if (ret) + return ret; =20 /* Run the MMU operation */ write_cmd(ptdev, as_nr, op); @@ -608,9 +621,12 @@ static int mmu_hw_do_operation(struct panthor_vm *vm, static int panthor_mmu_as_enable(struct panthor_device *ptdev, u32 as_nr, u64 transtab, u64 transcfg, u64 memattr) { + u32 va_bits =3D GPU_MMU_FEATURES_VA_BITS(ptdev->gpu_info.mmu_features); + u64 full_va_range =3D 1ull << va_bits; int ret; =20 - ret =3D mmu_hw_do_operation_locked(ptdev, as_nr, 0, ~0ULL, AS_COMMAND_FLU= SH_MEM); + ret =3D mmu_hw_do_operation_locked(ptdev, as_nr, 0, + full_va_range, AS_COMMAND_FLUSH_MEM); if (ret) return ret; =20 @@ -628,9 +644,12 @@ static int panthor_mmu_as_enable(struct panthor_device= *ptdev, u32 as_nr, =20 static int panthor_mmu_as_disable(struct panthor_device *ptdev, u32 as_nr) { + u32 va_bits =3D GPU_MMU_FEATURES_VA_BITS(ptdev->gpu_info.mmu_features); + u64 full_va_range =3D 1ull << va_bits; int ret; =20 - ret =3D mmu_hw_do_operation_locked(ptdev, as_nr, 0, ~0ULL, AS_COMMAND_FLU= SH_MEM); + ret =3D mmu_hw_do_operation_locked(ptdev, as_nr, 0, + full_va_range, AS_COMMAND_FLUSH_MEM); if (ret) return ret; =20 --=20 2.34.1