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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ5PEPF00000206.mail.protection.outlook.com (10.167.244.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8335.7 via Frontend Transport; Tue, 7 Jan 2025 14:41:16 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 7 Jan 2025 08:40:37 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 09/16] cxl/pci: Map CXL PCIe Upstream Switch Port RAS registers Date: Tue, 7 Jan 2025 08:38:45 -0600 Message-ID: <20250107143852.3692571-10-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250107143852.3692571-1-terry.bowman@amd.com> References: <20250107143852.3692571-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000206:EE_|DM4PR12MB9072:EE_ X-MS-Office365-Filtering-Correlation-Id: b644caf3-0dd0-4b6a-3ebf-08dd2f2957a4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|7416014|376014|1800799024|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jan 2025 14:41:16.5618 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b644caf3-0dd0-4b6a-3ebf-08dd2f2957a4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000206.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB9072 Content-Type: text/plain; charset="utf-8" Add logic to map CXL PCIe Upstream Switch Port (USP) RAS registers. Introduce 'struct cxl_regs' member into 'struct cxl_port' to cache a pointer to the CXL Upstream Port's mapped RAS registers. Also, introduce cxl_uport_init_ras_reporting() to perform the USP RAS register mapping. This is similar to the existing cxl_dport_init_ras_reporting() but for USP devices. The USP may have multiple downstream endpoints. Before mapping AER registers check if the registers are already mapped. Signed-off-by: Terry Bowman Reviewed-by: Gregory Price Reviewed-by: Ira Weiny --- drivers/cxl/core/pci.c | 15 +++++++++++++++ drivers/cxl/cxl.h | 4 ++++ drivers/cxl/mem.c | 8 ++++++++ 3 files changed, 27 insertions(+) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 1af2d0a14f5d..97e6a15bea88 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -773,6 +773,21 @@ static void cxl_disable_rch_root_ints(struct cxl_dport= *dport) writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); } =20 +void cxl_uport_init_ras_reporting(struct cxl_port *port) +{ + /* uport may have more than 1 downstream EP. Check if already mapped. */ + if (port->uport_regs.ras) + return; + + port->reg_map.host =3D &port->dev; + if (cxl_map_component_regs(&port->reg_map, &port->uport_regs, + BIT(CXL_CM_CAP_CAP_ID_RAS))) { + dev_err(&port->dev, "Failed to map RAS capability.\n"); + return; + } +} +EXPORT_SYMBOL_NS_GPL(cxl_uport_init_ras_reporting, "CXL"); + /** * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport * @dport: the cxl_dport that needs to be initialized diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 727429dfdaed..c51735fe75d6 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -601,6 +601,7 @@ struct cxl_dax_region { * @parent_dport: dport that points to this port in the parent * @decoder_ida: allocator for decoder ids * @reg_map: component and ras register mapping parameters + * @uport_regs: mapped component registers * @nr_dports: number of entries in @dports * @hdm_end: track last allocated HDM decoder instance for allocation orde= ring * @commit_end: cursor to track highest committed decoder for commit order= ing @@ -621,6 +622,7 @@ struct cxl_port { struct cxl_dport *parent_dport; struct ida decoder_ida; struct cxl_register_map reg_map; + struct cxl_component_regs uport_regs; int nr_dports; int hdm_end; int commit_end; @@ -773,8 +775,10 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_po= rt *port, =20 #ifdef CONFIG_PCIEAER_CXL void cxl_dport_init_ras_reporting(struct cxl_dport *dport); +void cxl_uport_init_ras_reporting(struct cxl_port *port); #else static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport) {= } +static inline void cxl_uport_init_ras_reporting(struct cxl_port *port) { } #endif =20 struct cxl_decoder *to_cxl_decoder(struct device *dev); diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index dd39f4565be2..97dbca765f4d 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -60,6 +60,7 @@ static bool dev_is_cxl_pci(struct device *dev, u32 pcie_t= ype) static void cxl_init_ep_ports_aer(struct cxl_ep *ep) { struct cxl_dport *dport =3D ep->dport; + struct cxl_port *port =3D ep->next; =20 if (dport) { struct device *dport_dev =3D dport->dport_dev; @@ -68,6 +69,13 @@ static void cxl_init_ep_ports_aer(struct cxl_ep *ep) dev_is_cxl_pci(dport_dev, PCI_EXP_TYPE_ROOT_PORT)) cxl_dport_init_ras_reporting(dport); } + + if (port) { + struct device *uport_dev =3D port->uport_dev; + + if (dev_is_cxl_pci(uport_dev, PCI_EXP_TYPE_UPSTREAM)) + cxl_uport_init_ras_reporting(port); + } } =20 static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *c= xlmd, --=20 2.34.1