From nobody Thu Dec 18 09:50:30 2025 Received: from mail-m49239.qiye.163.com (mail-m49239.qiye.163.com [45.254.49.239]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DB6F1EF0B5; Tue, 7 Jan 2025 13:32:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.239 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736256740; cv=none; b=m/pcOQwaSonYxvvDqQpwdw0qUC8IIaWTJ7d7UgUFwQ9Qsg247eKoUTFENn1pMdbcLLJK4VHKipf2TUiWvLhdIqgc4SEOhEYYZVUKO4JNMaaKZ2p8hjj41bOrXC06ZMRNMqlvU4rKeJsYeK8wPMJZEoOhwBA8ehAnq/oUNMIo0I8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736256740; c=relaxed/simple; bh=Nk1YL8gMJ4htzY7Kg2D0YJZLN+lat5BbUfEfF8VAgwo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Vgg1o10gohzhqG/JYt8YEd/f0KBPE2kt10T2W9D9dp408ovg6ZQxvH2Sc28Lwdo5pCWZwxXkaUuxZ+E1OvzRU3BwZGuMnDeo/em1JmiQGCkMHjsKQ35LOZkzc4BSCKo3Rnvc/5ISQIbF9rbcDdirqUOYIuzXrWTO6yWd8kQJP5M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=EP9w8k7x; arc=none smtp.client-ip=45.254.49.239 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="EP9w8k7x" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 7f3b5a8c; Tue, 7 Jan 2025 15:49:19 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Frank Wang , Kever Yang , devicetree@vger.kernel.org, Conor Dooley , Finley Xiao , Rob Herring , Liang Chen , Detlev Casanova , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 4/7] arm64: dts: rockchip: add usb related nodes for rk3576 Date: Tue, 7 Jan 2025 15:49:08 +0800 Message-Id: <20250107074911.550057-5-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250107074911.550057-1-kever.yang@rock-chips.com> References: <20250107074911.550057-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGklDGVZPHR8ZGE4fSUJMSkJWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCSE NVSktLVUpCS0tZBg++ X-HM-Tid: 0a943fbd53af03afkunm7f3b5a8c X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Mxg6ARw5PzIRTBNLSSgZSFEf HjkwCzdVSlVKTEhNSUhNSk1KSEtJVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFOTENPNwY+ DKIM-Signature: a=rsa-sha256; b=EP9w8k7x7u+ZZ7FvCoIG2SBRWd6tGh08CcLq1zbeJngl10HlphTo96rDMC1Snn2/2S5vE6t6TwQibUiBNm537InwzHEaGS3+DbQ6UfAcJnyEZ9LnfoR2JZKLFKS9Lkdh2lAd7ypIsPLzpBHU8Z9CZM7fQfkodFlNU85OcsEYgXU=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=UjWRwJmepX1/tP10Gtcn2jZFD8Z/yI8Z/tGocsPqklA=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" From: Frank Wang This adds USB and USB-PHY related nodes for RK3576 SoC. Signed-off-by: Frank Wang Signed-off-by: Kever Yang --- Changes in v4: None Changes in v3: None Changes in v2: None arch/arm64/boot/dts/rockchip/rk3576.dtsi | 133 +++++++++++++++++++++++ 1 file changed, 133 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts= /rockchip/rk3576.dtsi index 0486525fe596..b4f396421686 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -445,6 +445,58 @@ soc { #size-cells =3D <2>; ranges; =20 + usb_drd0_dwc3: usb@23000000 { + compatible =3D "rockchip,rk3576-dwc3", "snps,dwc3"; + reg =3D <0x0 0x23000000 0x0 0x400000>; + clocks =3D <&cru CLK_REF_USB3OTG0>, + <&cru CLK_SUSPEND_USB3OTG0>, + <&cru ACLK_USB3OTG0>; + clock-names =3D "ref_clk", "suspend_clk", "bus_clk"; + interrupts =3D ; + power-domains =3D <&power RK3576_PD_USB>; + resets =3D <&cru SRST_A_USB3OTG0>; + dr_mode =3D "otg"; + phys =3D <&u2phy0_otg>, <&usbdp_phy PHY_TYPE_USB3>; + phy-names =3D "usb2-phy", "usb3-phy"; + phy_type =3D "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + status =3D "disabled"; + }; + + usb_drd1_dwc3: usb@23400000 { + compatible =3D "rockchip,rk3576-dwc3", "snps,dwc3"; + reg =3D <0x0 0x23400000 0x0 0x400000>; + clocks =3D <&cru CLK_REF_USB3OTG1>, + <&cru CLK_SUSPEND_USB3OTG1>, + <&cru ACLK_USB3OTG1>; + clock-names =3D "ref_clk", "suspend_clk", "bus_clk"; + interrupts =3D ; + power-domains =3D <&power RK3576_PD_PHP>; + resets =3D <&cru SRST_A_USB3OTG1>; + dr_mode =3D "otg"; + phys =3D <&u2phy1_otg>, <&combphy1_psu PHY_TYPE_USB3>; + phy-names =3D "usb2-phy", "usb3-phy"; + phy_type =3D "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + dma-coherent; + status =3D "disabled"; + }; + sys_grf: syscon@2600a000 { compatible =3D "rockchip,rk3576-sys-grf", "syscon"; reg =3D <0x0 0x2600a000 0x0 0x2000>; @@ -515,6 +567,65 @@ usbdpphy_grf: syscon@2602c000 { reg =3D <0x0 0x2602c000 0x0 0x2000>; }; =20 + usb2phy_grf: syscon@2602e000 { + compatible =3D "rockchip,rk3576-usb2phy-grf", "syscon", "simple-mfd"; + reg =3D <0x0 0x2602e000 0x0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + u2phy0: usb2-phy@0 { + compatible =3D "rockchip,rk3576-usb2phy"; + reg =3D <0x0 0x10>; + resets =3D <&cru SRST_OTGPHY_0>, <&cru SRST_P_USBPHY_GRF_0>; + reset-names =3D "phy", "apb"; + clocks =3D <&cru CLK_PHY_REF_SRC>, + <&cru ACLK_MMU2>, + <&cru ACLK_SLV_MMU2>; + clock-names =3D "phyclk", "aclk", "aclk_slv"; + clock-output-names =3D "usb480m_phy0"; + #clock-cells =3D <0>; + status =3D "disabled"; + + u2phy0_otg: otg-port { + #phy-cells =3D <0>; + interrupts =3D , + , + ; + interrupt-names =3D "otg-bvalid", "otg-id", "linestate"; + status =3D "disabled"; + }; + }; + + u2phy1: usb2-phy@2000 { + compatible =3D "rockchip,rk3576-usb2phy"; + reg =3D <0x2000 0x10>; + resets =3D <&cru SRST_OTGPHY_1>, <&cru SRST_P_USBPHY_GRF_1>; + reset-names =3D "phy", "apb"; + clocks =3D <&cru CLK_PHY_REF_SRC>, + <&cru ACLK_MMU1>, + <&cru ACLK_SLV_MMU1>; + clock-names =3D "phyclk", "aclk", "aclk_slv"; + clock-output-names =3D "usb480m_phy1"; + #clock-cells =3D <0>; + status =3D "disabled"; + + u2phy1_otg: otg-port { + #phy-cells =3D <0>; + interrupts =3D , + , + ; + interrupt-names =3D "otg-bvalid", "otg-id", "linestate"; + status =3D "disabled"; + }; + }; + }; + + vo1_grf: syscon@26036000 { + compatible =3D "rockchip,rk3576-vo1-grf", "syscon"; + reg =3D <0x0 0x26036000 0x0 0x100>; + clocks =3D <&cru PCLK_VO1_ROOT>; + }; + sdgmac_grf: syscon@26038000 { compatible =3D "rockchip,rk3576-sdgmac-grf", "syscon"; reg =3D <0x0 0x26038000 0x0 0x1000>; @@ -1732,6 +1843,28 @@ combphy1_psu: phy@2b060000 { status =3D "disabled"; }; =20 + usbdp_phy: phy@2b010000 { + compatible =3D "rockchip,rk3576-usbdp-phy"; + reg =3D <0x0 0x2b010000 0x0 0x10000>; + #phy-cells =3D <1>; + clocks =3D <&cru CLK_PHY_REF_SRC >, + <&cru CLK_USBDP_COMBO_PHY_IMMORTAL>, + <&cru PCLK_USBDPPHY>, + <&u2phy0>; + clock-names =3D "refclk", "immortal", "pclk", "utmi"; + resets =3D <&cru SRST_USBDP_COMBO_PHY_INIT>, + <&cru SRST_USBDP_COMBO_PHY_CMN>, + <&cru SRST_USBDP_COMBO_PHY_LANE>, + <&cru SRST_USBDP_COMBO_PHY_PCS>, + <&cru SRST_P_USBDPPHY>; + reset-names =3D "init", "cmn", "lane", "pcs_apb", "pma_apb"; + rockchip,u2phy-grf =3D <&usb2phy_grf>; + rockchip,usb-grf =3D <&usb_grf>; + rockchip,usbdpphy-grf =3D <&usbdpphy_grf>; + rockchip,vo-grf =3D <&vo1_grf>; + status =3D "disabled"; + }; + sram: sram@3ff88000 { compatible =3D "mmio-sram"; reg =3D <0x0 0x3ff88000 0x0 0x78000>; --=20 2.25.1