From nobody Thu Dec 18 08:13:00 2025 Received: from mail-m32107.qiye.163.com (mail-m32107.qiye.163.com [220.197.32.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 540FA522A; Tue, 7 Jan 2025 07:49:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.107 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736236169; cv=none; b=gRq9qXPHDMkCZhwDETmd3rJi33PRPpyAYnlVhRAnPzfwjB4+ICeJiFQ0kj5gL7rrXkPN1NwAR07gT+r0BDqwxbYld3gjjfeIfYz4bxXRASvgp7SrA4J7oPGEqrP/XUTpU2C4oUHthED4+6Chtem6KLzIVn05fjE1C1VP99oADxI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736236169; c=relaxed/simple; bh=jpfIapPt8pLJpTwhvVJOSNnmsYukKBP2ivRxQVHMKCc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=C9UzT20c5FBcREYDMb7zsoAEEhc359oTPzSp+a8nddjPCd9Ere+/7EDcCM0q2qGeaG7kpxuxzAenD418hr72fqlIf/AiQhlOODOzLfUlnKj9QqSxCgYtk6j1x75VO+T2MGJjP6Hi7xD8Owsf0R31VEgVYG2pSZP5EECrFU7IeMI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=ae71aq9g; arc=none smtp.client-ip=220.197.32.107 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="ae71aq9g" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 7f3b5a76; Tue, 7 Jan 2025 15:49:15 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , devicetree@vger.kernel.org, Conor Dooley , Frank Wang , Rob Herring , Liang Chen , Detlev Casanova , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Yifeng Zhao , Elaine Zhang , linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 1/7] arm64: dts: rockchip: Add rk3576 naneng combphy nodes Date: Tue, 7 Jan 2025 15:49:05 +0800 Message-Id: <20250107074911.550057-2-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250107074911.550057-1-kever.yang@rock-chips.com> References: <20250107074911.550057-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGkMaH1ZDHUIYS0IZTxlOH0hWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCSE NVSktLVUpCS0tZBg++ X-HM-Tid: 0a943fbd41f503afkunm7f3b5a76 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6My46Lgw6FTILMRM3SSpCSE0q LR0aCgNVSlVKTEhNSUhNSk5NTE5DVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFJSktONwY+ DKIM-Signature: a=rsa-sha256; b=ae71aq9gsUG5V1a0Dln8Hh/L0LgV+IqS4/i+n/Awi05lflNiNJFB+42V4IWNstuoCRsbXwajWn41adwznm+7FggGxhrF/JfjGKpoLjzyEwCKkgM37REewsvwMfiRjIH9U2xWpB7qy3zeSOYZJ+eN0X4/P9xLnsTTlEymFn6cRI4=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=uSCqXXvyq7kaloFgBj+3piFhPo3zSlCSuA6539oXzdw=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" rk3576 has two naneng combo phys: - combophy0 is used for one of pcie and sata; - combophy1 is used for one of pcie, sata and usb3; Signed-off-by: Kever Yang --- Changes in v4: None Changes in v3: - Update the subject Changes in v2: - Update the clock and reset names to pass the DTB CHECK arch/arm64/boot/dts/rockchip/rk3576.dtsi | 36 ++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts= /rockchip/rk3576.dtsi index 436232ffe4d1..a147879da501 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1587,6 +1587,42 @@ uart11: serial@2afd0000 { status =3D "disabled"; }; =20 + combphy0_ps: phy@2b050000 { + compatible =3D "rockchip,rk3576-naneng-combphy"; + reg =3D <0x0 0x2b050000 0x0 0x100>; + #phy-cells =3D <1>; + clocks =3D <&cru CLK_REF_PCIE0_PHY>, + <&cru PCLK_PCIE2_COMBOPHY0>, + <&cru PCLK_PCIE0>; + clock-names =3D "ref", "apb", "pipe"; + assigned-clocks =3D <&cru CLK_REF_PCIE0_PHY>; + assigned-clock-rates =3D <100000000>; + resets =3D <&cru SRST_PCIE0_PIPE_PHY>, + <&cru SRST_P_PCIE2_COMBOPHY0>; + reset-names =3D "phy", "apb"; + rockchip,pipe-grf =3D <&php_grf>; + rockchip,pipe-phy-grf =3D <&pipe_phy0_grf>; + status =3D "disabled"; + }; + + combphy1_psu: phy@2b060000 { + compatible =3D "rockchip,rk3576-naneng-combphy"; + reg =3D <0x0 0x2b060000 0x0 0x100>; + #phy-cells =3D <1>; + clocks =3D <&cru CLK_REF_PCIE1_PHY>, + <&cru PCLK_PCIE2_COMBOPHY1>, + <&cru PCLK_PCIE1>; + clock-names =3D "ref", "apb", "pipe"; + assigned-clocks =3D <&cru CLK_REF_PCIE1_PHY>; + assigned-clock-rates =3D <100000000>; + resets =3D <&cru SRST_PCIE1_PIPE_PHY>, + <&cru SRST_P_PCIE2_COMBOPHY1>; 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Tue, 7 Jan 2025 15:49:16 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , Simon Xue , Conor Dooley , Rob Herring , Bjorn Helgaas , linux-pci@vger.kernel.org, =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , devicetree@vger.kernel.org, Lorenzo Pieralisi , Shawn Lin , Manivannan Sadhasivam , linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 2/7] dt-bindings: PCI: dw: rockchip: Add rk3576 support Date: Tue, 7 Jan 2025 15:49:06 +0800 Message-Id: <20250107074911.550057-3-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250107074911.550057-1-kever.yang@rock-chips.com> References: <20250107074911.550057-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGRgZT1YaS0geSRlPQ0wYGUNWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCSE NVSktLVUpCS0tZBg++ X-HM-Tid: 0a943fbd47fc03afkunm7f3b5a7a X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6OBg6Cyo6EzILORMoIi8zSAEU FS9PChxVSlVKTEhNSUhNSk5DSE1LVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFKQk1JNwY+ DKIM-Signature: a=rsa-sha256; b=ULXNgOJr/FibT+0J2+sVLlSdQbjM7qUhkAcAdPFN6pgx11Nwgw0mDiMRcnsruEBSf08bspsf4XIdJiPbdSl5L/G5UPQz65KsfBSvSn9wtJzLQtJVWlc5RD1jvxenI8pNlb8vHba6dG92JxPF445EFIROB7V76TSob50zOBL52+Q=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=QnjYnNQ2cd6uU6QMuLion5/AeCzvzi5/5NXyDr58wf4=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" rk3576 is using dwc controller, with msi interrupt directly to gic instead of to gic its, so - no its support is required and the 'msi-map' is not need anymore, - a new 'msi' interrupt is needed. Signed-off-by: Kever Yang --- Changes in v4: - Fix wrong indentation in dt_binding_check report by Rob Changes in v3: - Fix dtb check broken on rk3588 - Update commit message Changes in v2: - remove required 'msi-map' - add interrupt name 'msi' .../devicetree/bindings/pci/rockchip-dw-pcie-common.yaml | 4 +++- Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 4 +--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.= yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml index cc9adfc7611c..e4fcc2dff413 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml @@ -81,7 +81,9 @@ properties: - const: msg - const: legacy - const: err - - const: dma0 + - enum: + - msi + - dma0 - const: dma1 - const: dma2 - const: dma3 diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/= Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 550d8a684af3..9a464731fa4a 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -26,6 +26,7 @@ properties: - const: rockchip,rk3568-pcie - items: - enum: + - rockchip,rk3576-pcie - rockchip,rk3588-pcie - const: rockchip,rk3568-pcie =20 @@ -71,9 +72,6 @@ properties: =20 vpcie3v3-supply: true =20 -required: - - msi-map - unevaluatedProperties: false =20 examples: --=20 2.25.1 From nobody Thu Dec 18 08:13:00 2025 Received: from mail-m32124.qiye.163.com (mail-m32124.qiye.163.com [220.197.32.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31448149DF4; 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arc=none smtp.client-ip=220.197.32.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="AN+0coXP" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 7f3b5a82; Tue, 7 Jan 2025 15:49:18 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , devicetree@vger.kernel.org, Conor Dooley , Frank Wang , Rob Herring , Detlev Casanova , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Yifeng Zhao , linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 3/7] arm64: dts: rockchip: Add rk3576 pcie nodes Date: Tue, 7 Jan 2025 15:49:07 +0800 Message-Id: <20250107074911.550057-4-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250107074911.550057-1-kever.yang@rock-chips.com> References: <20250107074911.550057-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGUseS1ZISh1CH0JPSRhMHRpWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCSE NVSktLVUpCS0tZBg++ X-HM-Tid: 0a943fbd4e3e03afkunm7f3b5a82 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6NCI6Njo5NDIUNRMDFC8QSE4p PysKCxhVSlVKTEhNSUhNSk5CTE5OVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFPQ0JJNwY+ DKIM-Signature: a=rsa-sha256; b=AN+0coXPQCMvjo6nqPVJvY9tch6IlU1vE11PtoH6CGdD/RyXAhCf3SAg4Er5Ia+Gbkik+c9/DpM1iVrxk7oJWi/ZCX1+JoM8yVLMpD12cotqbbO0xeln/8AWuYrLb+BKhedaOcUJiUKdIwbWffHBAPdaOgj8tHlAy7PFdNrJbl4=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=g0EkZFypRAuFjGmD0cpX0E7wOFkSXom4w3Ap9DoRno8=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" rk3576 has two pcie controllers, both are pcie2x1 work with naneng-combphy. Signed-off-by: Kever Yang --- Changes in v4: None Changes in v3: - Update the subject Changes in v2: - Update clock and reset names and sequence to pass DTB check arch/arm64/boot/dts/rockchip/rk3576.dtsi | 109 +++++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts= /rockchip/rk3576.dtsi index a147879da501..0486525fe596 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1016,6 +1016,115 @@ qos_npu_m1ro: qos@27f22100 { reg =3D <0x0 0x27f22100 0x0 0x20>; }; =20 + pcie0: pcie@2a200000 { + compatible =3D "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x0 0xf>; + clocks =3D <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>, + <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>, + <&cru CLK_PCIE0_AUX>; + + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux"; + device_type =3D "pci"; + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "sys", "pmc", "msg", "legacy", "err", "msi"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; + linux,pci-domain =3D <0>; + num-ib-windows =3D <8>; + num-viewport =3D <8>; + num-ob-windows =3D <2>; + max-link-speed =3D <2>; + num-lanes =3D <1>; + phys =3D <&combphy0_ps PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + power-domains =3D <&power RK3576_PD_PHP>; + ranges =3D <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000 + 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000 + 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>; + reg =3D <0x0 0x22000000 0x0 0x00400000>, + <0x0 0x2a200000 0x0 0x00010000>, + <0x0 0x20000000 0x0 0x00100000>; + reg-names =3D "dbi", "apb", "config"; + resets =3D <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names =3D "pwr", "pipe"; + status =3D "disabled"; + + pcie0_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + }; + + pcie1: pcie@2a210000 { + compatible =3D "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x20 0x2f>; + clocks =3D <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>, + <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>, + <&cru CLK_PCIE1_AUX>; + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux"; + device_type =3D "pci"; + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "sys", "pmc", "msg", "legacy", "err", "msi"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; + linux,pci-domain =3D <0>; + num-ib-windows =3D <8>; + num-viewport =3D <8>; + num-ob-windows =3D <2>; + max-link-speed =3D <2>; + num-lanes =3D <1>; + phys =3D <&combphy1_psu PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + power-domains =3D <&power RK3576_PD_SUBPHP>; + ranges =3D <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000 + 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000 + 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>; + reg =3D <0x0 0x22400000 0x0 0x00400000>, + <0x0 0x2a210000 0x0 0x00010000>, + <0x0 0x21000000 0x0 0x00100000>; + reg-names =3D "dbi", "apb", "config"; + resets =3D <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; + reset-names =3D "pwr", "pipe"; + status =3D "disabled"; + + pcie1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + }; + gmac0: ethernet@2a220000 { compatible =3D "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; reg =3D <0x0 0x2a220000 0x0 0x10000>; --=20 2.25.1 From nobody Thu Dec 18 08:13:00 2025 Received: from mail-m49239.qiye.163.com (mail-m49239.qiye.163.com [45.254.49.239]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DB6F1EF0B5; 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arc=none smtp.client-ip=45.254.49.239 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="EP9w8k7x" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 7f3b5a8c; Tue, 7 Jan 2025 15:49:19 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Frank Wang , Kever Yang , devicetree@vger.kernel.org, Conor Dooley , Finley Xiao , Rob Herring , Liang Chen , Detlev Casanova , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 4/7] arm64: dts: rockchip: add usb related nodes for rk3576 Date: Tue, 7 Jan 2025 15:49:08 +0800 Message-Id: <20250107074911.550057-5-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250107074911.550057-1-kever.yang@rock-chips.com> References: <20250107074911.550057-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGklDGVZPHR8ZGE4fSUJMSkJWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCSE NVSktLVUpCS0tZBg++ X-HM-Tid: 0a943fbd53af03afkunm7f3b5a8c X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Mxg6ARw5PzIRTBNLSSgZSFEf HjkwCzdVSlVKTEhNSUhNSk1KSEtJVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFOTENPNwY+ DKIM-Signature: a=rsa-sha256; b=EP9w8k7x7u+ZZ7FvCoIG2SBRWd6tGh08CcLq1zbeJngl10HlphTo96rDMC1Snn2/2S5vE6t6TwQibUiBNm537InwzHEaGS3+DbQ6UfAcJnyEZ9LnfoR2JZKLFKS9Lkdh2lAd7ypIsPLzpBHU8Z9CZM7fQfkodFlNU85OcsEYgXU=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=UjWRwJmepX1/tP10Gtcn2jZFD8Z/yI8Z/tGocsPqklA=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" From: Frank Wang This adds USB and USB-PHY related nodes for RK3576 SoC. Signed-off-by: Frank Wang Signed-off-by: Kever Yang --- Changes in v4: None Changes in v3: None Changes in v2: None arch/arm64/boot/dts/rockchip/rk3576.dtsi | 133 +++++++++++++++++++++++ 1 file changed, 133 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts= /rockchip/rk3576.dtsi index 0486525fe596..b4f396421686 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -445,6 +445,58 @@ soc { #size-cells =3D <2>; ranges; =20 + usb_drd0_dwc3: usb@23000000 { + compatible =3D "rockchip,rk3576-dwc3", "snps,dwc3"; + reg =3D <0x0 0x23000000 0x0 0x400000>; + clocks =3D <&cru CLK_REF_USB3OTG0>, + <&cru CLK_SUSPEND_USB3OTG0>, + <&cru ACLK_USB3OTG0>; + clock-names =3D "ref_clk", "suspend_clk", "bus_clk"; + interrupts =3D ; + power-domains =3D <&power RK3576_PD_USB>; + resets =3D <&cru SRST_A_USB3OTG0>; + dr_mode =3D "otg"; + phys =3D <&u2phy0_otg>, <&usbdp_phy PHY_TYPE_USB3>; + phy-names =3D "usb2-phy", "usb3-phy"; + phy_type =3D "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + status =3D "disabled"; + }; + + usb_drd1_dwc3: usb@23400000 { + compatible =3D "rockchip,rk3576-dwc3", "snps,dwc3"; + reg =3D <0x0 0x23400000 0x0 0x400000>; + clocks =3D <&cru CLK_REF_USB3OTG1>, + <&cru CLK_SUSPEND_USB3OTG1>, + <&cru ACLK_USB3OTG1>; + clock-names =3D "ref_clk", "suspend_clk", "bus_clk"; + interrupts =3D ; + power-domains =3D <&power RK3576_PD_PHP>; + resets =3D <&cru SRST_A_USB3OTG1>; + dr_mode =3D "otg"; + phys =3D <&u2phy1_otg>, <&combphy1_psu PHY_TYPE_USB3>; + phy-names =3D "usb2-phy", "usb3-phy"; + phy_type =3D "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + dma-coherent; + status =3D "disabled"; + }; + sys_grf: syscon@2600a000 { compatible =3D "rockchip,rk3576-sys-grf", "syscon"; reg =3D <0x0 0x2600a000 0x0 0x2000>; @@ -515,6 +567,65 @@ usbdpphy_grf: syscon@2602c000 { reg =3D <0x0 0x2602c000 0x0 0x2000>; }; =20 + usb2phy_grf: syscon@2602e000 { + compatible =3D "rockchip,rk3576-usb2phy-grf", "syscon", "simple-mfd"; + reg =3D <0x0 0x2602e000 0x0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + u2phy0: usb2-phy@0 { + compatible =3D "rockchip,rk3576-usb2phy"; + reg =3D <0x0 0x10>; + resets =3D <&cru SRST_OTGPHY_0>, <&cru SRST_P_USBPHY_GRF_0>; + reset-names =3D "phy", "apb"; + clocks =3D <&cru CLK_PHY_REF_SRC>, + <&cru ACLK_MMU2>, + <&cru ACLK_SLV_MMU2>; + clock-names =3D "phyclk", "aclk", "aclk_slv"; + clock-output-names =3D "usb480m_phy0"; + #clock-cells =3D <0>; + status =3D "disabled"; + + u2phy0_otg: otg-port { + #phy-cells =3D <0>; + interrupts =3D , + , + ; + interrupt-names =3D "otg-bvalid", "otg-id", "linestate"; + status =3D "disabled"; + }; + }; + + u2phy1: usb2-phy@2000 { + compatible =3D "rockchip,rk3576-usb2phy"; + reg =3D <0x2000 0x10>; + resets =3D <&cru SRST_OTGPHY_1>, <&cru SRST_P_USBPHY_GRF_1>; + reset-names =3D "phy", "apb"; + clocks =3D <&cru CLK_PHY_REF_SRC>, + <&cru ACLK_MMU1>, + <&cru ACLK_SLV_MMU1>; + clock-names =3D "phyclk", "aclk", "aclk_slv"; + clock-output-names =3D "usb480m_phy1"; + #clock-cells =3D <0>; + status =3D "disabled"; + + u2phy1_otg: otg-port { + #phy-cells =3D <0>; + interrupts =3D , + , + ; + interrupt-names =3D "otg-bvalid", "otg-id", "linestate"; + status =3D "disabled"; + }; + }; + }; + + vo1_grf: syscon@26036000 { + compatible =3D "rockchip,rk3576-vo1-grf", "syscon"; + reg =3D <0x0 0x26036000 0x0 0x100>; + clocks =3D <&cru PCLK_VO1_ROOT>; + }; + sdgmac_grf: syscon@26038000 { compatible =3D "rockchip,rk3576-sdgmac-grf", "syscon"; reg =3D <0x0 0x26038000 0x0 0x1000>; @@ -1732,6 +1843,28 @@ combphy1_psu: phy@2b060000 { status =3D "disabled"; }; =20 + usbdp_phy: phy@2b010000 { + compatible =3D "rockchip,rk3576-usbdp-phy"; + reg =3D <0x0 0x2b010000 0x0 0x10000>; + #phy-cells =3D <1>; + clocks =3D <&cru CLK_PHY_REF_SRC >, + <&cru CLK_USBDP_COMBO_PHY_IMMORTAL>, + <&cru PCLK_USBDPPHY>, + <&u2phy0>; + clock-names =3D "refclk", "immortal", "pclk", "utmi"; + resets =3D <&cru SRST_USBDP_COMBO_PHY_INIT>, + <&cru SRST_USBDP_COMBO_PHY_CMN>, + <&cru SRST_USBDP_COMBO_PHY_LANE>, + <&cru SRST_USBDP_COMBO_PHY_PCS>, + <&cru SRST_P_USBDPPHY>; + reset-names =3D "init", "cmn", "lane", "pcs_apb", "pma_apb"; + rockchip,u2phy-grf =3D <&usb2phy_grf>; + rockchip,usb-grf =3D <&usb_grf>; + rockchip,usbdpphy-grf =3D <&usbdpphy_grf>; + rockchip,vo-grf =3D <&vo1_grf>; + status =3D "disabled"; + }; + sram: sram@3ff88000 { compatible =3D "mmio-sram"; reg =3D <0x0 0x3ff88000 0x0 0x78000>; --=20 2.25.1 From nobody Thu Dec 18 08:13:00 2025 Received: from mail-m127100.qiye.163.com (mail-m127100.qiye.163.com [115.236.127.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4A3E1DF740; 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arc=none smtp.client-ip=115.236.127.100 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="hYHrX78d" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 7f3b5a97; Tue, 7 Jan 2025 15:49:21 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , Conor Dooley , devicetree@vger.kernel.org, Conor Dooley , Chris Morgan , Rob Herring , Dragan Simic , Jonas Karlman , linux-kernel@vger.kernel.org, Tim Lunn , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 5/7] dt-bindings: arm: rockchip: Sort for boards not in correct order Date: Tue, 7 Jan 2025 15:49:09 +0800 Message-Id: <20250107074911.550057-6-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250107074911.550057-1-kever.yang@rock-chips.com> References: <20250107074911.550057-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGR1CTFZLTUIaSx0fGh8YS01WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a943fbd59ba03afkunm7f3b5a97 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6OE06Aio*FTIRAxM3SSo1SAEh Ti0aFD9VSlVKTEhNSUhNSk1JQ05LVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFISUpLNwY+ DKIM-Signature: a=rsa-sha256; b=hYHrX78dVT9Z2Cm3e9bxy0rM7H+FPJ5m+rpzZPbtOlTqP2WpeT33VTPzQ54M0yWDqdnMcm8NkR7gg99tTJNz0jIM9W039ZDiAP9EzNBTC5cVXJnAAff5oZVC3xhk9RsHSaEjPmM5sYnVPwuZr5vHADhsl0+SlUuDXkSfvh0zf7I=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=JdLym5gWP7Ggt3zKKLw5r/EC2/WqbZu0Dz4bqOTYEU0=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" The board entries should be sort in correct order by the description string. Signed-off-by: Kever Yang Acked-by: Conor Dooley --- Changes in v4: - Update the commit msg with sort rule per required by Krzysztof. Changes in v3: - sort for all the board entries instead of two rockchip boards which suggested by Diederik Changes in v2: - collect acked-by tag .../devicetree/bindings/arm/rockchip.yaml | 54 +++++++++---------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 753199a12923..01439d7bbde9 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -1006,6 +1006,16 @@ properties: - const: rockchip,rk3399-sapphire-excavator - const: rockchip,rk3399 =20 + - description: Rockchip RK3566 BOX Evaluation Demo board + items: + - const: rockchip,rk3566-box-demo + - const: rockchip,rk3566 + + - description: Rockchip RK3568 Evaluation board + items: + - const: rockchip,rk3568-evb1-v10 + - const: rockchip,rk3568 + - description: Rockchip RK3588 Evaluation board items: - const: rockchip,rk3588-evb1-v10 @@ -1026,6 +1036,23 @@ properties: - const: rockchip,rk3588-toybrick-x0 - const: rockchip,rk3588 =20 + - description: Sinovoip RK3308 Banana Pi P2 Pro + items: + - const: sinovoip,rk3308-bpi-p2pro + - const: rockchip,rk3308 + + - description: Sinovoip RK3568 Banana Pi R2 Pro + items: + - const: sinovoip,rk3568-bpi-r2pro + - const: rockchip,rk3568 + + - description: Sonoff iHost Smart Home Hub + items: + - const: itead,sonoff-ihost + - enum: + - rockchip,rv1126 + - rockchip,rv1109 + - description: Theobroma Systems PX30-uQ7 with Haikou baseboard items: - const: tsd,px30-ringneck-haikou @@ -1099,33 +1126,6 @@ properties: - const: zkmagic,a95x-z2 - const: rockchip,rk3318 =20 - - description: Rockchip RK3566 BOX Evaluation Demo board - items: - - const: rockchip,rk3566-box-demo - - const: rockchip,rk3566 - - - description: Rockchip RK3568 Evaluation board - items: - - const: rockchip,rk3568-evb1-v10 - - const: rockchip,rk3568 - - - description: Sinovoip RK3308 Banana Pi P2 Pro - items: - - const: sinovoip,rk3308-bpi-p2pro - - const: rockchip,rk3308 - - - description: Sinovoip RK3568 Banana Pi R2 Pro - items: - - const: sinovoip,rk3568-bpi-r2pro - - const: rockchip,rk3568 - - - description: Sonoff iHost Smart Home Hub - items: - - const: itead,sonoff-ihost - - enum: - - rockchip,rv1126 - - rockchip,rv1109 - additionalProperties: true =20 ... --=20 2.25.1 From nobody Thu Dec 18 08:13:00 2025 Received: from mail-m1973181.qiye.163.com (mail-m1973181.qiye.163.com [220.197.31.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CF991E0E1A; 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arc=none smtp.client-ip=220.197.31.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="U+5XNebA" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 7f3b5aa3; Tue, 7 Jan 2025 15:49:22 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , Conor Dooley , devicetree@vger.kernel.org, Conor Dooley , Chris Morgan , Rob Herring , Dragan Simic , Jonas Karlman , linux-kernel@vger.kernel.org, Tim Lunn , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 6/7] dt-bindings: arm: rockchip: Add rk3576 evb1 board Date: Tue, 7 Jan 2025 15:49:10 +0800 Message-Id: <20250107074911.550057-7-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250107074911.550057-1-kever.yang@rock-chips.com> References: <20250107074911.550057-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGRpJSlYaHkofSx4ZHksZSEpWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCS0 NVSktLVUpCWQY+ X-HM-Tid: 0a943fbd5fc503afkunm7f3b5aa3 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Ok06Sww4DjINLRMWFC8hSEod KD9PCSNVSlVKTEhNSUhNSk1PSUJLVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFKS09MNwY+ DKIM-Signature: a=rsa-sha256; b=U+5XNebAtpYBijCgr1z5KsGJKon9coo9B+Cnp/OdYciWqLPJpm4Xf5ssVgw5I0g1Unu3tx622I74+VYW1AkF8WFAmfft6dA9XkVTRaiOai4qJZYvC3ceKKHAFl7qPBbvA9ndLImuQmCUFaSrdEnCum2yN9BDt9e5ZJ9pV8/6Fk4=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=Lp/E3DMmxqFfKf7nr8y8xpC3WW8LriSrgQ6tS+xpEao=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add device tree documentation for rk3576-evb1-v10. Signed-off-by: Kever Yang Acked-by: Conor Dooley --- Changes in v4: None Changes in v3: None Changes in v2: - collect acked-by tag Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 01439d7bbde9..1bd1b609fcff 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -1016,6 +1016,11 @@ properties: - const: rockchip,rk3568-evb1-v10 - const: rockchip,rk3568 =20 + - description: Rockchip RK3576 Evaluation board + items: + - const: rockchip,rk3576-evb1-v10 + - const: rockchip,rk3576 + - description: Rockchip RK3588 Evaluation board items: - const: rockchip,rk3588-evb1-v10 --=20 2.25.1 From nobody Thu Dec 18 08:13:00 2025 Received: from mail-m155100.qiye.163.com (mail-m155100.qiye.163.com [101.71.155.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 870991DFE10; Tue, 7 Jan 2025 07:54:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=101.71.155.100 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736236482; cv=none; b=Em0DuBACGRs7mjDzuxO1BU5JzzUzbL2PrSqWQvNG/TFlcsIgh/pCBPT7pkmXMwyX9Dib4Qe4QTANXOfAhcD/rD1BaBGsx2C0bJnmw/u7jl13UiWv1jGMja+iS7QlBciKxbXBs4vFqgWT3+9Xo3DI0TzNABuVVsBdlWApOvupn/Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736236482; c=relaxed/simple; bh=d+xLjP+mX2AE3yfFU9amd0UnLip6nUmjYPjiiHHXg7E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YdSpAe9KPEf50sDCCc9v4QGBFBidIltInYqyVtK5z4WAQwP2zsfVJNDHrdd/cScL6cY6KOazVMnPojWtPuyc+U59db/k67ggj0Bf+mLZcjseJEyQhMwu69kyllQMWoBNeZ4XLLlC1oD+f6QQHO1lMoFl3P00OqUYJ/gJYUM6vnE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=ZAWv/PCR; arc=none smtp.client-ip=101.71.155.100 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="ZAWv/PCR" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 7f3b5aaf; Tue, 7 Jan 2025 15:49:24 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , Liang Chen , devicetree@vger.kernel.org, Conor Dooley , Chris Morgan , Alexey Charkov , Rob Herring , Dragan Simic , Detlev Casanova , FUKAUMI Naoki , Jonas Karlman , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, Michael Riesch , linux-kernel@vger.kernel.org, Andy Yan Subject: [PATCH v4 7/7] arm64: dts: rockchip: Add rk3576 evb1 board Date: Tue, 7 Jan 2025 15:49:11 +0800 Message-Id: <20250107074911.550057-8-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250107074911.550057-1-kever.yang@rock-chips.com> References: <20250107074911.550057-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGk9LS1ZCSRpNGUoeQk8aHx1WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCSE NVSktLVUpCS0tZBg++ X-HM-Tid: 0a943fbd657703afkunm7f3b5aaf X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Ohw6Txw5PjIINRM#SSgwSAEr SwoKCzJVSlVKTEhNSUhNSk1NSU1OVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFKQk5ITTcG DKIM-Signature: a=rsa-sha256; b=ZAWv/PCRim2PgK+dx/rSHg3SApLxfOnBGjP8Qne9EEsA0/IiDDazI4H9CCadDlvcon8XyLvhK4LpgrHUG8UStdzhwh7R845H/jG94kHkuNjh8RDWoHkjDLv6EZm4u7e6Az9DUxU3krbmYX7NpyPc73zCMCJCsPZzCAFr40aRI90=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=ZmcTmGenq+yC1GgKqwh3Ie0bubhNTJmzNbuDgHKikn0=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" RK3576 EVB1 board features: - Rockchip RK3576 - PMIC: RK806-2x2pcs+DiscretePower - RAM: LPDDR4/4x 2pcsx 32bit - ROM: eMMC5.1 + UFS - LAN x 2 - HDMI TX - SD card slot - PCIe2 slot Add support for pmic, eMMC, SD-card, ADC-KEY, PCIE and GMAC. NOTE: The board has a hardware mux design for - PCIe slot(pcie1) - USB3 host(usb_drd1_dwc3) and default state is switch to USB3. To enable PCIe slot: - hardware: Switch the mux to PCIe side; - dts: disable usb_drd1_dwc3 and enable pcie1; Signed-off-by: Liang Chen Signed-off-by: Kever Yang --- Changes in v4: None Changes in v3: - update some properties order Changes in v2: - Enable USB nodes arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3576-evb1-v10.dts | 722 ++++++++++++++++++ 2 files changed, 723 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 86cc418a2255..2e683d7eab58 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -129,6 +129,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-wolfvision-pf5.= dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-wolfvision-pf5-display-vz.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-wolfvision-pf5-io-expander.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3576-armsom-sige5.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3576-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-armsom-sige7.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-armsom-w3.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-coolpi-cm5-evb.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/= boot/dts/rockchip/rk3576-evb1-v10.dts new file mode 100644 index 000000000000..5e74027f1b83 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts @@ -0,0 +1,722 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "rk3576.dtsi" + +/ { + model =3D "Rockchip RK3576 EVB V10 Board"; + compatible =3D "rockchip,rk3576-evb1-v10", "rockchip,rk3576"; + + aliases { + ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; + }; + + chosen: chosen { + stdout-path =3D "serial0:1500000n8"; + }; + + adc_keys: adc-keys { + compatible =3D "adc-keys"; + io-channels =3D <&saradc 1>; + io-channel-names =3D "buttons"; + keyup-threshold-microvolt =3D <1800000>; + poll-interval =3D <100>; + + button-vol-up { + label =3D "volume up"; + linux,code =3D ; + press-threshold-microvolt =3D <17000>; + }; + + button-vol-down { + label =3D "volume down"; + linux,code =3D ; + press-threshold-microvolt =3D <417000>; + }; + + button-menu { + label =3D "menu"; + linux,code =3D ; + press-threshold-microvolt =3D <890000>; + }; + + button-back { + label =3D "back"; + linux,code =3D ; + press-threshold-microvolt =3D <1235000>; + }; + }; + + leds: leds { + compatible =3D "gpio-leds"; + work_led: led-0 { + gpios =3D <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + vcc_sys: regulator-vcc5v0-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc5v0_device: regulator-vcc5v0-device { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_device"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_2v0_pldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <2000000>; + regulator-max-microvolt =3D <2000000>; + vin-supply =3D <&vcc_sys>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_1v1_nldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + vin-supply =3D <&vcc_sys>; + }; + + vcc3v3_rtc_s5: regulator-vcc3v3-rtc-s5 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_rtc_s5"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc_sys>; + }; + + vcc_1v8_s0: regulator-vcc-1v8-s0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_1v8_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vcc_1v8_s3>; + }; + + vcc_3v3_s0: regulator-vcc-3v3-s0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_3v3_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc_3v3_s3>; + }; + + vcc_ufs_s0: regulator-vcc-ufs-s0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_ufs_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc_sys>; + }; + + vcc1v8_ufs_vccq2_s0: regulator-vcc1v8-ufs-vccq2-s0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc1v8_ufs_vccq2_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vcc_1v8_s3>; + }; + + vcc1v2_ufs_vccq_s0: regulator-vcc1v2-ufs-vccq-s0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc1v2_ufs_vccq_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + vin-supply =3D <&vcc_sys>; + }; + + vcc3v3_lcd_n: regulator-vcc3v3-lcd0-n { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio =3D <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&vcc_3v3_s0>; + }; + + vcc3v3_pcie0: regulator-vcc3v3-pcie0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_pcie1"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + enable-active-high; + gpios =3D <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + startup-delay-us =3D <5000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc5v0_host: regulator-vcc5v0-host { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&vcc5v0_device>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb_host_pwren>; + }; + + vbus5v0_typec: regulator-vbus5v0-typec { + compatible =3D "regulator-fixed"; + regulator-name =3D "vbus5v0_typec"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&vcc5v0_device>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb_otg0_pwren>; + }; +}; + +&cpu_l0 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_b0 { + cpu-supply =3D <&vdd_cpu_big_s0>; +}; + +&combphy1_psu { + status =3D "okay"; +}; + +&gmac0 { + clock_in_out =3D "output"; + phy-mode =3D "rgmii-rxid"; + phy-handle =3D <&rgmii_phy0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <ð0m0_miim + ð0m0_tx_bus2 + ð0m0_rx_bus2 + ð0m0_rgmii_clk + ð0m0_rgmii_bus + ðm0_clk0_25m_out>; + + snps,reset-gpio =3D <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us =3D <0 20000 100000>; + tx_delay =3D <0x21>; + status =3D "okay"; +}; + +&gmac1 { + clock_in_out =3D "output"; + + phy-handle =3D <&rgmii_phy1>; + phy-mode =3D "rgmii-rxid"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <ð1m0_miim + ð1m0_tx_bus2 + ð1m0_rx_bus2 + ð1m0_rgmii_clk + ð1m0_rgmii_bus + ðm0_clk1_25m_out>; + + snps,reset-gpio =3D <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us =3D <0 20000 100000>; + tx_delay =3D <0x20>; + status =3D "okay"; +}; + +&i2c1 { + status =3D "okay"; + + rk806: pmic@23 { + compatible =3D "rockchip,rk806"; + reg =3D <0x23>; + + interrupt-parent =3D <&gpio0>; + interrupts =3D <6 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + system-power-controller; + + + vcc1-supply =3D <&vcc_sys>; + vcc2-supply =3D <&vcc_sys>; + vcc3-supply =3D <&vcc_sys>; + vcc4-supply =3D <&vcc_sys>; + vcc5-supply =3D <&vcc_sys>; + vcc6-supply =3D <&vcc_sys>; + vcc7-supply =3D <&vcc_sys>; + vcc8-supply =3D <&vcc_sys>; + vcc9-supply =3D <&vcc_sys>; + vcc10-supply =3D <&vcc_sys>; + vcc11-supply =3D <&vcc_2v0_pldo_s3>; + vcc12-supply =3D <&vcc_sys>; + vcc13-supply =3D <&vcc_1v1_nldo_s3>; + vcc14-supply =3D <&vcc_1v1_nldo_s3>; + vcca-supply =3D <&vcc_sys>; + + gpio-controller; + #gpio-cells =3D <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun0"; + }; + + rk806_dvs1_slp: dvs1-slp-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun1"; + }; + + rk806_dvs1_pwrdn: dvs1-pwrdn-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun2"; + }; + + rk806_dvs1_rst: dvs1-rst-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun3"; + }; + + rk806_dvs2_slp: dvs2-slp-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun1"; + }; + + rk806_dvs2_pwrdn: dvs2-pwrdn-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun2"; + }; + + rk806_dvs2_rst: dvs2-rst-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun3"; + }; + + rk806_dvs2_dvs: dvs2-dvs-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun4"; + }; + + rk806_dvs2_gpio: dvs2-gpio-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun5"; + }; + + rk806_dvs3_slp: dvs3-slp-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun1"; + }; + + rk806_dvs3_pwrdn: dvs3-pwrdn-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun2"; + }; + + rk806_dvs3_rst: dvs3-rst-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun3"; + }; + + rk806_dvs3_dvs: dvs3-dvs-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun4"; + }; + + rk806_dvs3_gpio: dvs3-gpio-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun5"; + }; + + regulators { + vdd_cpu_big_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_cpu_big_s0"; + regulator-enable-ramp-delay =3D <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_npu_s0"; + regulator-enable-ramp-delay =3D <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vcc_3v3_s3: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vdd_gpu_s0: dcdc-reg5 { + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <900000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_gpu_s0"; + regulator-enable-ramp-delay =3D <400>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + vddq_ddr_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <800000>; + regulator-name =3D "vdd_logic_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1200000>; + regulator-name =3D "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo2_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca1v8_pldo2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-name =3D "vdda_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcca_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca1v8_pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdda_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v75_hdmi_s0: nldo-reg3 { + regulator-boot-on; + regulator-min-microvolt =3D <837500>; + regulator-max-microvolt =3D <837500>; + regulator-name =3D "vdda0v75_hdmi_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdda_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdda_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + clocks =3D <&cru REFCLKO25M_GMAC0_OUT>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + clocks =3D <&cru REFCLKO25M_GMAC1_OUT>; + }; +}; + +&pinctrl { + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins =3D <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg0_pwren: usb-otg0-pwren { + rockchip,pins =3D <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins =3D <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sdmmc { + bus-width =3D <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency =3D <200000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vqmmc-supply =3D <&vccio_sd_s0>; + status =3D "okay"; +}; + +&pcie1 { + reset-gpios =3D <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie0>; +}; + +&saradc { + vref-supply =3D <&vcca_1v8_s0>; + status =3D "okay"; +}; + +&u2phy0 { + status =3D "okay"; +}; + +&u2phy0_otg { + phy-supply =3D <&vbus5v0_typec>; + status =3D "okay"; +}; + +&u2phy1 { + status =3D "okay"; +}; + +&u2phy1_otg { + phy-supply =3D <&vcc5v0_host>; + status =3D "okay"; +}; + +&uart0 { + status =3D "okay"; +}; + +&usbdp_phy { + rockchip,dp-lane-mux =3D <2 3>; + status =3D "okay"; +}; + +&usb_drd0_dwc3 { + dr_mode =3D "host"; + status =3D "okay"; +}; + +&usb_drd1_dwc3 { + dr_mode =3D "host"; + status =3D "okay"; +}; --=20 2.25.1