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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc9f6967sm292479535ad.214.2025.01.06.07.49.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jan 2025 07:49:43 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= Subject: [PATCH 6/6] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG Date: Mon, 6 Jan 2025 16:48:43 +0100 Message-ID: <20250106154847.1100344-7-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250106154847.1100344-1-cleger@rivosinc.com> References: <20250106154847.1100344-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable SBI_FWFT_MISALIGNED_DELEG needs hedeleg to be modified to delegate misaligned load/store exceptions. Save and restore it during CPU load/put. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/kvm/vcpu.c | 3 +++ arch/riscv/kvm/vcpu_sbi_fwft.c | 39 ++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 3420a4a62c94..bb6f788d46f5 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -641,6 +641,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) { void *nsh; struct kvm_vcpu_csr *csr =3D &vcpu->arch.guest_csr; + struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; =20 vcpu->cpu =3D -1; =20 @@ -666,6 +667,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) csr->vstval =3D nacl_csr_read(nsh, CSR_VSTVAL); csr->hvip =3D nacl_csr_read(nsh, CSR_HVIP); csr->vsatp =3D nacl_csr_read(nsh, CSR_VSATP); + cfg->hedeleg =3D nacl_csr_read(nsh, CSR_HEDELEG); } else { csr->vsstatus =3D csr_read(CSR_VSSTATUS); csr->vsie =3D csr_read(CSR_VSIE); @@ -676,6 +678,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) csr->vstval =3D csr_read(CSR_VSTVAL); csr->hvip =3D csr_read(CSR_HVIP); csr->vsatp =3D csr_read(CSR_VSATP); + cfg->hedeleg =3D csr_read(CSR_HEDELEG); } } =20 diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c index 55433e805baa..1e85ff6666af 100644 --- a/arch/riscv/kvm/vcpu_sbi_fwft.c +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c @@ -14,6 +14,8 @@ #include #include =20 +#define MIS_DELEG (1UL << EXC_LOAD_MISALIGNED | 1UL << EXC_STORE_MISALIGNE= D) + static const enum sbi_fwft_feature_t kvm_fwft_defined_features[] =3D { SBI_FWFT_MISALIGNED_EXC_DELEG, SBI_FWFT_LANDING_PAD, @@ -35,7 +37,44 @@ static bool kvm_fwft_is_defined_feature(enum sbi_fwft_fe= ature_t feature) return false; } =20 +static bool kvm_sbi_fwft_misaligned_delegation_supported(struct kvm_vcpu *= vcpu) +{ + if (!unaligned_ctl_available()) + return false; + + return true; +} + +static int kvm_sbi_fwft_set_misaligned_delegation(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + unsigned long value) +{ + if (value =3D=3D 1) + csr_set(CSR_HEDELEG, MIS_DELEG); + else if (value =3D=3D 0) + csr_clear(CSR_HEDELEG, MIS_DELEG); + else + return SBI_ERR_INVALID_PARAM; + + return SBI_SUCCESS; +} + +static int kvm_sbi_fwft_get_misaligned_delegation(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + unsigned long *value) +{ + *value =3D (csr_read(CSR_HEDELEG) & MIS_DELEG) !=3D 0; + + return SBI_SUCCESS; +} + static const struct kvm_sbi_fwft_feature features[] =3D { + { + .id =3D SBI_FWFT_MISALIGNED_EXC_DELEG, + .supported =3D kvm_sbi_fwft_misaligned_delegation_supported, + .set =3D kvm_sbi_fwft_set_misaligned_delegation, + .get =3D kvm_sbi_fwft_get_misaligned_delegation, + } }; =20 static struct kvm_sbi_fwft_config * --=20 2.47.1