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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc9f6967sm292479535ad.214.2025.01.06.07.49.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jan 2025 07:49:17 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= Subject: [PATCH 2/6] riscv: request misaligned exception delegation from SBI Date: Mon, 6 Jan 2025 16:48:39 +0100 Message-ID: <20250106154847.1100344-3-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250106154847.1100344-1-cleger@rivosinc.com> References: <20250106154847.1100344-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Now that the kernel can handle misaligned accesses in S-mode, request misaligned access exception delegation from SBI. This uses the FWFT SBI extension defined in SBI version 3.0. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Jesse Taube --- arch/riscv/include/asm/cpufeature.h | 1 + arch/riscv/kernel/traps_misaligned.c | 59 ++++++++++++++++++++++ arch/riscv/kernel/unaligned_access_speed.c | 2 + 3 files changed, 62 insertions(+) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index 4bd054c54c21..cd406fe37df8 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -62,6 +62,7 @@ void __init riscv_user_isa_enable(void); _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), _valida= te) =20 bool check_unaligned_access_emulated_all_cpus(void); +void unaligned_access_init(void); #if defined(CONFIG_RISCV_SCALAR_MISALIGNED) void check_unaligned_access_emulated(struct work_struct *work __always_unu= sed); void unaligned_emulation_finish(void); diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index 7cc108aed74e..4aca600527e9 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -16,6 +16,7 @@ #include #include #include +#include #include =20 #define INSN_MATCH_LB 0x3 @@ -689,3 +690,61 @@ bool check_unaligned_access_emulated_all_cpus(void) return false; } #endif + +#ifdef CONFIG_RISCV_SBI + +struct misaligned_deleg_req { + bool enable; + int error; +}; + +static void +cpu_unaligned_sbi_request_delegation(void *arg) +{ + struct misaligned_deleg_req *req =3D arg; + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_FWFT, SBI_EXT_FWFT_SET, + SBI_FWFT_MISALIGNED_EXC_DELEG, req->enable, 0, 0, 0, 0); + if (ret.error) + req->error =3D 1; +} + +static void unaligned_sbi_request_delegation(void) +{ + struct misaligned_deleg_req req =3D {true, 0}; + + on_each_cpu(cpu_unaligned_sbi_request_delegation, &req, 1); + if (!req.error) { + pr_info("SBI misaligned access exception delegation ok\n"); + /* + * Note that we don't have to take any specific action here, if + * the delegation is successful, then + * check_unaligned_access_emulated() will verify that indeed the + * platform traps on misaligned accesses. + */ + return; + } + + /* + * If at least delegation request failed on one hart, revert misaligned + * delegation for all harts, if we don't do that, we'll panic at + * misaligned delegation check time (see + * check_unaligned_access_emulated()). + */ + req.enable =3D false; + req.error =3D 0; + on_each_cpu(cpu_unaligned_sbi_request_delegation, &req, 1); + if (req.error) + panic("Failed to disable misaligned delegation for all CPUs\n"); + +} + +void unaligned_access_init(void) +{ + if (sbi_probe_extension(SBI_EXT_FWFT) > 0) + unaligned_sbi_request_delegation(); +} +#else +void unaligned_access_init(void) {} +#endif diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel= /unaligned_access_speed.c index 91f189cf1611..1e3166100837 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -403,6 +403,8 @@ static int check_unaligned_access_all_cpus(void) { bool all_cpus_emulated, all_cpus_vec_unsupported; =20 + unaligned_access_init(); + all_cpus_emulated =3D check_unaligned_access_emulated_all_cpus(); all_cpus_vec_unsupported =3D check_vector_unaligned_access_emulated_all_c= pus(); =20 --=20 2.47.1