From nobody Tue Feb 10 15:45:55 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72F151DE3AF for ; Mon, 6 Jan 2025 13:16:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736169411; cv=none; b=UeoFDnmKqvTbH6TKFkvDtnku1atEwBlfQyFak1noslBzOJX30hNrRXthn9bwqDU8GtM7AlHZNXvZfgETRg+xBVkJjUmMqLRqhwKFjS4hDzIHqaQyp+YuAkzwCkTFMg53AUEYwXctiIzdJxzC0DPVrtC4DNDAndTNfG368a5N1hE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736169411; c=relaxed/simple; bh=G/T0r2QpWmY2BDMfRNd6yYRPdn1IfToAGAAM3P0knhM=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=VNt8zX81FpHX+Xujeo+/ZEyl783XStYPjvEkv/IiMUx/baFHeNQSCDazIkmIDdiiKYv8jWYMRRgC5cSPMHunaO29p1drrgZB0hWf5EuSDcEKvNauoTtbpr0NhJ1wFAnmHg3VlnuL1n6s4Jd3LrUsZg3i42Xt8bw9IzUeXGLv+5s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=kMllTYnp; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="kMllTYnp" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 506C8nMI017057; Mon, 6 Jan 2025 13:16:22 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=qcppdkim1; bh=Rf7oXGLumTIZDwdMDq2aR1 PdoWsVej2SESBLdy8Fyl8=; b=kMllTYnpPdIaxq/HzCSrF7i1VKDnu313N/5Z8p 1SX7Pe4wXD8/rwL2S7KYsn/pmK/3oc2F/JZW96OSL+7/Aply1dyHWuTpH3rjMNa2 i9toLOKKkKg8LczPK8Qt77qbFxz9xl+ns/YZ4q6Oe+oTwf4AdZ7DO4Xor5N8oz3g SPdBbEFS/Yt2/6ex7nwe0X6FjpAVVSOlGFnWftNgTSZXJZUTvhqdezJk0I/3wAs8 Mh0x9mB8Va7CqkFn57f4oHSm3c7Xi0dU9OG/Ec6kdoVmhgTfhTgx+E9iPktrBMh3 xnR8RNt6+gMjgsnax1OwROMoTKHssOMPIGozJadMqlVv1pOg== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44054ehewx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 06 Jan 2025 13:16:22 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 506DGHFa010988 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 6 Jan 2025 13:16:17 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 6 Jan 2025 05:16:13 -0800 From: Md Sadre Alam To: , , , , CC: , , , , Subject: [PATCH] mtd: rawnand: qcom: Fix build issue on x86 architecture Date: Mon, 6 Jan 2025 18:45:58 +0530 Message-ID: <20250106131558.2219136-1-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: IPVfhfgEpwmZ9mSyqS92s4RZaIe22U7t X-Proofpoint-ORIG-GUID: IPVfhfgEpwmZ9mSyqS92s4RZaIe22U7t X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 impostorscore=0 bulkscore=0 phishscore=0 suspectscore=0 clxscore=1015 mlxlogscore=946 adultscore=0 lowpriorityscore=0 malwarescore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501060118 Fix a buffer overflow issue in qcom_clear_bam_transaction by using struct_group to group related fields and avoid FORTIFY_SOURCE warnings. On x86 architecture, the following error occurs due to warnings being treated as errors: In function =E2=80=98fortify_memset_chk=E2=80=99, inlined from =E2=80=98qcom_clear_bam_transaction=E2=80=99 at drivers/mtd/nand/qpic_common.c:88:2: ./include/linux/fortify-string.h:480:25: error: call to =E2=80=98__write_ov= erflow_field=E2=80=99 declared with attribute warning: detected write beyond size of field (1st parameter); maybe use struct_group()? [-Werror=3Dattribute-warning] 480 | __write_overflow_field(p_size_field, size); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ LD [M] drivers/mtd/nand/nandcore.o CC [M] drivers/w1/masters/mxc_w1.o cc1: all warnings being treated as errors This patch addresses the issue by grouping the related fields in struct bam_transaction using struct_group and updating the memset call accordingly. Fixes: 8c52932da5e6 ("mtd: rawnand: qcom: cleanup qcom_nandc driver") Signed-off-by: Md Sadre Alam --- drivers/mtd/nand/qpic_common.c | 2 +- include/linux/mtd/nand-qpic-common.h | 19 +++++++++++-------- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/nand/qpic_common.c b/drivers/mtd/nand/qpic_common.c index 8abbb960a7ce..e0ed25b5afea 100644 --- a/drivers/mtd/nand/qpic_common.c +++ b/drivers/mtd/nand/qpic_common.c @@ -85,7 +85,7 @@ void qcom_clear_bam_transaction(struct qcom_nand_controll= er *nandc) if (!nandc->props->supports_bam) return; =20 - memset(&bam_txn->bam_ce_pos, 0, sizeof(u32) * 8); + memset(&bam_txn->bam_positions, 0, sizeof(bam_txn->bam_positions)); bam_txn->last_data_desc =3D NULL; =20 sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage * diff --git a/include/linux/mtd/nand-qpic-common.h b/include/linux/mtd/nand-= qpic-common.h index e79c79775eb8..4d9b736ff8b7 100644 --- a/include/linux/mtd/nand-qpic-common.h +++ b/include/linux/mtd/nand-qpic-common.h @@ -254,14 +254,17 @@ struct bam_transaction { struct dma_async_tx_descriptor *last_data_desc; struct dma_async_tx_descriptor *last_cmd_desc; struct completion txn_done; - u32 bam_ce_pos; - u32 bam_ce_start; - u32 cmd_sgl_pos; - u32 cmd_sgl_start; - u32 tx_sgl_pos; - u32 tx_sgl_start; - u32 rx_sgl_pos; - u32 rx_sgl_start; + struct_group(bam_positions, + u32 bam_ce_pos; + u32 bam_ce_start; + u32 cmd_sgl_pos; + u32 cmd_sgl_start; + u32 tx_sgl_pos; + u32 tx_sgl_start; + u32 rx_sgl_pos; + u32 rx_sgl_start; + + ); }; =20 /* --=20 2.34.1