From nobody Wed Feb 11 04:00:43 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 30E4B1CCEC8 for ; Mon, 6 Jan 2025 09:01:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736154085; cv=none; b=Onnqq0LnboipXdTqtFZUkbE4WXABIniCbBdYy7n6g24cPj8wpqRsHjGclvxPmOa4WFnzb1fJymrS6abjTgmuHL7Sa8CaDU1SUT+6f21o7iLomZeZLiz28eB7QuMwW6QZ/DVHjZpwDQhutlnBih9uLhRr37aOZY1te1YWckQh0Go= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736154085; c=relaxed/simple; bh=MLXEyCIiMDWktlr2iqhQjbEZtBYosjMmeoiMpQX1mH4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PSPrkPosNuzryTDwqA7Md4qmTCuMeX5OMQotTFyrgajCnxAHq0sGD2azAsTM5SbabM6JULeC5VjfZihXxheUfiG03Tq65Oq/FAFpOslKUzHmRyStA3FsfYRefDlH9S1YZNvUfvvwRNxVvkeIQAmjHfKn0ZXpTxFfZaPjfIxmLWQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [113.200.148.30]) by gateway (Coremail) with SMTP id _____8DxbKzfm3tnxI5eAA--.606S3; Mon, 06 Jan 2025 17:01:19 +0800 (CST) Received: from linux.localdomain (unknown [113.200.148.30]) by front1 (Coremail) with SMTP id qMiowMDx_8fTm3tn2UgWAA--.31746S2; Mon, 06 Jan 2025 17:01:07 +0800 (CST) From: Tiezhu Yang To: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Xinhui Pan , Harry Wentland , Leo Li , Rodrigo Siqueira Cc: Nathan Chancellor , Josh Poimboeuf , Peter Zijlstra , loongarch@lists.linux.dev, amd-gfx@lists.freedesktop.org, llvm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/5] drm/amd/display: Replace SPL_ASSERT() with SPL_ASSERT_WARN() Date: Mon, 6 Jan 2025 17:01:06 +0800 Message-ID: <20250106090106.4683-1-yangtiezhu@loongson.cn> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20250106085755.3268-1-yangtiezhu@loongson.cn> References: <20250106085755.3268-1-yangtiezhu@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMDx_8fTm3tn2UgWAA--.31746S2 X-CM-SenderInfo: p1dqw3xlh2x3gn0dqz5rrqw2lrqou0/ X-Coremail-Antispam: 1Uk129KBj93XoWfGrW8KFyxZrWfZFyfuF43CFX_yoWkAr4xpa 1fJry8ZF4jqayvqFZrW34UuF93Ja4rtrW2q3Z3W3ykWa4xCw15Ja9rtrs3Ar4UCr9xAa47 AFyFgrWUKayktwcCm3ZEXasCq-sJn29KB7ZKAUJUUUUx529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUBIb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2kKe7AKxVWUAVWUtwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07 AIYIkI8VC2zVCFFI0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWU tVWrXwAv7VC2z280aVAFwI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7V AKI48JMxkF7I0En4kS14v26r1q6r43MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY 6r1j6r4UMxCIbckI1I0E14v26r126r1DMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7 xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xII jxv20xvE14v26r4j6ryUMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw2 0EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x02 67AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IU8XTm3UUUUU== Content-Type: text/plain; charset="utf-8" SPL_ASSERT() is actually SPL_ASSERT_WARN() according to the macro definition in drivers/gpu/drm/amd/display/dc/spl/spl_debug.h, just replace the macro name SPL_ASSERT() with explicit SPL_ASSERT_WARN() to avoid ambiguous. Here is the one-line script: sed -i "s/\/SPL_ASSERT_WARN/g" `grep SPL_ASSERT -rwl drivers= /gpu/drm/amd/display` This is in preparation to add SPL_ASSERT_BUG() in later patch to harden the callers of division functions, no functional change intended. Signed-off-by: Tiezhu Yang --- drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 12 +++---- .../gpu/drm/amd/display/dc/spl/spl_debug.h | 6 ++-- .../drm/amd/display/dc/spl/spl_fixpt31_32.c | 32 +++++++++---------- .../drm/amd/display/dc/spl/spl_fixpt31_32.h | 12 +++---- 4 files changed, 31 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c b/drivers/gpu/drm/= amd/display/dc/spl/dc_spl.c index 73a65913cb12..664343102f46 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c @@ -146,7 +146,7 @@ static struct spl_rect calculate_mpc_slice_in_timing_ac= tive( mpc_rec.x =3D plane_clip_rec->x + mpc_rec.width * mpc_slice_idx; mpc_rec.height =3D plane_clip_rec->height; mpc_rec.y =3D plane_clip_rec->y; - SPL_ASSERT(mpc_slice_count =3D=3D 1 || + SPL_ASSERT_WARN(mpc_slice_count =3D=3D 1 || spl_in->basic_out.view_format !=3D SPL_VIEW_3D_SIDE_BY_SIDE || mpc_rec.width % 2 =3D=3D 0); =20 @@ -159,7 +159,7 @@ static struct spl_rect calculate_mpc_slice_in_timing_ac= tive( } =20 if (spl_in->basic_out.view_format =3D=3D SPL_VIEW_3D_TOP_AND_BOTTOM) { - SPL_ASSERT(mpc_rec.height % 2 =3D=3D 0); + SPL_ASSERT_WARN(mpc_rec.height % 2 =3D=3D 0); mpc_rec.height /=3D 2; } return mpc_rec; @@ -666,7 +666,7 @@ static void spl_calculate_inits_and_viewports(struct sp= l_in *spl_in, } spl_scratch->scl_data.viewport.x +=3D src.x; spl_scratch->scl_data.viewport.y +=3D src.y; - SPL_ASSERT(src.x % vpc_div =3D=3D 0 && src.y % vpc_div =3D=3D 0); + SPL_ASSERT_WARN(src.x % vpc_div =3D=3D 0 && src.y % vpc_div =3D=3D 0); spl_scratch->scl_data.viewport_c.x +=3D src.x / vpc_div; spl_scratch->scl_data.viewport_c.y +=3D src.y / vpc_div; } @@ -679,7 +679,7 @@ static void spl_handle_3d_recout(struct spl_in *spl_in,= struct spl_rect *recout) * This may break with rotation, good thing we aren't mixing hw rotation = and 3d */ if (spl_in->basic_in.mpc_combine_v) { - SPL_ASSERT(spl_in->basic_in.rotation =3D=3D SPL_ROTATION_ANGLE_0 || + SPL_ASSERT_WARN(spl_in->basic_in.rotation =3D=3D SPL_ROTATION_ANGLE_0 || (spl_in->basic_out.view_format !=3D SPL_VIEW_3D_TOP_AND_BOTTOM && spl_in->basic_out.view_format !=3D SPL_VIEW_3D_SIDE_BY_SIDE)); if (spl_in->basic_out.view_format =3D=3D SPL_VIEW_3D_TOP_AND_BOTTOM) @@ -1052,7 +1052,7 @@ static bool spl_get_optimal_number_of_taps( *enable_easf_v =3D true; *enable_easf_h =3D true; } - SPL_ASSERT((spl_scratch->scl_data.taps.v_taps > 1) && + SPL_ASSERT_WARN((spl_scratch->scl_data.taps.v_taps > 1) && (spl_scratch->scl_data.taps.v_taps_c > 1)); } else { /* RGB */ if (spl_scratch->scl_data.taps.h_taps <=3D 3) { @@ -1065,7 +1065,7 @@ static bool spl_get_optimal_number_of_taps( *enable_easf_v =3D true; *enable_easf_h =3D true; } - SPL_ASSERT(spl_scratch->scl_data.taps.v_taps > 1); + SPL_ASSERT_WARN(spl_scratch->scl_data.taps.v_taps > 1); } } else { *enable_easf_v =3D false; diff --git a/drivers/gpu/drm/amd/display/dc/spl/spl_debug.h b/drivers/gpu/d= rm/amd/display/dc/spl/spl_debug.h index a6f6132df241..f01c932d550d 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/spl_debug.h +++ b/drivers/gpu/drm/amd/display/dc/spl/spl_debug.h @@ -20,11 +20,11 @@ #endif /* CONFIG_HAVE_KGDB || CONFIG_KGDB */ =20 #if defined(CONFIG_DEBUG_KERNEL_DC) -#define SPL_ASSERT(expr) SPL_ASSERT_CRITICAL(expr) +#define SPL_ASSERT_WARN(expr) SPL_ASSERT_CRITICAL(expr) #else -#define SPL_ASSERT(expr) WARN_ON(!(expr)) +#define SPL_ASSERT_WARN(expr) WARN_ON(!(expr)) #endif /* CONFIG_DEBUG_KERNEL_DC */ =20 -#define SPL_BREAK_TO_DEBUGGER() SPL_ASSERT(0) +#define SPL_BREAK_TO_DEBUGGER() SPL_ASSERT_WARN(0) =20 #endif // SPL_DEBUG_H diff --git a/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.c b/drivers/= gpu/drm/amd/display/dc/spl/spl_fixpt31_32.c index 131f1e3949d3..07a5c09b250e 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.c +++ b/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.c @@ -29,7 +29,7 @@ static inline unsigned long long spl_complete_integer_div= ision_u64( { unsigned long long result; =20 - SPL_ASSERT(divisor); + SPL_ASSERT_WARN(divisor); =20 result =3D spl_div64_u64_rem(dividend, divisor, remainder); =20 @@ -63,7 +63,7 @@ struct spl_fixed31_32 spl_fixpt_from_fraction(long long n= umerator, long long den unsigned long long res_value =3D spl_complete_integer_division_u64( arg1_value, arg2_value, &remainder); =20 - SPL_ASSERT(res_value <=3D (unsigned long long)LONG_MAX); + SPL_ASSERT_WARN(res_value <=3D (unsigned long long)LONG_MAX); =20 /* determine fractional part */ { @@ -85,7 +85,7 @@ struct spl_fixed31_32 spl_fixpt_from_fraction(long long n= umerator, long long den { unsigned long long summand =3D (remainder << 1) >=3D arg2_value; =20 - SPL_ASSERT(res_value <=3D (unsigned long long)LLONG_MAX - summand); + SPL_ASSERT_WARN(res_value <=3D (unsigned long long)LLONG_MAX - summand); =20 res_value +=3D summand; } @@ -118,19 +118,19 @@ struct spl_fixed31_32 spl_fixpt_mul(struct spl_fixed3= 1_32 arg1, struct spl_fixed =20 res.value =3D arg1_int * arg2_int; =20 - SPL_ASSERT(res.value <=3D (long long)LONG_MAX); + SPL_ASSERT_WARN(res.value <=3D (long long)LONG_MAX); =20 res.value <<=3D FIXED31_32_BITS_PER_FRACTIONAL_PART; =20 tmp =3D arg1_int * arg2_fra; =20 - SPL_ASSERT(tmp <=3D (unsigned long long)(LLONG_MAX - res.value)); + SPL_ASSERT_WARN(tmp <=3D (unsigned long long)(LLONG_MAX - res.value)); =20 res.value +=3D tmp; =20 tmp =3D arg2_int * arg1_fra; =20 - SPL_ASSERT(tmp <=3D (unsigned long long)(LLONG_MAX - res.value)); + SPL_ASSERT_WARN(tmp <=3D (unsigned long long)(LLONG_MAX - res.value)); =20 res.value +=3D tmp; =20 @@ -139,7 +139,7 @@ struct spl_fixed31_32 spl_fixpt_mul(struct spl_fixed31_= 32 arg1, struct spl_fixed tmp =3D (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) + (tmp >=3D (unsigned long long)spl_fixpt_half.value); =20 - SPL_ASSERT(tmp <=3D (unsigned long long)(LLONG_MAX - res.value)); + SPL_ASSERT_WARN(tmp <=3D (unsigned long long)(LLONG_MAX - res.value)); =20 res.value +=3D tmp; =20 @@ -163,17 +163,17 @@ struct spl_fixed31_32 spl_fixpt_sqr(struct spl_fixed3= 1_32 arg) =20 res.value =3D arg_int * arg_int; =20 - SPL_ASSERT(res.value <=3D (long long)LONG_MAX); + SPL_ASSERT_WARN(res.value <=3D (long long)LONG_MAX); =20 res.value <<=3D FIXED31_32_BITS_PER_FRACTIONAL_PART; =20 tmp =3D arg_int * arg_fra; =20 - SPL_ASSERT(tmp <=3D (unsigned long long)(LLONG_MAX - res.value)); + SPL_ASSERT_WARN(tmp <=3D (unsigned long long)(LLONG_MAX - res.value)); =20 res.value +=3D tmp; =20 - SPL_ASSERT(tmp <=3D (unsigned long long)(LLONG_MAX - res.value)); + SPL_ASSERT_WARN(tmp <=3D (unsigned long long)(LLONG_MAX - res.value)); =20 res.value +=3D tmp; =20 @@ -182,7 +182,7 @@ struct spl_fixed31_32 spl_fixpt_sqr(struct spl_fixed31_= 32 arg) tmp =3D (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) + (tmp >=3D (unsigned long long)spl_fixpt_half.value); =20 - SPL_ASSERT(tmp <=3D (unsigned long long)(LLONG_MAX - res.value)); + SPL_ASSERT_WARN(tmp <=3D (unsigned long long)(LLONG_MAX - res.value)); =20 res.value +=3D tmp; =20 @@ -196,7 +196,7 @@ struct spl_fixed31_32 spl_fixpt_recip(struct spl_fixed3= 1_32 arg) * Good idea to use Newton's method */ =20 - SPL_ASSERT(arg.value); + SPL_ASSERT_WARN(arg.value); =20 return spl_fixpt_from_fraction( spl_fixpt_one.value, @@ -295,7 +295,7 @@ static struct spl_fixed31_32 spl_fixed31_32_exp_from_ta= ylor_series(struct spl_fi n + 1); /* TODO find correct res */ =20 - SPL_ASSERT(spl_fixpt_lt(arg, spl_fixpt_one)); + SPL_ASSERT_WARN(spl_fixpt_lt(arg, spl_fixpt_one)); =20 do res =3D spl_fixpt_add( @@ -337,9 +337,9 @@ struct spl_fixed31_32 spl_fixpt_exp(struct spl_fixed31_= 32 arg) spl_fixpt_ln2, m)); =20 - SPL_ASSERT(m !=3D 0); + SPL_ASSERT_WARN(m !=3D 0); =20 - SPL_ASSERT(spl_fixpt_lt( + SPL_ASSERT_WARN(spl_fixpt_lt( spl_fixpt_abs(r), spl_fixpt_one)); =20 @@ -364,7 +364,7 @@ struct spl_fixed31_32 spl_fixpt_log(struct spl_fixed31_= 32 arg) =20 struct spl_fixed31_32 error; =20 - SPL_ASSERT(arg.value > 0); + SPL_ASSERT_WARN(arg.value > 0); /* TODO if arg is negative, return NaN */ /* TODO if arg is zero, return -INF */ =20 diff --git a/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.h b/drivers/= gpu/drm/amd/display/dc/spl/spl_fixpt31_32.h index ed2647f9a099..b285f4397f07 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.h +++ b/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.h @@ -191,7 +191,7 @@ static inline struct spl_fixed31_32 spl_fixpt_clamp( */ static inline struct spl_fixed31_32 spl_fixpt_shl(struct spl_fixed31_32 ar= g, unsigned char shift) { - SPL_ASSERT(((arg.value >=3D 0) && (arg.value <=3D LLONG_MAX >> shift)) || + SPL_ASSERT_WARN(((arg.value >=3D 0) && (arg.value <=3D LLONG_MAX >> shift= )) || ((arg.value < 0) && (arg.value >=3D ~(LLONG_MAX >> shift)))); =20 arg.value =3D arg.value << shift; @@ -228,7 +228,7 @@ static inline struct spl_fixed31_32 spl_fixpt_add(struc= t spl_fixed31_32 arg1, st { struct spl_fixed31_32 res; =20 - SPL_ASSERT(((arg1.value >=3D 0) && (LLONG_MAX - arg1.value >=3D arg2.valu= e)) || + SPL_ASSERT_WARN(((arg1.value >=3D 0) && (LLONG_MAX - arg1.value >=3D arg2= .value)) || ((arg1.value < 0) && (LLONG_MIN - arg1.value <=3D arg2.value))); =20 res.value =3D arg1.value + arg2.value; @@ -253,7 +253,7 @@ static inline struct spl_fixed31_32 spl_fixpt_sub(struc= t spl_fixed31_32 arg1, st { struct spl_fixed31_32 res; =20 - SPL_ASSERT(((arg2.value >=3D 0) && (LLONG_MIN + arg2.value <=3D arg1.valu= e)) || + SPL_ASSERT_WARN(((arg2.value >=3D 0) && (LLONG_MIN + arg2.value <=3D arg1= .value)) || ((arg2.value < 0) && (LLONG_MAX + arg2.value >=3D arg1.value))); =20 res.value =3D arg1.value - arg2.value; @@ -445,7 +445,7 @@ static inline int spl_fixpt_round(struct spl_fixed31_32= arg) =20 const long long summand =3D spl_fixpt_half.value; =20 - SPL_ASSERT(LLONG_MAX - (long long)arg_value >=3D summand); + SPL_ASSERT_WARN(LLONG_MAX - (long long)arg_value >=3D summand); =20 arg_value +=3D summand; =20 @@ -466,7 +466,7 @@ static inline int spl_fixpt_ceil(struct spl_fixed31_32 = arg) const long long summand =3D spl_fixpt_one.value - spl_fixpt_epsilon.value; =20 - SPL_ASSERT(LLONG_MAX - (long long)arg_value >=3D summand); + SPL_ASSERT_WARN(LLONG_MAX - (long long)arg_value >=3D summand); =20 arg_value +=3D summand; =20 @@ -501,7 +501,7 @@ static inline struct spl_fixed31_32 spl_fixpt_truncate(= struct spl_fixed31_32 arg bool negative =3D arg.value < 0; =20 if (frac_bits >=3D FIXED31_32_BITS_PER_FRACTIONAL_PART) { - SPL_ASSERT(frac_bits =3D=3D FIXED31_32_BITS_PER_FRACTIONAL_PART); + SPL_ASSERT_WARN(frac_bits =3D=3D FIXED31_32_BITS_PER_FRACTIONAL_PART); return arg; } =20 --=20 2.42.0