From nobody Tue Feb 10 20:06:05 2026 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F6D51D63F5; Mon, 6 Jan 2025 07:11:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736147494; cv=none; b=Io1veKR/px7bAF5wAfKAYTxPAvNf5+qrVo7CCPF+Gdaey+ZWiSMUi0zZSV0pObLLZ6c//Q7L1aPZfN4/Nkr/gFdBI3wy2qACvyuFy9BZUdqCWwK74bo0tFluXRQKPRDjzp7n6nFiEVeegoLu6m26bqtSQYaq1PVjxC5Q1l8MjYo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736147494; c=relaxed/simple; bh=5lhneQP8cS1astWGORHzpojAcmqjPfSGXb0ZA8OVBQs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=O38dn+nGTVVnWuHfIvFi+LZenRYq9NxGj0SVoWtjvNqEV1jsRUMathYvDhvDaXX3zDKuRHAAne9c/koROQwXf9QkInyZqecN7laLiSFvLefyOgA2OTqJKzfJdSb09NGQqR3CMKbwafEbsVkdyQY6HIZ8zsKC6/HFX7MwIkJrD9Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com; spf=pass smtp.mailfrom=zytor.com; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b=R7UE49X4; arc=none smtp.client-ip=198.137.202.136 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zytor.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b="R7UE49X4" Received: from terminus.zytor.com (terminus.zytor.com [IPv6:2607:7c80:54:3:0:0:0:136]) (authenticated bits=0) by mail.zytor.com (8.18.1/8.17.1) with ESMTPSA id 50677RpA3211026 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO); Sun, 5 Jan 2025 23:07:33 -0800 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 50677RpA3211026 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2024121701; t=1736147253; bh=0IXB2jBiJPz8ByNPP/BjmChXzReQlc5twftE/TJErz4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=R7UE49X4YgYaKL/LbQ0HGfD0MPs5QkbgqKyJqYt1TmttyFBFpxXuah40MW2/gOAi/ l9WQZZNt8czLuFxCmZn44j4Sau+W26WICUmWWLjzOYW5GD0Wa7jbfTvIok0hbNDfwa DKSj9ahNwe608VJOPQILc//AmUQtbRp9U3WNEzh6uJrrcPT64cCXVyXVH65P1QLL2c yqnUgTPm96QpAut/v6lZdzFMUIeuhUPmExHqJ1n1b+fQFvPFotAhKTrYxoZ9MAZg6F UB6+w1Af9kkz2iqtx/3X2vrE9nhCVjPfs6wv5lhic6XWsqnMYsyOOhIs8/Kld8gBFy gLTvQcf3nF3aQ== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, will@kernel.org, peterz@infradead.org, yury.norov@gmail.com, akpm@linux-foundation.org, acme@kernel.org, namhyung@kernel.org, brgerst@gmail.com, andrew.cooper3@citrix.com, nik.borisov@suse.com Subject: [PATCH v5 1/5] x86/cpufeatures: Add {required,disabled} feature configs Date: Sun, 5 Jan 2025 23:07:23 -0800 Message-ID: <20250106070727.3211006-2-xin@zytor.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250106070727.3211006-1-xin@zytor.com> References: <20250106070727.3211006-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "H. Peter Anvin (Intel)" Required and disabled feature masks completely rely on build configs, i.e., once a build config is fixed, so are the feature masks. To prepare for auto-generating a header with required and disabled feature masks based on a build config, add feature Kconfig items: - X86_REQUIRED_FEATURE_x - X86_DISABLED_FEATURE_x each of which may be set to "y" if and only if its preconditions from current build config are met. X86_CMPXCHG64 and X86_CMOV are required features, thus rename them to X86_REQUIRED_FEATURE_CX8 and X86_REQUIRED_FEATURE_CMOV. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li (Intel) --- Changes since v1: * Keep the X86_{REQUIRED,DISABLED}_FEATURE_ prefixes solely in arch/x86/Kconfig.cpufeatures (Borislav Petkov). * Explain how config option names X86_{REQUIRED,DISABLED}_FEATURE_ are formed (Borislav Petkov). --- arch/x86/Kconfig | 4 +- arch/x86/Kconfig.cpu | 12 +- arch/x86/Kconfig.cpufeatures | 197 ++++++++++++++++++ arch/x86/include/asm/asm-prototypes.h | 2 +- arch/x86/include/asm/atomic64_32.h | 2 +- arch/x86/include/asm/bitops.h | 4 +- arch/x86/include/asm/cmpxchg_32.h | 2 +- arch/x86/include/asm/required-features.h | 4 +- arch/x86/lib/Makefile | 2 +- arch/x86/lib/cmpxchg8b_emu.S | 2 +- lib/atomic64_test.c | 2 +- .../arch/x86/include/asm/required-features.h | 4 +- 12 files changed, 213 insertions(+), 24 deletions(-) create mode 100644 arch/x86/Kconfig.cpufeatures diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index e4e27d44dc2b..1c1f73202903 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -131,7 +131,7 @@ config X86 select ARCH_SUPPORTS_AUTOFDO_CLANG select ARCH_SUPPORTS_PROPELLER_CLANG if X86_64 select ARCH_USE_BUILTIN_BSWAP - select ARCH_USE_CMPXCHG_LOCKREF if X86_CMPXCHG64 + select ARCH_USE_CMPXCHG_LOCKREF if X86_REQUIRED_FEATURE_CX8 select ARCH_USE_MEMTEST select ARCH_USE_QUEUED_RWLOCKS select ARCH_USE_QUEUED_SPINLOCKS @@ -3191,4 +3191,6 @@ config HAVE_ATOMIC_IOMAP =20 source "arch/x86/kvm/Kconfig" =20 +source "arch/x86/Kconfig.cpufeatures" + source "arch/x86/Kconfig.assembler" diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 2a7279d80460..c439f9c61101 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -366,21 +366,11 @@ config X86_HAVE_PAE def_bool y depends on MCRUSOE || MEFFICEON || MCYRIXIII || MPENTIUM4 || MPENTIUMM ||= MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC7 || MCORE2 || MATOM || X= 86_64 =20 -config X86_CMPXCHG64 - def_bool y - depends on X86_HAVE_PAE || M586TSC || M586MMX || MK6 || MK7 - -# this should be set for all -march=3D.. options where the compiler -# generates cmov. -config X86_CMOV - def_bool y - depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII= || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86= _64 || MATOM || MGEODE_LX) - config X86_MINIMUM_CPU_FAMILY int default "64" if X86_64 default "6" if X86_32 && (MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTI= UMII || M686 || MVIAC3_2 || MVIAC7 || MEFFICEON || MATOM || MCORE2 || MK7 |= | MK8) - default "5" if X86_32 && X86_CMPXCHG64 + default "5" if X86_32 && X86_REQUIRED_FEATURE_CX8 default "4" =20 config X86_DEBUGCTLMSR diff --git a/arch/x86/Kconfig.cpufeatures b/arch/x86/Kconfig.cpufeatures new file mode 100644 index 000000000000..5ed24e45df87 --- /dev/null +++ b/arch/x86/Kconfig.cpufeatures @@ -0,0 +1,197 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# x86 feature bits (see arch/x86/include/asm/cpufeatures.h) that are +# either REQUIRED to be enabled, or DISABLED (always ignored) for this +# particular compile-time configuration. The tests for these features +# are turned into compile-time constants via the generated +# . +# +# The naming of these variables *must* match asm/cpufeatures.h, e.g., +# X86_FEATURE_ALWAYS <=3D=3D> X86_REQUIRED_FEATURE_ALWAYS +# X86_FEATURE_FRED <=3D=3D> X86_DISABLED_FEATURE_FRED +# +# And these REQUIRED and DISABLED config options are manipulated in an +# AWK script as the following example: +# +# +----------------------+ +# | X86_FRED =3D y ? | +# +----------------------+ +# / \ +# Y / \ N +# +-------------------------------------+ +----------------------------= ---+ +# | X86_DISABLED_FEATURE_FRED undefined | | X86_DISABLED_FEATURE_FRED = =3D y | +# +-------------------------------------+ +----------------------------= ---+ +# | +# | +# +-------------------------------------------+ | +# | X86_FEATURE_FRED: feature word 12, bit 17 | ---->| +# +-------------------------------------------+ | +# | +# | +# +-------------------------------+ +# | set bit 17 of DISABLED_MASK12 | +# +-------------------------------+ +# + +config X86_REQUIRED_FEATURE_ALWAYS + def_bool y + +config X86_REQUIRED_FEATURE_NOPL + def_bool y + depends on X86_64 || X86_P6_NOP + +config X86_REQUIRED_FEATURE_CX8 + def_bool y + depends on X86_HAVE_PAE || M586TSC || M586MMX || MK6 || MK7 + +# this should be set for all -march=3D.. options where the compiler +# generates cmov. +config X86_REQUIRED_FEATURE_CMOV + def_bool y + depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII= || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86= _64 || MATOM || MGEODE_LX) + +# this should be set for all -march=3D options where the compiler +# generates movbe. +config X86_REQUIRED_FEATURE_MOVBE + def_bool y + depends on MATOM + +config X86_REQUIRED_FEATURE_CPUID + def_bool y + depends on X86_64 + +config X86_REQUIRED_FEATURE_UP + def_bool y + depends on !SMP + +config X86_REQUIRED_FEATURE_FPU + def_bool y + depends on !MATH_EMULATION + +config X86_REQUIRED_FEATURE_PAE + def_bool y + depends on X86_64 || X86_PAE + +config X86_REQUIRED_FEATURE_PSE + def_bool y + depends on X86_64 && !PARAVIRT_XXL + +config X86_REQUIRED_FEATURE_PGE + def_bool y + depends on X86_64 && !PARAVIRT_XXL + +config X86_REQUIRED_FEATURE_MSR + def_bool y + depends on X86_64 + +config X86_REQUIRED_FEATURE_FXSR + def_bool y + depends on X86_64 + +config X86_REQUIRED_FEATURE_XMM + def_bool y + depends on X86_64 + +config X86_REQUIRED_FEATURE_XMM2 + def_bool y + depends on X86_64 + +config X86_REQUIRED_FEATURE_LM + def_bool y + depends on X86_64 + +config X86_DISABLED_FEATURE_UMIP + def_bool y + depends on !X86_UMIP + +config X86_DISABLED_FEATURE_VME + def_bool y + depends on X86_64 + +config X86_DISABLED_FEATURE_K6_MTRR + def_bool y + depends on X86_64 + +config X86_DISABLED_FEATURE_CYRIX_ARR + def_bool y + depends on X86_64 + +config X86_DISABLED_FEATURE_CENTAUR_MCR + def_bool y + depends on X86_64 + +config X86_DISABLED_FEATURE_PCID + def_bool y + depends on !X86_64 + +config X86_DISABLED_FEATURE_PKU + def_bool y + depends on !X86_INTEL_MEMORY_PROTECTION_KEYS + +config X86_DISABLED_FEATURE_OSPKE + def_bool y + depends on !X86_INTEL_MEMORY_PROTECTION_KEYS + +config X86_DISABLED_FEATURE_LA57 + def_bool y + depends on !X86_5LEVEL + +config X86_DISABLED_FEATURE_PTI + def_bool y + depends on !MITIGATION_PAGE_TABLE_ISOLATION + +config X86_DISABLED_FEATURE_RETPOLINE + def_bool y + depends on !MITIGATION_RETPOLINE + +config X86_DISABLED_FEATURE_RETPOLINE_LFENCE + def_bool y + depends on !MITIGATION_RETPOLINE + +config X86_DISABLED_FEATURE_RETHUNK + def_bool y + depends on !MITIGATION_RETHUNK + +config X86_DISABLED_FEATURE_UNRET + def_bool y + depends on !MITIGATION_UNRET_ENTRY + +config X86_DISABLED_FEATURE_CALL_DEPTH + def_bool y + depends on !MITIGATION_CALL_DEPTH_TRACKING + +config X86_DISABLED_FEATURE_LAM + def_bool y + depends on !ADDRESS_MASKING + +config X86_DISABLED_FEATURE_ENQCMD + def_bool y + depends on !INTEL_IOMMU_SVM + +config X86_DISABLED_FEATURE_SGX + def_bool y + depends on !X86_SGX + +config X86_DISABLED_FEATURE_XENPV + def_bool y + depends on !XEN_PV + +config X86_DISABLED_FEATURE_TDX_GUEST + def_bool y + depends on !INTEL_TDX_GUEST + +config X86_DISABLED_FEATURE_USER_SHSTK + def_bool y + depends on !X86_USER_SHADOW_STACK + +config X86_DISABLED_FEATURE_IBT + def_bool y + depends on !X86_KERNEL_IBT + +config X86_DISABLED_FEATURE_FRED + def_bool y + depends on !X86_FRED + +config X86_DISABLED_FEATURE_SEV_SNP + def_bool y + depends on !KVM_AMD_SEV diff --git a/arch/x86/include/asm/asm-prototypes.h b/arch/x86/include/asm/a= sm-prototypes.h index 3674006e3974..66fe5009830e 100644 --- a/arch/x86/include/asm/asm-prototypes.h +++ b/arch/x86/include/asm/asm-prototypes.h @@ -16,7 +16,7 @@ #include #include =20 -#ifndef CONFIG_X86_CMPXCHG64 +#ifndef CONFIG_X86_REQUIRED_FEATURE_CX8 extern void cmpxchg8b_emu(void); #endif =20 diff --git a/arch/x86/include/asm/atomic64_32.h b/arch/x86/include/asm/atom= ic64_32.h index 6c6e9b9f98a4..3dca0f13b59f 100644 --- a/arch/x86/include/asm/atomic64_32.h +++ b/arch/x86/include/asm/atomic64_32.h @@ -48,7 +48,7 @@ static __always_inline s64 arch_atomic64_read_nonatomic(c= onst atomic64_t *v) ATOMIC64_EXPORT(atomic64_##sym) #endif =20 -#ifdef CONFIG_X86_CMPXCHG64 +#ifdef CONFIG_X86_REQUIRED_FEATURE_CX8 #define __alternative_atomic64(f, g, out, in...) \ asm volatile("call %c[func]" \ : ALT_OUTPUT_SP(out) \ diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h index b96d45944c59..ff6444311704 100644 --- a/arch/x86/include/asm/bitops.h +++ b/arch/x86/include/asm/bitops.h @@ -321,7 +321,7 @@ static __always_inline int variable_ffs(int x) asm("bsfl %1,%0" : "=3Dr" (r) : ASM_INPUT_RM (x), "0" (-1)); -#elif defined(CONFIG_X86_CMOV) +#elif defined(CONFIG_X86_REQUIRED_FEATURE_CMOV) asm("bsfl %1,%0\n\t" "cmovzl %2,%0" : "=3D&r" (r) : "rm" (x), "r" (-1)); @@ -378,7 +378,7 @@ static __always_inline int fls(unsigned int x) asm("bsrl %1,%0" : "=3Dr" (r) : ASM_INPUT_RM (x), "0" (-1)); -#elif defined(CONFIG_X86_CMOV) +#elif defined(CONFIG_X86_REQUIRED_FEATURE_CMOV) asm("bsrl %1,%0\n\t" "cmovzl %2,%0" : "=3D&r" (r) : "rm" (x), "rm" (-1)); diff --git a/arch/x86/include/asm/cmpxchg_32.h b/arch/x86/include/asm/cmpxc= hg_32.h index fd1282a783dd..633ca915644a 100644 --- a/arch/x86/include/asm/cmpxchg_32.h +++ b/arch/x86/include/asm/cmpxchg_32.h @@ -69,7 +69,7 @@ static __always_inline bool __try_cmpxchg64_local(volatil= e u64 *ptr, u64 *oldp, return __arch_try_cmpxchg64(ptr, oldp, new,); } =20 -#ifdef CONFIG_X86_CMPXCHG64 +#ifdef CONFIG_X86_REQUIRED_FEATURE_CX8 =20 #define arch_cmpxchg64 __cmpxchg64 =20 diff --git a/arch/x86/include/asm/required-features.h b/arch/x86/include/as= m/required-features.h index e9187ddd3d1f..cef8104c103c 100644 --- a/arch/x86/include/asm/required-features.h +++ b/arch/x86/include/asm/required-features.h @@ -23,13 +23,13 @@ # define NEED_PAE 0 #endif =20 -#ifdef CONFIG_X86_CMPXCHG64 +#ifdef CONFIG_X86_REQUIRED_FEATURE_CX8 # define NEED_CX8 (1<<(X86_FEATURE_CX8 & 31)) #else # define NEED_CX8 0 #endif =20 -#if defined(CONFIG_X86_CMOV) || defined(CONFIG_X86_64) +#if defined(CONFIG_X86_REQUIRED_FEATURE_CMOV) || defined(CONFIG_X86_64) # define NEED_CMOV (1<<(X86_FEATURE_CMOV & 31)) #else # define NEED_CMOV 0 diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 98583a9dbab3..9d4e96157e81 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -49,7 +49,7 @@ ifeq ($(CONFIG_X86_32),y) lib-y +=3D string_32.o lib-y +=3D memmove_32.o lib-y +=3D cmpxchg8b_emu.o -ifneq ($(CONFIG_X86_CMPXCHG64),y) +ifneq ($(CONFIG_X86_REQUIRED_FEATURE_CX8),y) lib-y +=3D atomic64_386_32.o endif else diff --git a/arch/x86/lib/cmpxchg8b_emu.S b/arch/x86/lib/cmpxchg8b_emu.S index 1c96be769adc..4bc06bd1aee1 100644 --- a/arch/x86/lib/cmpxchg8b_emu.S +++ b/arch/x86/lib/cmpxchg8b_emu.S @@ -7,7 +7,7 @@ =20 .text =20 -#ifndef CONFIG_X86_CMPXCHG64 +#ifndef CONFIG_X86_REQUIRED_FEATURE_CX8 =20 /* * Emulate 'cmpxchg8b (%esi)' on UP diff --git a/lib/atomic64_test.c b/lib/atomic64_test.c index 759ea1783cc5..c85e8ab3f67d 100644 --- a/lib/atomic64_test.c +++ b/lib/atomic64_test.c @@ -254,7 +254,7 @@ static __init int test_atomics_init(void) pr_info("passed for %s platform %s CX8 and %s SSE\n", #ifdef CONFIG_X86_64 "x86-64", -#elif defined(CONFIG_X86_CMPXCHG64) +#elif defined(CONFIG_X86_REQUIRED_FEATURE_CX8) "i586+", #else "i386+", diff --git a/tools/arch/x86/include/asm/required-features.h b/tools/arch/x8= 6/include/asm/required-features.h index e9187ddd3d1f..cef8104c103c 100644 --- a/tools/arch/x86/include/asm/required-features.h +++ b/tools/arch/x86/include/asm/required-features.h @@ -23,13 +23,13 @@ # define NEED_PAE 0 #endif =20 -#ifdef CONFIG_X86_CMPXCHG64 +#ifdef CONFIG_X86_REQUIRED_FEATURE_CX8 # define NEED_CX8 (1<<(X86_FEATURE_CX8 & 31)) #else # define NEED_CX8 0 #endif =20 -#if defined(CONFIG_X86_CMOV) || defined(CONFIG_X86_64) +#if defined(CONFIG_X86_REQUIRED_FEATURE_CMOV) || defined(CONFIG_X86_64) # define NEED_CMOV (1<<(X86_FEATURE_CMOV & 31)) #else # define NEED_CMOV 0 --=20 2.47.1 From nobody Tue Feb 10 20:06:05 2026 Received: from terminus.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D2F51D86F6; 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charset="utf-8" From: "H. Peter Anvin (Intel)" Introduce an AWK script to auto-generate a header with required and disabled feature masks based on and current build config. Thus for any CPU feature with a build config, e.g., X86_FRED, simply add config X86_DISABLED_FEATURE_FRED def_bool y depends on !X86_FRED to arch/x86/Kconfig.cpufeatures, instead of adding a conditional CPU feature disable flag, e.g., DISABLE_FRED. Lastly the generated required and disabled feature masks will be added to their corresponding feature masks for this particular compile-time configuration. [ Xin: build integration improvements ] Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li (Intel) Reviewed-by: Nikolay Borisov --- Change since v4: * More polishes (Nikolay Borisov). Changes since v3: * Add a few high-level comments to the AWK script (Nikolay Borisov). * Enforce CPU feature mask values to be unsigned. Changes since v2: * Remove AWK code that generates extra debugging comments (Brian Gerst). * Move SSE_MASK to verify_cpu.S, the only place it is used (Brian Gerst). Change since v1: * Remove code generating unused macros {REQUIRED,DISABLED}_FEATURE(x) to tell if a CPU feature, e.g., X86_FEATURE_FRED, is a required or disabled feature for this particular compile-time configuration. --- arch/x86/Makefile | 17 ++++++- arch/x86/boot/cpucheck.c | 3 +- arch/x86/boot/cpuflags.c | 1 - arch/x86/boot/mkcpustr.c | 3 +- arch/x86/include/asm/Kbuild | 1 + arch/x86/include/asm/cpufeature.h | 1 + arch/x86/include/asm/cpufeatures.h | 8 --- arch/x86/kernel/verify_cpu.S | 4 ++ arch/x86/tools/featuremasks.awk | 81 ++++++++++++++++++++++++++++++ 9 files changed, 105 insertions(+), 14 deletions(-) create mode 100755 arch/x86/tools/featuremasks.awk diff --git a/arch/x86/Makefile b/arch/x86/Makefile index 5b773b34768d..a7c58dabf086 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -271,9 +271,22 @@ archscripts: scripts_basic $(Q)$(MAKE) $(build)=3Darch/x86/tools relocs =20 ### -# Syscall table generation +# Feature masks header and syscall table generation =20 -archheaders: +out :=3D arch/x86/include/generated/asm +featuremasks_hdr :=3D featuremasks.h +featuremasks_awk :=3D $(srctree)/arch/x86/tools/featuremasks.awk +cpufeatures_hdr :=3D $(srctree)/arch/x86/include/asm/cpufeatures.h +quiet_cmd_gen_featuremasks =3D GEN $@ + cmd_gen_featuremasks =3D $(AWK) -f $(featuremasks_awk) $(cpufeatures= _hdr) $(KCONFIG_CONFIG) > $@ + +$(out)/$(featuremasks_hdr): $(featuremasks_awk) $(cpufeatures_hdr) $(KCONF= IG_CONFIG) FORCE + $(shell mkdir -p $(out)) + $(call if_changed,gen_featuremasks) + +targets +=3D $(out)/$(featuremasks_hdr) + +archheaders: $(out)/$(featuremasks_hdr) $(Q)$(MAKE) $(build)=3Darch/x86/entry/syscalls all =20 ### diff --git a/arch/x86/boot/cpucheck.c b/arch/x86/boot/cpucheck.c index 0aae4d4ed615..8d03a741d1b2 100644 --- a/arch/x86/boot/cpucheck.c +++ b/arch/x86/boot/cpucheck.c @@ -22,10 +22,11 @@ # include "boot.h" #endif #include +#include #include #include -#include #include + #include "string.h" #include "msr.h" =20 diff --git a/arch/x86/boot/cpuflags.c b/arch/x86/boot/cpuflags.c index d75237ba7ce9..0cabdacb2a2f 100644 --- a/arch/x86/boot/cpuflags.c +++ b/arch/x86/boot/cpuflags.c @@ -3,7 +3,6 @@ #include "bitops.h" =20 #include -#include #include #include "cpuflags.h" =20 diff --git a/arch/x86/boot/mkcpustr.c b/arch/x86/boot/mkcpustr.c index da0ccc5de538..b90110109675 100644 --- a/arch/x86/boot/mkcpustr.c +++ b/arch/x86/boot/mkcpustr.c @@ -12,8 +12,6 @@ =20 #include =20 -#include "../include/asm/required-features.h" -#include "../include/asm/disabled-features.h" #include "../include/asm/cpufeatures.h" #include "../include/asm/vmxfeatures.h" #include "../kernel/cpu/capflags.c" @@ -23,6 +21,7 @@ int main(void) int i, j; const char *str; =20 + printf("#include \n\n"); printf("static const char x86_cap_strs[] =3D\n"); =20 for (i =3D 0; i < NCAPINTS; i++) { diff --git a/arch/x86/include/asm/Kbuild b/arch/x86/include/asm/Kbuild index 6c23d1661b17..16944892d5ee 100644 --- a/arch/x86/include/asm/Kbuild +++ b/arch/x86/include/asm/Kbuild @@ -8,6 +8,7 @@ generated-y +=3D syscalls_x32.h generated-y +=3D unistd_32_ia32.h generated-y +=3D unistd_64_x32.h generated-y +=3D xen-hypercalls.h +generated-y +=3D featuremasks.h =20 generic-y +=3D early_ioremap.h generic-y +=3D mcs_spinlock.h diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufe= ature.h index de1ad09fe8d7..077a5bbd1cc5 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -9,6 +9,7 @@ #include #include #include +#include =20 enum cpuid_leafs { diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 508c0dad116b..d5985e8eef29 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -2,14 +2,6 @@ #ifndef _ASM_X86_CPUFEATURES_H #define _ASM_X86_CPUFEATURES_H =20 -#ifndef _ASM_X86_REQUIRED_FEATURES_H -#include -#endif - -#ifndef _ASM_X86_DISABLED_FEATURES_H -#include -#endif - /* * Defines x86 CPU feature bits */ diff --git a/arch/x86/kernel/verify_cpu.S b/arch/x86/kernel/verify_cpu.S index 1258a5872d12..a23a65d5d177 100644 --- a/arch/x86/kernel/verify_cpu.S +++ b/arch/x86/kernel/verify_cpu.S @@ -29,8 +29,12 @@ */ =20 #include +#include #include =20 +#define SSE_MASK \ + (REQUIRED_MASK0 & ((1<<(X86_FEATURE_XMM & 31)) | (1<<(X86_FEATURE_XMM2 & = 31)))) + SYM_FUNC_START_LOCAL(verify_cpu) pushf # Save caller passed flags push $0 # Kill any dangerous flags diff --git a/arch/x86/tools/featuremasks.awk b/arch/x86/tools/featuremasks.= awk new file mode 100755 index 000000000000..dfac56a697fc --- /dev/null +++ b/arch/x86/tools/featuremasks.awk @@ -0,0 +1,81 @@ +#!/usr/bin/awk +# +# Convert cpufeatures.h to a list of compile-time masks +# Note: this blithly assumes that each word has at least one +# feature defined in it; if not, something else is wrong! +# + +BEGIN { + printf "#ifndef _ASM_X86_FEATUREMASKS_H\n"; + printf "#define _ASM_X86_FEATUREMASKS_H\n\n"; + + file =3D 0 +} + +BEGINFILE { + switch (++file) { + case 1: # cpufeatures.h + FPAT =3D "#[ \t]*[a-z]+|[A-Za-z0-9_]+|[^ \t]"; + break; + case 2: # .config + FPAT =3D "CONFIG_[A-Z0-9_]+|is not set|[yn]"; + break; + } +} + +# Create a dictionary of sorts, containing all defined feature bits +file =3D=3D 1 && $1 ~ /^#[ \t]*define$/ && $2 ~ /^X86_FEATURE_/ && +$3 =3D=3D "(" && $5 =3D=3D "*" && $7 =3D=3D "+" && $9 =3D=3D ")" { + nfeat =3D $4 * $6 + $8; + feat =3D $2; + sub(/^X86_FEATURE_/, "", feat); + feats[nfeat] =3D feat; +} +file =3D=3D 1 && $1 ~ /^#[ \t]*define$/ && $2 =3D=3D "NCAPINTS" { + ncapints =3D strtonum($3); +} + +# Create a dictionary featstat[REQUIRED|DISABLED, FEATURE_NAME] =3D on | o= ff +file =3D=3D 2 && $1 ~ /^CONFIG_X86_[A-Z]*_FEATURE_/ { + on =3D ($2 =3D=3D "y"); + if (split($1, fs, "CONFIG_X86_|_FEATURE_") =3D=3D 3) + featstat[fs[2], fs[3]] =3D on; +} + +END { + sets[1] =3D "REQUIRED"; + sets[2] =3D "DISABLED"; + + for (ns in sets) { + s =3D sets[ns]; + + printf "/*\n"; + printf " * %s features:\n", s; + printf " *\n"; + fstr =3D ""; + for (i =3D 0; i < ncapints; i++) { + mask =3D 0; + for (j =3D 0; j < 32; j++) { + feat =3D feats[i*32 + j]; + if (featstat[s, feat]) { + nfstr =3D fstr " " feat; + if (length(nfstr) > 72) { + printf " * %s\n", fstr; + nfstr =3D " " feat; + } + fstr =3D nfstr; + mask +=3D (2 ^ j); + } + } + masks[i] =3D mask; + } + printf " * %s\n */\n", fstr; + + for (i =3D 0; i < ncapints; i++) + printf "#define %s_MASK%d\t0x%08xU\n", s, i, masks[i]; + + printf "#define %s_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS !=3D %d)\n\n", = s, ncapints; + } + + printf "#endif /* _ASM_X86_FEATUREMASKS_H */\n"; +} --=20 2.47.1 From nobody Tue Feb 10 20:06:05 2026 Received: from terminus.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4712A1D88CA; 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charset="utf-8" The functionalities of {disabled,required}-features.h are replaced with the auto-generated header cpufeature_masks.h. Thus they are no longer needed. So delete them. None of the macros defined in {disabled,required}-features.h is used in tools, delete them too. Signed-off-by: Xin Li (Intel) --- arch/x86/include/asm/disabled-features.h | 161 ------------------ arch/x86/include/asm/required-features.h | 105 ------------ tools/arch/x86/include/asm/cpufeatures.h | 8 - .../arch/x86/include/asm/disabled-features.h | 161 ------------------ .../arch/x86/include/asm/required-features.h | 105 ------------ tools/perf/check-headers.sh | 2 - 6 files changed, 542 deletions(-) delete mode 100644 arch/x86/include/asm/disabled-features.h delete mode 100644 arch/x86/include/asm/required-features.h delete mode 100644 tools/arch/x86/include/asm/disabled-features.h delete mode 100644 tools/arch/x86/include/asm/required-features.h diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/as= m/disabled-features.h deleted file mode 100644 index c492bdc97b05..000000000000 --- a/arch/x86/include/asm/disabled-features.h +++ /dev/null @@ -1,161 +0,0 @@ -#ifndef _ASM_X86_DISABLED_FEATURES_H -#define _ASM_X86_DISABLED_FEATURES_H - -/* These features, although they might be available in a CPU - * will not be used because the compile options to support - * them are not present. - * - * This code allows them to be checked and disabled at - * compile time without an explicit #ifdef. Use - * cpu_feature_enabled(). - */ - -#ifdef CONFIG_X86_UMIP -# define DISABLE_UMIP 0 -#else -# define DISABLE_UMIP (1<<(X86_FEATURE_UMIP & 31)) -#endif - -#ifdef CONFIG_X86_64 -# define DISABLE_VME (1<<(X86_FEATURE_VME & 31)) -# define DISABLE_K6_MTRR (1<<(X86_FEATURE_K6_MTRR & 31)) -# define DISABLE_CYRIX_ARR (1<<(X86_FEATURE_CYRIX_ARR & 31)) -# define DISABLE_CENTAUR_MCR (1<<(X86_FEATURE_CENTAUR_MCR & 31)) -# define DISABLE_PCID 0 -#else -# define DISABLE_VME 0 -# define DISABLE_K6_MTRR 0 -# define DISABLE_CYRIX_ARR 0 -# define DISABLE_CENTAUR_MCR 0 -# define DISABLE_PCID (1<<(X86_FEATURE_PCID & 31)) -#endif /* CONFIG_X86_64 */ - -#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS -# define DISABLE_PKU 0 -# define DISABLE_OSPKE 0 -#else -# define DISABLE_PKU (1<<(X86_FEATURE_PKU & 31)) -# define DISABLE_OSPKE (1<<(X86_FEATURE_OSPKE & 31)) -#endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */ - -#ifdef CONFIG_X86_5LEVEL -# define DISABLE_LA57 0 -#else -# define DISABLE_LA57 (1<<(X86_FEATURE_LA57 & 31)) -#endif - -#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION -# define DISABLE_PTI 0 -#else -# define DISABLE_PTI (1 << (X86_FEATURE_PTI & 31)) -#endif - -#ifdef CONFIG_MITIGATION_RETPOLINE -# define DISABLE_RETPOLINE 0 -#else -# define DISABLE_RETPOLINE ((1 << (X86_FEATURE_RETPOLINE & 31)) | \ - (1 << (X86_FEATURE_RETPOLINE_LFENCE & 31))) -#endif - -#ifdef CONFIG_MITIGATION_RETHUNK -# define DISABLE_RETHUNK 0 -#else -# define DISABLE_RETHUNK (1 << (X86_FEATURE_RETHUNK & 31)) -#endif - -#ifdef CONFIG_MITIGATION_UNRET_ENTRY -# define DISABLE_UNRET 0 -#else -# define DISABLE_UNRET (1 << (X86_FEATURE_UNRET & 31)) -#endif - -#ifdef CONFIG_MITIGATION_CALL_DEPTH_TRACKING -# define DISABLE_CALL_DEPTH_TRACKING 0 -#else -# define DISABLE_CALL_DEPTH_TRACKING (1 << (X86_FEATURE_CALL_DEPTH & 31)) -#endif - -#ifdef CONFIG_ADDRESS_MASKING -# define DISABLE_LAM 0 -#else -# define DISABLE_LAM (1 << (X86_FEATURE_LAM & 31)) -#endif - -#ifdef CONFIG_INTEL_IOMMU_SVM -# define DISABLE_ENQCMD 0 -#else -# define DISABLE_ENQCMD (1 << (X86_FEATURE_ENQCMD & 31)) -#endif - -#ifdef CONFIG_X86_SGX -# define DISABLE_SGX 0 -#else -# define DISABLE_SGX (1 << (X86_FEATURE_SGX & 31)) -#endif - -#ifdef CONFIG_XEN_PV -# define DISABLE_XENPV 0 -#else -# define DISABLE_XENPV (1 << (X86_FEATURE_XENPV & 31)) -#endif - -#ifdef CONFIG_INTEL_TDX_GUEST -# define DISABLE_TDX_GUEST 0 -#else -# define DISABLE_TDX_GUEST (1 << (X86_FEATURE_TDX_GUEST & 31)) -#endif - -#ifdef CONFIG_X86_USER_SHADOW_STACK -#define DISABLE_USER_SHSTK 0 -#else -#define DISABLE_USER_SHSTK (1 << (X86_FEATURE_USER_SHSTK & 31)) -#endif - -#ifdef CONFIG_X86_KERNEL_IBT -#define DISABLE_IBT 0 -#else -#define DISABLE_IBT (1 << (X86_FEATURE_IBT & 31)) -#endif - -#ifdef CONFIG_X86_FRED -# define DISABLE_FRED 0 -#else -# define DISABLE_FRED (1 << (X86_FEATURE_FRED & 31)) -#endif - -#ifdef CONFIG_KVM_AMD_SEV -#define DISABLE_SEV_SNP 0 -#else -#define DISABLE_SEV_SNP (1 << (X86_FEATURE_SEV_SNP & 31)) -#endif - -/* - * Make sure to add features to the correct mask - */ -#define DISABLED_MASK0 (DISABLE_VME) -#define DISABLED_MASK1 0 -#define DISABLED_MASK2 0 -#define DISABLED_MASK3 (DISABLE_CYRIX_ARR|DISABLE_CENTAUR_MCR|DISABLE_K6_M= TRR) -#define DISABLED_MASK4 (DISABLE_PCID) -#define DISABLED_MASK5 0 -#define DISABLED_MASK6 0 -#define DISABLED_MASK7 (DISABLE_PTI) -#define DISABLED_MASK8 (DISABLE_XENPV|DISABLE_TDX_GUEST) -#define DISABLED_MASK9 (DISABLE_SGX) -#define DISABLED_MASK10 0 -#define DISABLED_MASK11 (DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET| \ - DISABLE_CALL_DEPTH_TRACKING|DISABLE_USER_SHSTK) -#define DISABLED_MASK12 (DISABLE_FRED|DISABLE_LAM) -#define DISABLED_MASK13 0 -#define DISABLED_MASK14 0 -#define DISABLED_MASK15 0 -#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UM= IP| \ - DISABLE_ENQCMD) -#define DISABLED_MASK17 0 -#define DISABLED_MASK18 (DISABLE_IBT) -#define DISABLED_MASK19 (DISABLE_SEV_SNP) -#define DISABLED_MASK20 0 -#define DISABLED_MASK21 0 -#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS !=3D 22) - -#endif /* _ASM_X86_DISABLED_FEATURES_H */ diff --git a/arch/x86/include/asm/required-features.h b/arch/x86/include/as= m/required-features.h deleted file mode 100644 index cef8104c103c..000000000000 --- a/arch/x86/include/asm/required-features.h +++ /dev/null @@ -1,105 +0,0 @@ -#ifndef _ASM_X86_REQUIRED_FEATURES_H -#define _ASM_X86_REQUIRED_FEATURES_H - -/* Define minimum CPUID feature set for kernel These bits are checked - really early to actually display a visible error message before the - kernel dies. Make sure to assign features to the proper mask! - - Some requirements that are not in CPUID yet are also in the - CONFIG_X86_MINIMUM_CPU_FAMILY which is checked too. - - The real information is in arch/x86/Kconfig.cpu, this just converts - the CONFIGs into a bitmask */ - -#ifndef CONFIG_MATH_EMULATION -# define NEED_FPU (1<<(X86_FEATURE_FPU & 31)) -#else -# define NEED_FPU 0 -#endif - -#if defined(CONFIG_X86_PAE) || defined(CONFIG_X86_64) -# define NEED_PAE (1<<(X86_FEATURE_PAE & 31)) -#else -# define NEED_PAE 0 -#endif - -#ifdef CONFIG_X86_REQUIRED_FEATURE_CX8 -# define NEED_CX8 (1<<(X86_FEATURE_CX8 & 31)) -#else -# define NEED_CX8 0 -#endif - -#if defined(CONFIG_X86_REQUIRED_FEATURE_CMOV) || defined(CONFIG_X86_64) -# define NEED_CMOV (1<<(X86_FEATURE_CMOV & 31)) -#else -# define NEED_CMOV 0 -#endif - -# define NEED_3DNOW 0 - -#if defined(CONFIG_X86_P6_NOP) || defined(CONFIG_X86_64) -# define NEED_NOPL (1<<(X86_FEATURE_NOPL & 31)) -#else -# define NEED_NOPL 0 -#endif - -#ifdef CONFIG_MATOM -# define NEED_MOVBE (1<<(X86_FEATURE_MOVBE & 31)) -#else -# define NEED_MOVBE 0 -#endif - -#ifdef CONFIG_X86_64 -#ifdef CONFIG_PARAVIRT_XXL -/* Paravirtualized systems may not have PSE or PGE available */ -#define NEED_PSE 0 -#define NEED_PGE 0 -#else -#define NEED_PSE (1<<(X86_FEATURE_PSE) & 31) -#define NEED_PGE (1<<(X86_FEATURE_PGE) & 31) -#endif -#define NEED_MSR (1<<(X86_FEATURE_MSR & 31)) -#define NEED_FXSR (1<<(X86_FEATURE_FXSR & 31)) -#define NEED_XMM (1<<(X86_FEATURE_XMM & 31)) -#define NEED_XMM2 (1<<(X86_FEATURE_XMM2 & 31)) -#define NEED_LM (1<<(X86_FEATURE_LM & 31)) -#else -#define NEED_PSE 0 -#define NEED_MSR 0 -#define NEED_PGE 0 -#define NEED_FXSR 0 -#define NEED_XMM 0 -#define NEED_XMM2 0 -#define NEED_LM 0 -#endif - -#define REQUIRED_MASK0 (NEED_FPU|NEED_PSE|NEED_MSR|NEED_PAE|\ - NEED_CX8|NEED_PGE|NEED_FXSR|NEED_CMOV|\ - NEED_XMM|NEED_XMM2) -#define SSE_MASK (NEED_XMM|NEED_XMM2) - -#define REQUIRED_MASK1 (NEED_LM|NEED_3DNOW) - -#define REQUIRED_MASK2 0 -#define REQUIRED_MASK3 (NEED_NOPL) -#define REQUIRED_MASK4 (NEED_MOVBE) -#define REQUIRED_MASK5 0 -#define REQUIRED_MASK6 0 -#define REQUIRED_MASK7 0 -#define REQUIRED_MASK8 0 -#define REQUIRED_MASK9 0 -#define REQUIRED_MASK10 0 -#define REQUIRED_MASK11 0 -#define REQUIRED_MASK12 0 -#define REQUIRED_MASK13 0 -#define REQUIRED_MASK14 0 -#define REQUIRED_MASK15 0 -#define REQUIRED_MASK16 0 -#define REQUIRED_MASK17 0 -#define REQUIRED_MASK18 0 -#define REQUIRED_MASK19 0 -#define REQUIRED_MASK20 0 -#define REQUIRED_MASK21 0 -#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS !=3D 22) - -#endif /* _ASM_X86_REQUIRED_FEATURES_H */ diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/incl= ude/asm/cpufeatures.h index 17b6590748c0..c691481d59ce 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -2,14 +2,6 @@ #ifndef _ASM_X86_CPUFEATURES_H #define _ASM_X86_CPUFEATURES_H =20 -#ifndef _ASM_X86_REQUIRED_FEATURES_H -#include -#endif - -#ifndef _ASM_X86_DISABLED_FEATURES_H -#include -#endif - /* * Defines x86 CPU feature bits */ diff --git a/tools/arch/x86/include/asm/disabled-features.h b/tools/arch/x8= 6/include/asm/disabled-features.h deleted file mode 100644 index c492bdc97b05..000000000000 --- a/tools/arch/x86/include/asm/disabled-features.h +++ /dev/null @@ -1,161 +0,0 @@ -#ifndef _ASM_X86_DISABLED_FEATURES_H -#define _ASM_X86_DISABLED_FEATURES_H - -/* These features, although they might be available in a CPU - * will not be used because the compile options to support - * them are not present. - * - * This code allows them to be checked and disabled at - * compile time without an explicit #ifdef. Use - * cpu_feature_enabled(). - */ - -#ifdef CONFIG_X86_UMIP -# define DISABLE_UMIP 0 -#else -# define DISABLE_UMIP (1<<(X86_FEATURE_UMIP & 31)) -#endif - -#ifdef CONFIG_X86_64 -# define DISABLE_VME (1<<(X86_FEATURE_VME & 31)) -# define DISABLE_K6_MTRR (1<<(X86_FEATURE_K6_MTRR & 31)) -# define DISABLE_CYRIX_ARR (1<<(X86_FEATURE_CYRIX_ARR & 31)) -# define DISABLE_CENTAUR_MCR (1<<(X86_FEATURE_CENTAUR_MCR & 31)) -# define DISABLE_PCID 0 -#else -# define DISABLE_VME 0 -# define DISABLE_K6_MTRR 0 -# define DISABLE_CYRIX_ARR 0 -# define DISABLE_CENTAUR_MCR 0 -# define DISABLE_PCID (1<<(X86_FEATURE_PCID & 31)) -#endif /* CONFIG_X86_64 */ - -#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS -# define DISABLE_PKU 0 -# define DISABLE_OSPKE 0 -#else -# define DISABLE_PKU (1<<(X86_FEATURE_PKU & 31)) -# define DISABLE_OSPKE (1<<(X86_FEATURE_OSPKE & 31)) -#endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */ - -#ifdef CONFIG_X86_5LEVEL -# define DISABLE_LA57 0 -#else -# define DISABLE_LA57 (1<<(X86_FEATURE_LA57 & 31)) -#endif - -#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION -# define DISABLE_PTI 0 -#else -# define DISABLE_PTI (1 << (X86_FEATURE_PTI & 31)) -#endif - -#ifdef CONFIG_MITIGATION_RETPOLINE -# define DISABLE_RETPOLINE 0 -#else -# define DISABLE_RETPOLINE ((1 << (X86_FEATURE_RETPOLINE & 31)) | \ - (1 << (X86_FEATURE_RETPOLINE_LFENCE & 31))) -#endif - -#ifdef CONFIG_MITIGATION_RETHUNK -# define DISABLE_RETHUNK 0 -#else -# define DISABLE_RETHUNK (1 << (X86_FEATURE_RETHUNK & 31)) -#endif - -#ifdef CONFIG_MITIGATION_UNRET_ENTRY -# define DISABLE_UNRET 0 -#else -# define DISABLE_UNRET (1 << (X86_FEATURE_UNRET & 31)) -#endif - -#ifdef CONFIG_MITIGATION_CALL_DEPTH_TRACKING -# define DISABLE_CALL_DEPTH_TRACKING 0 -#else -# define DISABLE_CALL_DEPTH_TRACKING (1 << (X86_FEATURE_CALL_DEPTH & 31)) -#endif - -#ifdef CONFIG_ADDRESS_MASKING -# define DISABLE_LAM 0 -#else -# define DISABLE_LAM (1 << (X86_FEATURE_LAM & 31)) -#endif - -#ifdef CONFIG_INTEL_IOMMU_SVM -# define DISABLE_ENQCMD 0 -#else -# define DISABLE_ENQCMD (1 << (X86_FEATURE_ENQCMD & 31)) -#endif - -#ifdef CONFIG_X86_SGX -# define DISABLE_SGX 0 -#else -# define DISABLE_SGX (1 << (X86_FEATURE_SGX & 31)) -#endif - -#ifdef CONFIG_XEN_PV -# define DISABLE_XENPV 0 -#else -# define DISABLE_XENPV (1 << (X86_FEATURE_XENPV & 31)) -#endif - -#ifdef CONFIG_INTEL_TDX_GUEST -# define DISABLE_TDX_GUEST 0 -#else -# define DISABLE_TDX_GUEST (1 << (X86_FEATURE_TDX_GUEST & 31)) -#endif - -#ifdef CONFIG_X86_USER_SHADOW_STACK -#define DISABLE_USER_SHSTK 0 -#else -#define DISABLE_USER_SHSTK (1 << (X86_FEATURE_USER_SHSTK & 31)) -#endif - -#ifdef CONFIG_X86_KERNEL_IBT -#define DISABLE_IBT 0 -#else -#define DISABLE_IBT (1 << (X86_FEATURE_IBT & 31)) -#endif - -#ifdef CONFIG_X86_FRED -# define DISABLE_FRED 0 -#else -# define DISABLE_FRED (1 << (X86_FEATURE_FRED & 31)) -#endif - -#ifdef CONFIG_KVM_AMD_SEV -#define DISABLE_SEV_SNP 0 -#else -#define DISABLE_SEV_SNP (1 << (X86_FEATURE_SEV_SNP & 31)) -#endif - -/* - * Make sure to add features to the correct mask - */ -#define DISABLED_MASK0 (DISABLE_VME) -#define DISABLED_MASK1 0 -#define DISABLED_MASK2 0 -#define DISABLED_MASK3 (DISABLE_CYRIX_ARR|DISABLE_CENTAUR_MCR|DISABLE_K6_M= TRR) -#define DISABLED_MASK4 (DISABLE_PCID) -#define DISABLED_MASK5 0 -#define DISABLED_MASK6 0 -#define DISABLED_MASK7 (DISABLE_PTI) -#define DISABLED_MASK8 (DISABLE_XENPV|DISABLE_TDX_GUEST) -#define DISABLED_MASK9 (DISABLE_SGX) -#define DISABLED_MASK10 0 -#define DISABLED_MASK11 (DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET| \ - DISABLE_CALL_DEPTH_TRACKING|DISABLE_USER_SHSTK) -#define DISABLED_MASK12 (DISABLE_FRED|DISABLE_LAM) -#define DISABLED_MASK13 0 -#define DISABLED_MASK14 0 -#define DISABLED_MASK15 0 -#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UM= IP| \ - DISABLE_ENQCMD) -#define DISABLED_MASK17 0 -#define DISABLED_MASK18 (DISABLE_IBT) -#define DISABLED_MASK19 (DISABLE_SEV_SNP) -#define DISABLED_MASK20 0 -#define DISABLED_MASK21 0 -#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS !=3D 22) - -#endif /* _ASM_X86_DISABLED_FEATURES_H */ diff --git a/tools/arch/x86/include/asm/required-features.h b/tools/arch/x8= 6/include/asm/required-features.h deleted file mode 100644 index cef8104c103c..000000000000 --- a/tools/arch/x86/include/asm/required-features.h +++ /dev/null @@ -1,105 +0,0 @@ -#ifndef _ASM_X86_REQUIRED_FEATURES_H -#define _ASM_X86_REQUIRED_FEATURES_H - -/* Define minimum CPUID feature set for kernel These bits are checked - really early to actually display a visible error message before the - kernel dies. Make sure to assign features to the proper mask! - - Some requirements that are not in CPUID yet are also in the - CONFIG_X86_MINIMUM_CPU_FAMILY which is checked too. - - The real information is in arch/x86/Kconfig.cpu, this just converts - the CONFIGs into a bitmask */ - -#ifndef CONFIG_MATH_EMULATION -# define NEED_FPU (1<<(X86_FEATURE_FPU & 31)) -#else -# define NEED_FPU 0 -#endif - -#if defined(CONFIG_X86_PAE) || defined(CONFIG_X86_64) -# define NEED_PAE (1<<(X86_FEATURE_PAE & 31)) -#else -# define NEED_PAE 0 -#endif - -#ifdef CONFIG_X86_REQUIRED_FEATURE_CX8 -# define NEED_CX8 (1<<(X86_FEATURE_CX8 & 31)) -#else -# define NEED_CX8 0 -#endif - -#if defined(CONFIG_X86_REQUIRED_FEATURE_CMOV) || defined(CONFIG_X86_64) -# define NEED_CMOV (1<<(X86_FEATURE_CMOV & 31)) -#else -# define NEED_CMOV 0 -#endif - -# define NEED_3DNOW 0 - -#if defined(CONFIG_X86_P6_NOP) || defined(CONFIG_X86_64) -# define NEED_NOPL (1<<(X86_FEATURE_NOPL & 31)) -#else -# define NEED_NOPL 0 -#endif - -#ifdef CONFIG_MATOM -# define NEED_MOVBE (1<<(X86_FEATURE_MOVBE & 31)) -#else -# define NEED_MOVBE 0 -#endif - -#ifdef CONFIG_X86_64 -#ifdef CONFIG_PARAVIRT_XXL -/* Paravirtualized systems may not have PSE or PGE available */ -#define NEED_PSE 0 -#define NEED_PGE 0 -#else -#define NEED_PSE (1<<(X86_FEATURE_PSE) & 31) -#define NEED_PGE (1<<(X86_FEATURE_PGE) & 31) -#endif -#define NEED_MSR (1<<(X86_FEATURE_MSR & 31)) -#define NEED_FXSR (1<<(X86_FEATURE_FXSR & 31)) -#define NEED_XMM (1<<(X86_FEATURE_XMM & 31)) -#define NEED_XMM2 (1<<(X86_FEATURE_XMM2 & 31)) -#define NEED_LM (1<<(X86_FEATURE_LM & 31)) -#else -#define NEED_PSE 0 -#define NEED_MSR 0 -#define NEED_PGE 0 -#define NEED_FXSR 0 -#define NEED_XMM 0 -#define NEED_XMM2 0 -#define NEED_LM 0 -#endif - -#define REQUIRED_MASK0 (NEED_FPU|NEED_PSE|NEED_MSR|NEED_PAE|\ - NEED_CX8|NEED_PGE|NEED_FXSR|NEED_CMOV|\ - NEED_XMM|NEED_XMM2) -#define SSE_MASK (NEED_XMM|NEED_XMM2) - -#define REQUIRED_MASK1 (NEED_LM|NEED_3DNOW) - -#define REQUIRED_MASK2 0 -#define REQUIRED_MASK3 (NEED_NOPL) -#define REQUIRED_MASK4 (NEED_MOVBE) -#define REQUIRED_MASK5 0 -#define REQUIRED_MASK6 0 -#define REQUIRED_MASK7 0 -#define REQUIRED_MASK8 0 -#define REQUIRED_MASK9 0 -#define REQUIRED_MASK10 0 -#define REQUIRED_MASK11 0 -#define REQUIRED_MASK12 0 -#define REQUIRED_MASK13 0 -#define REQUIRED_MASK14 0 -#define REQUIRED_MASK15 0 -#define REQUIRED_MASK16 0 -#define REQUIRED_MASK17 0 -#define REQUIRED_MASK18 0 -#define REQUIRED_MASK19 0 -#define REQUIRED_MASK20 0 -#define REQUIRED_MASK21 0 -#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS !=3D 22) - -#endif /* _ASM_X86_REQUIRED_FEATURES_H */ diff --git a/tools/perf/check-headers.sh b/tools/perf/check-headers.sh index a05c1c105c51..67d4e9fc4d36 100755 --- a/tools/perf/check-headers.sh +++ b/tools/perf/check-headers.sh @@ -26,8 +26,6 @@ FILES=3D( "include/linux/hash.h" "include/linux/list-sort.h" "include/uapi/linux/hw_breakpoint.h" - "arch/x86/include/asm/disabled-features.h" - "arch/x86/include/asm/required-features.h" "arch/x86/include/asm/cpufeatures.h" "arch/x86/include/asm/inat_types.h" "arch/x86/include/asm/emulate_prefix.h" --=20 2.47.1 From nobody Tue Feb 10 20:06:05 2026 Received: from terminus.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 454FB1D6DB7; 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charset="utf-8" Generate macros {REQUIRED|DISABLED}_MASK_BIT_SET in the newly added AWK script that generates the required and disabled feature mask header. Suggested-by: Brian Gerst Signed-off-by: Xin Li (Intel) Reviewed-by: Brian Gerst --- Changes since v3: * Use '1U' instead of '1' in feature mask shifting (Andrew Cooper). * Checking NCAPINTS isn't necessary anymore. It was needed when these macros had to be manually updated, but now if cpufeatures.h changes this header will be regenerated (Brian Gerst). --- arch/x86/include/asm/cpufeature.h | 69 ------------------------------- arch/x86/tools/featuremasks.awk | 9 +++- 2 files changed, 8 insertions(+), 70 deletions(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufe= ature.h index 077a5bbd1cc5..b829a12eda8a 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -55,75 +55,6 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; #define test_cpu_cap(c, bit) \ arch_test_bit(bit, (unsigned long *)((c)->x86_capability)) =20 -/* - * There are 32 bits/features in each mask word. The high bits - * (selected with (bit>>5) give us the word number and the low 5 - * bits give us the bit/feature number inside the word. - * (1UL<<((bit)&31) gives us a mask for the feature_bit so we can - * see if it is set in the mask word. - */ -#define CHECK_BIT_IN_MASK_WORD(maskname, word, bit) \ - (((bit)>>5)=3D=3D(word) && (1UL<<((bit)&31) & maskname##word )) - -/* - * {REQUIRED,DISABLED}_MASK_CHECK below may seem duplicated with the - * following BUILD_BUG_ON_ZERO() check but when NCAPINTS gets changed, all - * header macros which use NCAPINTS need to be changed. The duplicated mac= ro - * use causes the compiler to issue errors for all headers so that all usa= ge - * sites can be corrected. - */ -#define REQUIRED_MASK_BIT_SET(feature_bit) \ - ( CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 0, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 1, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 2, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 3, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 4, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 5, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 6, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 7, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 8, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 9, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 10, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 11, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 12, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 13, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 14, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 15, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 16, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 19, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 20, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 21, feature_bit) || \ - REQUIRED_MASK_CHECK || \ - BUILD_BUG_ON_ZERO(NCAPINTS !=3D 22)) - -#define DISABLED_MASK_BIT_SET(feature_bit) \ - ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 0, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 1, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 2, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 3, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 4, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 5, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 6, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 7, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 8, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 9, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 10, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 11, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 12, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 13, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 14, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 15, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 16, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 19, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 20, feature_bit) || \ - CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 21, feature_bit) || \ - DISABLED_MASK_CHECK || \ - BUILD_BUG_ON_ZERO(NCAPINTS !=3D 22)) - #define cpu_has(c, bit) \ (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ test_cpu_cap(c, bit)) diff --git a/arch/x86/tools/featuremasks.awk b/arch/x86/tools/featuremasks.= awk index dfac56a697fc..01e47b31e187 100755 --- a/arch/x86/tools/featuremasks.awk +++ b/arch/x86/tools/featuremasks.awk @@ -74,7 +74,14 @@ END { for (i =3D 0; i < ncapints; i++) printf "#define %s_MASK%d\t0x%08xU\n", s, i, masks[i]; =20 - printf "#define %s_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS !=3D %d)\n\n", = s, ncapints; + printf "\n#define %s_MASK_BIT_SET(x)\t\t\t\\\n", s; + printf "\t((\t\t\t\t\t"; + for (i =3D 0; i < ncapints; i++) { + if (masks[i]) + printf "\t\\\n\t\t((x) >> 5) =3D=3D %2d ? %s_MASK%d :", i, s, i; + } + printf " 0\t\\\n"; + printf "\t) & (1U << ((x) & 31)))\n\n"; } =20 printf "#endif /* _ASM_X86_FEATUREMASKS_H */\n"; --=20 2.47.1 From nobody Tue Feb 10 20:06:05 2026 Received: from terminus.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48EAC7603F; Mon, 6 Jan 2025 07:11:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736147476; cv=none; b=nlr+rT4KBiEvg3BVxluTQRqdUrJp0yrzQN4IW5H7AXX+vYl9oxauEpnKDCwN2n5rYZ3n0CrrY1NLHPKXlxIEcthnlZBa3LsdzBaT4kSlz/miQIeilqRaJe4T0RKEGJpO6Fjg+MlgkzYwc8PuskDXvuqH76QDHOctdYiD4QdaJWQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736147476; c=relaxed/simple; bh=vURgG34GrHdYjB3buk5HlnegJCTaxHYf/0eFMWCO8VY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GoZX8jR3DMchrv0CrIf90tM1LYnmSrPRsPoIIzgBruhEBO+GRWnwLFdQ6W6EuhittLB03SgEjENQky9J1eNvn0juBuzfKDeWQszjZwiiM0hoq7YyAMtNxqEq90Ni08dndXT9s3EjRHL2GgrIJ02K90X/dSvLbsjJ/0KNo6nNtpo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com; spf=pass smtp.mailfrom=zytor.com; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b=iqOwybmd; arc=none smtp.client-ip=198.137.202.136 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zytor.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b="iqOwybmd" Received: from terminus.zytor.com (terminus.zytor.com [IPv6:2607:7c80:54:3:0:0:0:136]) (authenticated bits=0) by mail.zytor.com (8.18.1/8.17.1) with ESMTPSA id 50677RpE3211026 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO); Sun, 5 Jan 2025 23:07:37 -0800 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 50677RpE3211026 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2024121701; t=1736147258; bh=Re3MfHtuLBMHpeFVMue+szaKAp0SHaPCUZaQZ+mtJkU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iqOwybmdV2PNIuYs7/ayZms6/Pm/dBp8Tr0tFnD+zBzeixMvuzn5irzOsCtkUq6Sl Pd6JXuoT9UVNM9AirliJcuet6j4PonWCbvE00g6TFhGwwR7hIQGt3gZygXNvFIOp8y iZhwEkfQ6G83sd/eVvHTyLUVA3qMtQNsGOjCes1mkfStr4JQC/gmz2R5nOcz5DtU7A hKzH877fPowLTCULFLB8vlSkVtvwb3AKaoHwwwEUV7Yi0MGDKxfDjLmyH9k2h169eK MLS8v6hzMh7/w0QL8AQb6YR4Rehqz5TeZQt04rkWrzHvYEH86qJLEa3Jr72aA9bd6n ghlrtXLfKVoQA== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, will@kernel.org, peterz@infradead.org, yury.norov@gmail.com, akpm@linux-foundation.org, acme@kernel.org, namhyung@kernel.org, brgerst@gmail.com, andrew.cooper3@citrix.com, nik.borisov@suse.com Subject: [PATCH v5 5/5] x86/cpufeatures: Add the CPU feature bit for MSR immediate form instructions Date: Sun, 5 Jan 2025 23:07:27 -0800 Message-ID: <20250106070727.3211006-6-xin@zytor.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250106070727.3211006-1-xin@zytor.com> References: <20250106070727.3211006-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The immediate form of MSR access instructions are primarily motivated by performance, not code size: by having the MSR number in an immediate, it is available *much* earlier in the pipeline, which allows the hardware much more leeway about how a particular MSR is handled. Add a new CPU feature word for CPUID.7.1.ECX and then the CPU feature bit for MSR immediate form. Signed-off-by: Xin Li (Intel) --- arch/x86/include/asm/cpufeature.h | 1 + arch/x86/include/asm/cpufeatures.h | 5 ++++- arch/x86/kernel/cpu/common.c | 1 + 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufe= ature.h index b829a12eda8a..9a2991e7b21b 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -35,6 +35,7 @@ enum cpuid_leafs CPUID_8000_001F_EAX, CPUID_8000_0021_EAX, CPUID_LNX_5, + CPUID_7_1_ECX, NR_CPUID_WORDS, }; =20 diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index d5985e8eef29..59aa04915032 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -5,7 +5,7 @@ /* * Defines x86 CPU feature bits */ -#define NCAPINTS 22 /* N 32-bit words worth of info */ +#define NCAPINTS 23 /* N 32-bit words worth of info */ #define NBUGINTS 2 /* N 32-bit bug flags */ =20 /* @@ -476,6 +476,9 @@ #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous C= ore Topology */ #define X86_FEATURE_AMD_WORKLOAD_CLASS (21*32 + 7) /* Workload Classificat= ion */ =20 +/* Intel-defined CPU features, CPUID level 0x00000007:1 (ECX), word 22 */ +#define X86_FEATURE_MSR_IMM (22*32+ 5) /* "msr_imm" MSR immediate form in= structions */ + /* * BUG word(s) */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 7cce91b19fb2..13d270eabd09 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -997,6 +997,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c) if (eax >=3D 1) { cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); c->x86_capability[CPUID_7_1_EAX] =3D eax; + c->x86_capability[CPUID_7_1_ECX] =3D ecx; } } =20 --=20 2.47.1