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Mon, 06 Jan 2025 05:44:43 -0800 (PST) From: Krzysztof Kozlowski Date: Mon, 06 Jan 2025 14:44:30 +0100 Subject: [PATCH v2 2/3] clk: qcom: clk-alpha-pll: Add Pongo PLL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250106-sm8750-dispcc-v2-2-6f42beda6317@linaro.org> References: <20250106-sm8750-dispcc-v2-0-6f42beda6317@linaro.org> In-Reply-To: <20250106-sm8750-dispcc-v2-0-6f42beda6317@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10027; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=BuGgxnT8GMf64DMeHuTbpu3NUBH1f3aydDCYK6u6bsA=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBne95Fpn+Mb36A3fYoMGD9W3ROEcr9EkmP0fIt5 OzLMzOXlxWJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ3veRQAKCRDBN2bmhouD 1wvjD/0c0ewfkCZXtzrbzg9sTGFllgttbERhtfKwAiGOF2SiyUWRnpnToU4oTUJ6KgrwMTO25xd gYmAKmlsoDf3u1vP7PpAdlJ16ICdS978e9DuuYV7VB0ESW/xnlzznDUltNPZ4AR0b1JMNrtEB59 hC7CEcFDnuNVwF5Inq5N6szRFIe1OxpFi+0tEW89ygVuDaUZr/0v3Gfp40tWtbxoQxVs3LTO/V8 TGjUupCv643GRezXwBBN5+JOyyGBclXUZVFfUEnMPu2LSqSH+9Qnxz746zB52tirwC6T6qhZqYK +tVIrVQFSDmIMX7w9ItRQNuvc4bG9qqd02z1ILxZwfURE9P/ZmMDHTihpFTqUtF+M12v7Ovg1TD WraJ19Vxi2FIHKSajSeGgQpleM81ksqbWVpa3Hza/T681P24nV5pVz+Bqe2Q56lkUl3CMABaZvE B3P+Pjmy/dHg0gkq+iJYa9RxtZH0W3qs7Bb+/Ys/QSNzX88MtG1X79J8P6ULMwXyXI6dAbPvqdh kzG40stzSOLJqnxeS28TFoJaK7Pw0Xm3SE6Mq6AEOGf4wunU05pv7oTlp+yzt78pqr8/JWxQH1P Fd4espwHyDGBhtHBKO4UcmAiGaPzSGt9p94q1Guqk2nLgKFKO5lKA0ARJ0MocJEY22EIaoQ0Rcl bC35hdj1jcopH5A== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add support for Pongo type of PLL clocks, used in Qualcomm SM8750 SoC. Notable difference comparing to other PLLs is the need for calibration for internally generated clock followed by wait_for_pll(). This is done in configure call and at this time clocks are not yet registered, thus wait_for_pll() cannot use clk_hw_get_name. Locking during this calibration requires much more time, thus increase the timeout in wait_for_pll(). Signed-off-by: Krzysztof Kozlowski --- v2: - EXPORT_SYMBOL_GPL - Move the PLL calibration and wait_for_pll_enable_lock() call to prepare callback. --- drivers/clk/qcom/clk-alpha-pll.c | 165 +++++++++++++++++++++++++++++++++++= +++- drivers/clk/qcom/clk-alpha-pll.h | 6 ++ 2 files changed, 170 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-= pll.c index 00d3659ea2124e26dd50c1b4e88ba71c1411442e..df609f7e394de2dc73e60df01b1= ad71714c0719d 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -58,6 +58,7 @@ #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U= 1]) #define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U= 2]) +#define PLL_TEST_CTL_U3(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U= 3]) #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) @@ -197,6 +198,23 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] =3D { [PLL_OFF_TEST_CTL_U1] =3D 0x34, [PLL_OFF_TEST_CTL_U2] =3D 0x38, }, + [CLK_ALPHA_PLL_TYPE_PONGO_ELU] =3D { + [PLL_OFF_OPMODE] =3D 0x04, + [PLL_OFF_STATE] =3D 0x08, + [PLL_OFF_STATUS] =3D 0x0c, + [PLL_OFF_L_VAL] =3D 0x10, + [PLL_OFF_USER_CTL] =3D 0x14, + [PLL_OFF_USER_CTL_U] =3D 0x18, + [PLL_OFF_CONFIG_CTL] =3D 0x1c, + [PLL_OFF_CONFIG_CTL_U] =3D 0x20, + [PLL_OFF_CONFIG_CTL_U1] =3D 0x24, + [PLL_OFF_CONFIG_CTL_U2] =3D 0x28, + [PLL_OFF_TEST_CTL] =3D 0x2c, + [PLL_OFF_TEST_CTL_U] =3D 0x30, + [PLL_OFF_TEST_CTL_U1] =3D 0x34, + [PLL_OFF_TEST_CTL_U2] =3D 0x38, + [PLL_OFF_TEST_CTL_U3] =3D 0x3c, + }, [CLK_ALPHA_PLL_TYPE_TAYCAN_ELU] =3D { [PLL_OFF_OPMODE] =3D 0x04, [PLL_OFF_STATE] =3D 0x08, @@ -337,6 +355,12 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); #define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16 #define LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT 24 =20 +/* PONGO ELU PLL specific setting and offsets */ +#define PONGO_PLL_OUT_MASK GENMASK(1, 0) +#define PONGO_PLL_L_VAL_MASK GENMASK(11, 0) +#define PONGO_XO_PRESENT BIT(10) +#define PONGO_CLOCK_SELECT BIT(12) + /* ZONDA PLL specific */ #define ZONDA_PLL_OUT_MASK 0xf #define ZONDA_STAY_IN_CFA BIT(16) @@ -366,7 +390,8 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 = mask, bool inverse, if (ret) return ret; =20 - for (count =3D 200; count > 0; count--) { + /* Pongo PLLs using a 32KHz reference can take upwards of 1500us to lock.= */ + for (count =3D 1500; count > 0; count--) { ret =3D regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); if (ret) return ret; @@ -2527,6 +2552,144 @@ const struct clk_ops clk_alpha_pll_reset_lucid_evo_= ops =3D { }; EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops); =20 +static int alpha_pll_pongo_elu_prepare(struct clk_hw *hw) +{ + struct clk_alpha_pll *pll =3D to_clk_alpha_pll(hw); + struct regmap *regmap =3D pll->clkr.regmap; + int ret; + + /* Enable PLL intially to one-time calibrate against XO. */ + regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); + regmap_update_bits(regmap, PLL_MODE(pll), PONGO_XO_PRESENT, PONGO_XO_PRES= ENT); + + /* Set regmap for wait_for_pll() */ + pll->clkr.regmap =3D regmap; + ret =3D wait_for_pll_enable_lock(pll); + if (ret) { + /* Reverse calibration - disable PLL output */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); + return ret; + } + + /* Disable PLL after one-time calibration. */ + regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); + + /* Select internally generated clock. */ + regmap_update_bits(regmap, PLL_MODE(pll), PONGO_CLOCK_SELECT, + PONGO_CLOCK_SELECT); + + return 0; +} + +static int alpha_pll_pongo_elu_enable(struct clk_hw *hw) +{ + struct clk_alpha_pll *pll =3D to_clk_alpha_pll(hw); + struct regmap *regmap =3D pll->clkr.regmap; + int ret; + + /* Check if PLL is already enabled */ + if (trion_pll_is_enabled(pll, regmap)) + return 0; + + ret =3D regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_= N); + if (ret) + return ret; + + /* Set operation mode to RUN */ + regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); + + ret =3D wait_for_pll_enable_lock(pll); + if (ret) + return ret; + + /* Enable the global PLL outputs */ + ret =3D regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTR= L); + if (ret) + return ret; + + /* Ensure that the write above goes through before returning. */ + mb(); + + return ret; +} + +static void alpha_pll_pongo_elu_disable(struct clk_hw *hw) +{ + struct clk_alpha_pll *pll =3D to_clk_alpha_pll(hw); + struct regmap *regmap =3D pll->clkr.regmap; + int ret; + + /* Disable the global PLL output */ + ret =3D regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); + if (ret) + return; + + /* Place the PLL mode in STANDBY */ + regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); +} + +static unsigned long alpha_pll_pongo_elu_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_alpha_pll *pll =3D to_clk_alpha_pll(hw); + struct regmap *regmap =3D pll->clkr.regmap; + u32 l; + + if (regmap_read(regmap, PLL_L_VAL(pll), &l)) + return 0; + + l &=3D PONGO_PLL_L_VAL_MASK; + + return alpha_pll_calc_rate(parent_rate, l, 0, pll_alpha_width(pll)); +} + +const struct clk_ops clk_alpha_pll_pongo_elu_ops =3D { + .prepare =3D alpha_pll_pongo_elu_prepare, + .enable =3D alpha_pll_pongo_elu_enable, + .disable =3D alpha_pll_pongo_elu_disable, + .recalc_rate =3D alpha_pll_pongo_elu_recalc_rate, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_pongo_elu_ops); + +void clk_pongo_elu_pll_configure(struct clk_alpha_pll *pll, + struct regmap *regmap, + const struct alpha_pll_config *config) +{ + u32 val; + + regmap_update_bits(regmap, PLL_USER_CTL(pll), PONGO_PLL_OUT_MASK, + PONGO_PLL_OUT_MASK); + + if (trion_pll_is_enabled(pll, regmap)) + return; + + if (regmap_read(regmap, PLL_L_VAL(pll), &val)) + return; + val &=3D PONGO_PLL_L_VAL_MASK; + if (val) + return; + + clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); + clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ct= l_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_= ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config= _ctl_hi1_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U2(pll), config->config= _ctl_hi2_val); + clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), + config->user_ctl_val | PONGO_PLL_OUT_MASK); + clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_= hi_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_va= l); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_= hi_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl= _hi1_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl= _hi2_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U3(pll), config->test_ctl= _hi3_val); + + /* Disable PLL output */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); +} +EXPORT_SYMBOL_GPL(clk_pongo_elu_pll_configure); + void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap= *regmap, const struct alpha_pll_config *config) { diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-= pll.h index 87bd469d9c2c2ec4e0758c97231527b92fe6afe5..79aca8525262211ae5295245427= d4540abf1e09a 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -27,6 +27,7 @@ enum { CLK_ALPHA_PLL_TYPE_ZONDA_OLE, CLK_ALPHA_PLL_TYPE_LUCID_EVO, CLK_ALPHA_PLL_TYPE_LUCID_OLE, + CLK_ALPHA_PLL_TYPE_PONGO_ELU, CLK_ALPHA_PLL_TYPE_TAYCAN_ELU, CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, CLK_ALPHA_PLL_TYPE_DEFAULT_EVO, @@ -53,6 +54,7 @@ enum { PLL_OFF_TEST_CTL_U, PLL_OFF_TEST_CTL_U1, PLL_OFF_TEST_CTL_U2, + PLL_OFF_TEST_CTL_U3, PLL_OFF_STATE, PLL_OFF_STATUS, PLL_OFF_OPMODE, @@ -138,6 +140,7 @@ struct alpha_pll_config { u32 test_ctl_hi_mask; u32 test_ctl_hi1_val; u32 test_ctl_hi2_val; + u32 test_ctl_hi3_val; u32 main_output_mask; u32 aux_output_mask; u32 aux2_output_mask; @@ -196,6 +199,7 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid= _evo_ops; #define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_ev= o_ops #define clk_alpha_pll_postdiv_taycan_elu_ops clk_alpha_pll_postdiv_lucid_e= vo_ops =20 +extern const struct clk_ops clk_alpha_pll_pongo_elu_ops; extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_o= ps =20 @@ -222,6 +226,8 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *= pll, struct regmap *regma const struct alpha_pll_config *config); void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap = *regmap, const struct alpha_pll_config *config); +void clk_pongo_elu_pll_configure(struct clk_alpha_pll *pll, struct regmap = *regmap, + const struct alpha_pll_config *config); #define clk_taycan_elu_pll_configure(pll, regmap, config) \ clk_lucid_evo_pll_configure(pll, regmap, config) =20 --=20 2.43.0