From nobody Wed Feb 11 06:31:23 2026 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38CB2158538 for ; Sun, 5 Jan 2025 18:15:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736100937; cv=none; b=iisVl6mlhHU6sLTUexfvTeyf7H1p2xt3VlNSUAPkl3Ikgm73XCasdv/Tv6opnPRSeZN+4nNm7EYvJjSTrWRpkSstcCZ9gvznZnajlw5XwlGzDf9U1i4DS2Mw+5PPKrvYzG7rqJGqLFjb1QSq1lKxBWyLDd6d1Bk/AKErizCqaqk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736100937; c=relaxed/simple; bh=OYiP2QG9kMV4RnRey17uDcC89PLcQMoOdIcHH/BgX+w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=E3W777PcV/JItCAaOrBbUbMQlR9OntuwpeGRnr9rXRYN/yL3KXCqXf8Ce1pO4iwwzxg5lS7CIuQDWLfM0a1iSCWh+y1IN5Ze4YEuMjiZJyzV3Qr1HcRCt/62fnM6FzhgPMichv8IOVhY/i0SB9ATHOiKv0Qq4QxXrbSNpPxV4LE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=OzhnIgcH; arc=none smtp.client-ip=209.85.218.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="OzhnIgcH" Received: by mail-ej1-f48.google.com with SMTP id a640c23a62f3a-aabfb33aff8so2448413066b.0 for ; Sun, 05 Jan 2025 10:15:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1736100933; x=1736705733; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+zwadKSgcT3YHRBr470NAxtLB4LzWS9m4NLNCF1dK9k=; b=OzhnIgcHG8/ssOMXniadvfMu9Bci2P04AUIQBzaCqhs5Qqlr6yPOXOQUqPjBvRnt4M HQjkXtTKVzfiiMDo/oravNNMhTlBsZvu2VH3wrNolkrzS6HY/Qx3Axx01JXbFwRJ8mhK t0GpPyChuY3m6sLpH+yJUMBjV+sJjqZuoNzDU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736100933; x=1736705733; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+zwadKSgcT3YHRBr470NAxtLB4LzWS9m4NLNCF1dK9k=; b=Cmn7y32bGyFd9qmvaKoAa7BAFL5g2JwLKoSj9kZt/s+8c0LG2hTHnqiVDDR9AeMTQS aBSenyOx7TNhDoAgrun5cuROb4mAQadRAilfiCCDuH8DjaVak3kJB0RDQkLRHWvnGmyQ uOq7iJiANlTaKJQW2dgPNxA8bM5TGPU5vSgQgsK92iuJzAB3bSOygz3X2k5hl6QcYBEk LVSY82UtZkjZwbppxaIFwAaCmPoDa+ldR/i54GYO6JHr/uFjFoYipdm1eFeC4GwaGKMK reG7M0vdMlntE5CqrlmoOy8UboV1Qq4mWd3sdbAgGiGQ4bRqW52YF7c8K79LVUuuv61r kwEQ== X-Gm-Message-State: AOJu0Ywdrge5l1deAqbzYrf5GaXUd0lwLqsWz8v1HUOLWhQ2OkpTxDJi lj8sr6DPPmGDw7NItLS3I0imHTpp/XQZRda0nCvpI3qWokfo8QrgSzWRKN3A/SLSx19/PznuCKX 1 X-Gm-Gg: ASbGncsPI5A0ZeXtUoVbJSgUOWpuq0Gj9oQ0nCiORZ9IPO/ndbiIkOATm4hA70UXPXZ FanovLAGohdQi8spQ+BVuI4LvWmvEmGnnELzwIcYStwrvdtFcRopa7h3B7BX0NTAU367/5Kxl24 9yRDgShYRBQJka3YzIUbOQUWPm0an9JOpmTBeRrorcenSe82CHxH6vIixpVcQrX00vsMtdj2CAD d/05STDHRrEf9+KrsXemBmqrMsxZ7AGW2gI8qQs6fMF43KJp218fLvGM7cM7erCyVwrCxPorHKs 0GX0QYogOM6OUfovTp94EJJsA6umpn9tq9ltH4Sro4PBYQjFazOCDoOrVoW0UA2G/uNzQ4eX2+G tWpBHAn/jJ4D0ePtPDg== X-Google-Smtp-Source: AGHT+IHEmlq6VZxXOC/j+3n171+PZx7zCTSoolypdqxYYVg9wTM278dYwsdwGbdufQTiEC+59arKyw== X-Received: by 2002:a17:907:86aa:b0:aae:f029:c2ec with SMTP id a640c23a62f3a-aaef029c69fmr3596149966b.12.1736100933172; Sun, 05 Jan 2025 10:15:33 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-41-6-15.retail.telecomitalia.it. [79.41.6.15]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0e82f178sm2138185066b.38.2025.01.05.10.15.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Jan 2025 10:15:32 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Michael Turquette , Rob Herring , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 1/6] dt-bindings: clock: convert stm32 rcc bindings to json-schema Date: Sun, 5 Jan 2025 19:14:13 +0100 Message-ID: <20250105181525.1370822-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250105181525.1370822-1-dario.binacchi@amarulasolutions.com> References: <20250105181525.1370822-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch not only performs the conversion according to the JSON-schema but also adds the missing parts: - st,syscfg phandle - st,stm32h743-rcc compatible that were not documented but are still used by the drivers and must therefore be included to ensure the patch submission tests do not fail. Signed-off-by: Dario Binacchi --- .../bindings/clock/st,stm32-rcc.txt | 138 ----------------- .../bindings/clock/st,stm32-rcc.yaml | 143 ++++++++++++++++++ 2 files changed, 143 insertions(+), 138 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/st,stm32-rcc.txt create mode 100644 Documentation/devicetree/bindings/clock/st,stm32-rcc.ya= ml diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt b/Doc= umentation/devicetree/bindings/clock/st,stm32-rcc.txt deleted file mode 100644 index cfa04b614d8a..000000000000 --- a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt +++ /dev/null @@ -1,138 +0,0 @@ -STMicroelectronics STM32 Reset and Clock Controller -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D - -The RCC IP is both a reset and a clock controller. - -Please refer to clock-bindings.txt for common clock controller binding usa= ge. -Please also refer to reset.txt for common reset controller binding usage. - -Required properties: -- compatible: Should be: - "st,stm32f42xx-rcc" - "st,stm32f469-rcc" - "st,stm32f746-rcc" - "st,stm32f769-rcc" - -- reg: should be register base and length as documented in the - datasheet -- #reset-cells: 1, see below -- #clock-cells: 2, device nodes should specify the clock in their "clocks" - property, containing a phandle to the clock device node, an index select= ing - between gated clocks and other clocks and an index specifying the clock = to - use. -- clocks: External oscillator clock phandle - - high speed external clock signal (HSE) - - external I2S clock (I2S_CKIN) - -Example: - - rcc: rcc@40023800 { - #reset-cells =3D <1>; - #clock-cells =3D <2> - compatible =3D "st,stm32f42xx-rcc", "st,stm32-rcc"; - reg =3D <0x40023800 0x400>; - clocks =3D <&clk_hse>, <&clk_i2s_ckin>; - }; - -Specifying gated clocks -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - -The primary index must be set to 0. - -The secondary index is the bit number within the RCC register bank, starti= ng -from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30= ). - -It is calculated as: index =3D register_offset / 4 * 32 + bit_offset. -Where bit_offset is the bit offset within the register (LSB is 0, MSB is 3= 1). - -To simplify the usage and to share bit definition with the reset and clock -drivers of the RCC IP, macros are available to generate the index in -human-readble format. - -For STM32F4 series, the macro are available here: - - include/dt-bindings/mfd/stm32f4-rcc.h - -Example: - - /* Gated clock, AHB1 bit 0 (GPIOA) */ - ... { - clocks =3D <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)> - }; - - /* Gated clock, AHB2 bit 4 (CRYP) */ - ... { - clocks =3D <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)> - }; - -Specifying other clocks -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - -The primary index must be set to 1. - -The secondary index is bound with the following magic numbers: - - 0 SYSTICK - 1 FCLK - 2 CLK_LSI (low-power clock source) - 3 CLK_LSE (generated from a 32.768 kHz low-speed external - crystal or ceramic resonator) - 4 CLK_HSE_RTC (HSE division factor for RTC clock) - 5 CLK_RTC (real-time clock) - 6 PLL_VCO_I2S (vco frequency of I2S pll) - 7 PLL_VCO_SAI (vco frequency of SAI pll) - 8 CLK_LCD (LCD-TFT) - 9 CLK_I2S (I2S clocks) - 10 CLK_SAI1 (audio clocks) - 11 CLK_SAI2 - 12 CLK_I2SQ_PDIV (post divisor of pll i2s q divisor) - 13 CLK_SAIQ_PDIV (post divisor of pll sai q divisor) - - 14 CLK_HSI (Internal ocscillator clock) - 15 CLK_SYSCLK (System Clock) - 16 CLK_HDMI_CEC (HDMI-CEC clock) - 17 CLK_SPDIF (SPDIF-Rx clock) - 18 CLK_USART1 (U(s)arts clocks) - 19 CLK_USART2 - 20 CLK_USART3 - 21 CLK_UART4 - 22 CLK_UART5 - 23 CLK_USART6 - 24 CLK_UART7 - 25 CLK_UART8 - 26 CLK_I2C1 (I2S clocks) - 27 CLK_I2C2 - 28 CLK_I2C3 - 29 CLK_I2C4 - 30 CLK_LPTIMER (LPTimer1 clock) - 31 CLK_PLL_SRC - 32 CLK_DFSDM1 - 33 CLK_ADFSDM1 - 34 CLK_F769_DSI -) - -Example: - - /* Misc clock, FCLK */ - ... { - clocks =3D <&rcc 1 STM32F4_APB1_CLOCK(TIM2)> - }; - - -Specifying softreset control of devices -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - -Device nodes should specify the reset channel required in their "resets" -property, containing a phandle to the reset device node and an index speci= fying -which channel to use. -The index is the bit number within the RCC registers bank, starting from R= CC -base address. -It is calculated as: index =3D register_offset / 4 * 32 + bit_offset. -Where bit_offset is the bit offset within the register. -For example, for CRC reset: - crc =3D AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset =3D 0x10 / 4 * 32 += 12 =3D 140 - -example: - - timer2 { - resets =3D <&rcc STM32F4_APB1_RESET(TIM2)>; - }; diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml b/Do= cumentation/devicetree/bindings/clock/st,stm32-rcc.yaml new file mode 100644 index 000000000000..ae9e5b26d876 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/st,stm32-rcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 Reset Clock Controller + +maintainers: + - Dario Binacchi + +description: | + The RCC IP is both a reset and a clock controller. + + This binding uses common clock and reset bindings + Documentation/devicetree/bindings/clock/clock-bindings.txt + Documentation/devicetree/bindings/reset/reset.txt + + Specifying softreset control of devices + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + Device nodes should specify the reset channel required in their "resets" + property, containing a phandle to the reset device node and an index spe= cifying + which channel to use. + The index is the bit number within the RCC registers bank, starting from= RCC + base address. + It is calculated as: index =3D register_offset / 4 * 32 + bit_offset. + Where bit_offset is the bit offset within the register. + + For example, for CRC reset: + crc =3D AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset =3D 0x10 / 4 * 32 += 12 =3D 140 + + The list of valid indices is available in: + - include/dt-bindings/mfd/stm32f4-rcc.h for STM32F4 series + - include/dt-bindings/mfd/stm32f7-rcc.h for STM32F7 series + - include/dt-bindings/mfd/stm32h7-rcc.h for STM32H7 series + +properties: + compatible: + oneOf: + - items: + - const: st,stm32f42xx-rcc + - const: st,stm32-rcc + - items: + - enum: + - st,stm32f469-rcc + - const: st,stm32f42xx-rcc + - const: st,stm32-rcc + - items: + - const: st,stm32f746-rcc + - const: st,stm32-rcc + - items: + - enum: + - st,stm32f769-rcc + - const: st,stm32f746-rcc + - const: st,stm32-rcc + - items: + - const: st,stm32h743-rcc + - const: st,stm32-rcc + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + + '#clock-cells': + enum: [1, 2] + + clocks: + minItems: 2 + maxItems: 3 + + st,syscfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to system configuration controller. It can be used to contro= l the + power domain circuitry. + +required: + - compatible + - reg + - '#reset-cells' + - '#clock-cells' + - clocks + - st,syscfg + +allOf: + - if: + properties: + compatible: + contains: + const: st,stm32h743-rcc + then: + properties: + '#clock-cells': + const: 1 + description: | + The clock index for the specified type. + else: + properties: + '#clock-cells': + const: 2 + description: | + - The first cell is the clock type, possible values are 0 for + gated clocks and 1 otherwise. + - The second cell is the clock index for the specified type. + +additionalProperties: false + +examples: + # Reset and Clock Control Module node: + - | + rcc@40023800 { + #reset-cells =3D <1>; + #clock-cells =3D <2>; + compatible =3D "st,stm32f42xx-rcc", "st,stm32-rcc"; + reg =3D <0x40023800 0x400>; + clocks =3D <&clk_hse>, <&clk_i2s_ckin>; + st,syscfg =3D <&pwrcfg>; + }; + + - | + rcc@40023800 { + #reset-cells =3D <1>; + #clock-cells =3D <2>; + compatible =3D "st,stm32f746-rcc", "st,stm32-rcc"; + reg =3D <0x40023800 0x400>; + clocks =3D <&clk_hse>, <&clk_i2s_ckin>; + st,syscfg =3D <&pwrcfg>; + }; + + - | + rcc@58024400 { + compatible =3D "st,stm32h743-rcc", "st,stm32-rcc"; + reg =3D <0x58024400 0x400>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + clocks =3D <&clk_hse>, <&clk_lse>, <&clk_i2s>; + st,syscfg =3D <&pwrcfg>; + }; + +... --=20 2.43.0 From nobody Wed Feb 11 06:31:23 2026 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4BDD1552E0 for ; Sun, 5 Jan 2025 18:15:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736100939; cv=none; b=NKUB2ER9E06lmWqtPSFKXUKRoDOzMoIJctsQsJ9MzlVMvagARhpAv3dwl599eyQAxS6r6I2qB3pVhUwAKoNAm0QE56NOHBvvnqoiUJ2hUxiP3IAdEILHskWOxVrkEqsvTnRqYLXjqoqhN0JNhYVXaHKyyA0/FytI/NQx7asyhls= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736100939; c=relaxed/simple; bh=R1RqfntRJFOx36yCcR4Mwvgf6/yfFCoRdqfgTg8JbsI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VA7aDPPlncAUcU5hJ4ozojhP6by27glgFBMpAIDE97GdJME6cmktpKlSutUeCMcG+v4ydWQCSKKx4h5XojX6WAaOpjvKS+TA1VGXehvFfwP2BX7GnVND4YZpJVMgvsMdlX2moJO2BL/ZjUQYIv8dksDl51GW66X3dnX2qOn9AGE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=mqlQQZxT; arc=none smtp.client-ip=209.85.218.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="mqlQQZxT" Received: by mail-ej1-f46.google.com with SMTP id a640c23a62f3a-aa679ad4265so2692505066b.0 for ; Sun, 05 Jan 2025 10:15:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1736100935; x=1736705735; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UOAsdgxDQEvC5uDcWK+yR25E57Nu26K/3jc3ZbJ9Cg0=; b=mqlQQZxTk1IX4XswsR8Bzkc8tN1F0DqWJlbd4Ea8aDRxu9mkDtTj9JVppftGEi9RL6 MiD3BDCa3JyyDD9+HUMjYdoWzVvR3oAXdbeLFHcwxwOJWbtyhri6FWZ6Xzuz0RwioopA 1OPTGHHXilC66MDYJqL4qjiAldAwO/lwJRPD4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736100935; x=1736705735; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UOAsdgxDQEvC5uDcWK+yR25E57Nu26K/3jc3ZbJ9Cg0=; b=n4N02uqG7Yr3/AX+V4Jc2lzqfDYDomENz54HUcQzx6TdGMW1Uvatwg0dcpIMeQSf7P hvlnGrJMgYWUyJ0QHPw7IQB8TSWXj9CASvTTBDy6oIRtVaSYMvmWOd/1Cl5nsmd/30iF 7x/3o5ySHTPIet5XxJA9Gaqfv/AZcL0F+b3vdWbEwXO0GJnBGM7XGfL0M+R4ITr+z8RG 2AIbMeT727IvwW9ffX68a/aDCSyZPN5wDJnDVLai1j2umho3ku4Yqdc9Ia3kZGKGoxrh gMv6w5cvaiVNBQZRrSTIglPyHxy1F/vDq9ougcCPBUrcf01E7M0hp9Ofo7cb/e1PlluV hxAQ== X-Gm-Message-State: AOJu0YwOo3jWSmcH6dhdyssp5VUjufo/D4teAHV7EY/bcQXsgWRC+bGQ yQHG0f/AlvEHvo0PpPNYQVdsCdZ8sjbyhSR8CmBLW2+4Kq7eXm0BHEJNA6LBWtAxkEuQhaE8SvT n X-Gm-Gg: ASbGncuej6QUnSeZAsGPmziwMiG4NaZTSCrBtFftqd7+13DhX90wA/O75N+ENQEGGlA 8QcqVr2joz0h4UJw5rxtiXQtMbeWrFt8upPkZ7KBcn4GFPPq2ea0Z2sqjvTQ4Gjz6D1T79KubXF 39HRojI+F/GFiBPSQ9qpXsY/A9iqVD7FDKzn/aYzbovuTZFhhy+J+b2Go4ZlHhexvc87nFJqVuc F3529oIZzHm88BF0AECHTxiZ1Wvn5jZFbs7WpYET/ST46RX2rJy24SJ9jE/hgj+VDGqAh1yEtx3 2IUeGvBYfYvYMnn2VxEKncT2FSEmwv6cVZUwDOX4bmHiDtBCbq8saSV60qjjGn/H1V2YiUX4BY2 zDC+vrpzfNMSqWaE4lw== X-Google-Smtp-Source: AGHT+IGmgVgc6B2TGyiYFDwVaPwnmHLCNND0P6xPziVSDtm7hEJn68GNvTjYVOhO12g7nBOja7hhAw== X-Received: by 2002:a17:906:dc8f:b0:aab:a1a8:92be with SMTP id a640c23a62f3a-aac080feebdmr5370408766b.5.1736100934660; Sun, 05 Jan 2025 10:15:34 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-41-6-15.retail.telecomitalia.it. [79.41.6.15]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0e82f178sm2138185066b.38.2025.01.05.10.15.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Jan 2025 10:15:34 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Philipp Zabel , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 2/6] dt-bindings: reset: st,stm32-rcc: update reference due to rename Date: Sun, 5 Jan 2025 19:14:14 +0100 Message-ID: <20250105181525.1370822-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250105181525.1370822-1-dario.binacchi@amarulasolutions.com> References: <20250105181525.1370822-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With the conversion of Documentation/devicetree/bindings/clock/st,stm32-rcc= .txt to JSON schema, the reference to st,stm32-rcc.txt is now broken. Therefore, let's fix it. Signed-off-by: Dario Binacchi --- Documentation/devicetree/bindings/reset/st,stm32-rcc.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt b/Doc= umentation/devicetree/bindings/reset/st,stm32-rcc.txt index 01db34375192..384035e8e60b 100644 --- a/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt +++ b/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt @@ -3,4 +3,4 @@ STMicroelectronics STM32 Peripheral Reset Controller =20 The RCC IP is both a reset and a clock controller. =20 -Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt +Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml --=20 2.43.0 From nobody Wed Feb 11 06:31:24 2026 Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F15A1CEE86 for ; Sun, 5 Jan 2025 18:15:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736100941; cv=none; b=pItaZAqtmVpweucM/AC5ocrmKX0bZ0i3yWrR8YzWolkyukyQcvHdMoftlXS4fpCPbKbaxlXlMbayxQI58HOz88jVAIBbJxgYCK6giNFbSKJ6cguGcCW9bYBmHrm25+2dhmSUY2cdGN9p+zZiOHUzVH1d+H5H7VGvP6z7vUuECUs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736100941; c=relaxed/simple; bh=Se3lRcHtGRPWwwaNRlFMfAK7boLIp7LH1AcyeBrpWOA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CP4lb4mFMOCKXSXlCGY2bI2fGpWSG0WWgqlC1d3bL/44zQ2Sn0PA/wpSfxNAEtipmgKMkr2k+OrnVpeuc5tH3ooT2ZcCESgiLDrHG6b6/UViEzUMwXQBE5DvuSyDJokvKWcsHNoXmRgX3JtT6i1tdXnh/Vjp3yySEPXU1fD6RwA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=cWfZ/uFe; arc=none smtp.client-ip=209.85.208.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="cWfZ/uFe" Received: by mail-ed1-f53.google.com with SMTP id 4fb4d7f45d1cf-5d7e3f1fc01so28133549a12.2 for ; Sun, 05 Jan 2025 10:15:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1736100937; x=1736705737; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ngcCwmTO+RIG/baergO/2VLeRq3P88V5Zllx9oRRwrs=; b=cWfZ/uFeICDU2d/sXMHN/dNDs4/eXGx2egMZd1fG5K/l6XltE00PAsu0VN88OiToPH OKWpiDJdqF6/ZHSXggVPq6zuz6SMMR4cGUrN/aCJPirXi6puvS+wDlC+pMWjDWuQtwF+ dM82cDZRvuR433yBveP8tzU1HOfrUD95LkKhk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736100937; x=1736705737; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ngcCwmTO+RIG/baergO/2VLeRq3P88V5Zllx9oRRwrs=; b=F7JGqTFHXVRVg5lElj4u81KS/6es5IbTk+KhSW9U/PnzBUSBbvK5ahaXFofFH4BTnu g19cymzLueZQz7UPtJ/jfqGFEpXGuAsizdXckRIx7ME1rdNS8oVcTEuhY8hiRYz0iROp KYvYlQcEXMF9jFzgTwmVzNlEYHYaQ5w+8Kq0mKHUzF8QhARUAQLS8gaU98bOOJiOmSCu QFs5AXEF2z7pMlrP2bnayAdccVjBsxocm4LH8S15X/AKfk1uOtV3Jp1ouzqOwmb6TpK0 1k9Ihy6QjLOFWwK9PeP17/jfNt4nSvALb2VF4+KsWsGhhWEaM7BjRxTaAa2eyiGDoHh0 jSEA== X-Gm-Message-State: AOJu0YyYvUXAT/WOuyQSTFd2PyEreSk8w5/+S0dN+1nR2x+EQyewJvw4 Hq7zvuZgVqZQWVPUxcT89UGeeAX96KyUvuWBEAEAvB8JYoe1MHMM8zSBUHsVRkBT38t7ZThelh4 h X-Gm-Gg: ASbGncuPBhFxsOmTuaCTJS/IzfgJryM3RlIPEd6OEz+jNYYltIXWjLj+Vxuc/EbewBz +E8o+rvJsu+39nK7NeY+nyKoMRgv0VgvhlNG4lCDypam7Bk0DA2cGS+yHQQbLg3rD9KLp4Hi7Ef 9Ko6eAbVFcIGuM74fZ5UI/JA4npQFqdihWKcuRv/pcPlsB71DESZ0Ze5qShXeNDbqxVzDOtc1PL tejtcMewsKDBlsEIRT0yGsElcW1dH7cRPjUvj//TFrZlM4ZOqX74N+RUTDGM94lbvRX87PiCNI4 gHcrrk915NNIwftBUpIWJY3c+JzOuGoOXxMo1opUDNikK2GP2RP3R53hA70vUsTfK9/TNBEe5pt LjBAqpa/Klo4xmCsMeA== X-Google-Smtp-Source: AGHT+IHxEDK9nG2Mi+Pm0wOh++nf130PTCB6/hhMGClugIlI0HI6FjgJGvhFReNL/vJEU6H89u69cA== X-Received: by 2002:a05:6402:4305:b0:5d0:e014:dee2 with SMTP id 4fb4d7f45d1cf-5d81de160f9mr56356151a12.27.1736100937450; Sun, 05 Jan 2025 10:15:37 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-41-6-15.retail.telecomitalia.it. [79.41.6.15]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0e82f178sm2138185066b.38.2025.01.05.10.15.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Jan 2025 10:15:37 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Michael Turquette , Rob Herring , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 3/6] dt-bindings: clock: stm32fx: update reference due to rename Date: Sun, 5 Jan 2025 19:14:15 +0100 Message-ID: <20250105181525.1370822-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250105181525.1370822-1-dario.binacchi@amarulasolutions.com> References: <20250105181525.1370822-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With the conversion of Documentation/devicetree/bindings/clock/st,stm32-rcc= .txt to JSON schema, the reference to st,stm32-rcc.txt is now broken. Therefore, let's fix it. Signed-off-by: Dario Binacchi --- include/dt-bindings/clock/stm32fx-clock.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-binding= s/clock/stm32fx-clock.h index e5dad050d518..b6ff9c68cb3f 100644 --- a/include/dt-bindings/clock/stm32fx-clock.h +++ b/include/dt-bindings/clock/stm32fx-clock.h @@ -10,7 +10,7 @@ * List of clocks which are not derived from system clock (SYSCLOCK) * * The index of these clocks is the secondary index of DT bindings - * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt) + * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml) * * e.g: ; --=20 2.43.0 From nobody Wed Feb 11 06:31:24 2026 Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D21301CF5EA for ; Sun, 5 Jan 2025 18:15:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736100942; cv=none; b=XdSTVTxlanEzu7glLDMCvwdyRY4cwbSbpX1ffvXbPzdVpITPn/hc1OyM76I2C1EW7nG5yWnN6ivGEtZJP8kfZvt/M9t9DRZprbIUmXomA2GuIRvU7YKABrm1dddyH5NOj5XG8VA6hzSRXC+Zc9ZKmwQKolMxoyVp9LYQ+A0mzd4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736100942; c=relaxed/simple; bh=yOiVkGwEdMZydm8mezT59eqr13KDSeir4uRipppy1Y8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WwhiMLqHZXICTBokANclhplO/bPjwaWRt4zl0EbduzstrSC0B5sybBKm9SP7Ie3hR68QezLeuQWuv6GV9QwMa451E5tKrm/feGdLyhNrf+F8Ebqt3Q87pvt0fKA6FSHEiSSnViiAXBOWNZmzYJ0nchVSNnjCzCgsXLSmIYkq2zE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=HTBW8RLZ; arc=none smtp.client-ip=209.85.218.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="HTBW8RLZ" Received: by mail-ej1-f41.google.com with SMTP id a640c23a62f3a-aa6a92f863cso2405043466b.1 for ; Sun, 05 Jan 2025 10:15:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1736100939; x=1736705739; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DBSWyldngVnQclvBLd3GqHALlVJ1Kxh3yvgFvrg0xjA=; b=HTBW8RLZzDaJtfRzAnBA0x6LLLOMzPddLL6YT5kTESOSAWpjhrP35VmttHyFkYXKdF 4dbTchOaiI5U7g6gXI9wriDQauoxdlBeQm6VHf9SBcb+7PErTf6Dixta89E3KcU2ccvY WaGKuK53HNicptqa8R7VkPU6JebsnFy30M284= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736100939; x=1736705739; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DBSWyldngVnQclvBLd3GqHALlVJ1Kxh3yvgFvrg0xjA=; b=AOb4UOnjWKaBt/UezeIQeN8QUfrlLlVJiCp/mFSRHz1FUSFjou0iQC0AKTIaspjfnh D1lGZUPgcjgh2hAX9TskM6xXNH6IaD9Qi+6yxjPB1CYPRVOSSXNy4mINkI23V+r80GwN NRs2JDn0DL9YdKPxk1ALd8HkEFkKJdnISUps6VwFALu7uwKPNmmJlZ1imX8z9uvEPVke HYOYecsqjCA9XFBA/XWpNYxAadYYL9yoElTOfYYWok767kSJgcsiBuq5J4wosQPIoZpc uhC5m72+YPqwZj7GFW4quFfFvgSMdU+dB9iV3KG0VXCBrSpDyCDjfXJrJw6sfuXHeDIj M89A== X-Gm-Message-State: AOJu0YyslO6JVaPGAH+hloEP0sZV7WR3EyCSMy47f2ksGMbY8KuToyz0 PDTeRfjbAE/9zuM8o90hFzPuTbzHENM5qM0c94978TD8OIT8QVgWkbY+zOqtXzdHmCe7wsgXeDV C X-Gm-Gg: ASbGncvkv/J9OUU5AKlsbKIPhq0DGQ0kNB4QsNJ2viMmFQFJVPO4ueT6yg5IfTMTYYN p+n6D6DsZtGDeSwCDQy4T2R7fbprg3IBWJcqJsbnWR6gGJIZZKOCMP5dRB2cidgz+kgnTpWtfqy 5cOBHXeVcRY5/m6yE7+Tt6wjYcwqVKihsh6s5l/64mdAJJxAcvNQw44nNb0j4F+JT/hFFNLKMit CBmEvvRPkZJpkmfHCFgzx0lSAIpf88/vuh767xEBJrb99WLBC+LDxwm7wuNRmqHGoQp+ZGn66bo 1WspOEvJBgNjqnyBTIoqmdbsEEFofKKZiWlmCF/yOZMSjwQYRvUNltmK/dQjRNKWcls8kMhQVnO XMjDC9RG+ed0V55jMDg== X-Google-Smtp-Source: AGHT+IEouP5DBWHZTHTQqFEZUf+3uEYRS8Zu6JvRBqEkbBu3GJtaa/Q5Qj6PinpQXdyRMCSrqc9f7w== X-Received: by 2002:a17:907:3e90:b0:aa6:abb2:be12 with SMTP id a640c23a62f3a-aac3354ff4dmr3925314866b.37.1736100938804; Sun, 05 Jan 2025 10:15:38 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-41-6-15.retail.telecomitalia.it. [79.41.6.15]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0e82f178sm2138185066b.38.2025.01.05.10.15.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Jan 2025 10:15:38 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Michael Turquette , Rob Herring , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 4/6] dt-bindings: clock: st,stm32-rcc: support spread spectrum clocking Date: Sun, 5 Jan 2025 19:14:16 +0100 Message-ID: <20250105181525.1370822-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250105181525.1370822-1-dario.binacchi@amarulasolutions.com> References: <20250105181525.1370822-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The addition of DT bindings for enabling and tuning spread spectrum clocking generation is available only for the main PLL. Signed-off-by: Dario Binacchi --- .../bindings/clock/st,stm32-rcc.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml b/Do= cumentation/devicetree/bindings/clock/st,stm32-rcc.yaml index ae9e5b26d876..c345d3ff3fc4 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml @@ -77,6 +77,26 @@ properties: Phandle to system configuration controller. It can be used to contro= l the power domain circuitry. =20 + st,ssc-modfreq-hz: + description: + The modulation frequency for main PLL (in Hz) + + st,ssc-moddepth-permyriad: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The modulation rate for main PLL (in permyriad, i.e. 0.01%) + minimum: 25 + maximum: 200 + + st,ssc-modmethod: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + description: + The modulation techniques for main PLL. + items: + enum: + - center-spread + - down-spread + required: - compatible - reg @@ -97,6 +117,10 @@ allOf: const: 1 description: | The clock index for the specified type. + st,ssc-modfreq-hz: false + st,ssc-moddepth-permyriad: false + st,ssc-modmethod: false + else: properties: '#clock-cells': @@ -118,6 +142,9 @@ examples: reg =3D <0x40023800 0x400>; clocks =3D <&clk_hse>, <&clk_i2s_ckin>; st,syscfg =3D <&pwrcfg>; + st,ssc-modfreq-hz =3D <10000>; + st,ssc-moddepth-permyriad =3D <200>; + st,ssc-modmethod =3D "center-spread"; }; =20 - | --=20 2.43.0 From nobody Wed Feb 11 06:31:24 2026 Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E548F1CDFAE for ; Sun, 5 Jan 2025 18:15:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736100946; cv=none; b=ldggDeH+zqHSuXv7e+ZFp6tDpnKKLBer2OEPMHJPno6uPg6pArMJ6+CE7IEy760pYrTdwTytfg0YKoO7NLmkalbwK0oCWf9apsIFpHiWkJoQf0MNveQ9vKFvxA5ZLRNLERbPnPCPhg06UKBMnge+Dpgl2qVyGxYxDUnqvvQ+Rhw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736100946; c=relaxed/simple; bh=uyYm4AkMvyc5cNDTbp+U5fuCFOWH+DVbD8gtKAdlEIU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PJSywUnUF226WeFS1UFRLH/gOAeORrzmGDoeOzVwuSU6hbbWblBGD0L9G/LYyremnv6WYD3/bwdu1w+71Cw1z5tCjlSxmk/qF+nNzoEzG0JNGfH6jGXsUmGPoKjCBnAK+UxRdNYWI2r0t1xnGZAf79CmvHmp7uNR3Womg/Shgvw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=CQh2d8V6; arc=none smtp.client-ip=209.85.208.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="CQh2d8V6" Received: by mail-ed1-f48.google.com with SMTP id 4fb4d7f45d1cf-5d7e527becaso23155005a12.3 for ; Sun, 05 Jan 2025 10:15:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1736100941; x=1736705741; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nCWum8u2aSE0H9NGugk1g+nl+FSObYpFAdsp0A4AhFk=; b=CQh2d8V6fMapEPmyoZng4SCtlKbEkpihSEOf2MgK3yVgahynmPLDNqoLvFgMD4Vr0a ZldnVRCGik6dnF9DQwsZRU+uRYOJcHq/KNGdxzeKQJgdRtih2M92nefDEvmhqhaX48Aj AvRW1TK5ASWYzT1rgzmFNN87KJewp4jZZ6l4k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736100941; x=1736705741; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nCWum8u2aSE0H9NGugk1g+nl+FSObYpFAdsp0A4AhFk=; b=qRnTXAqMi14WmU/QD0f0KwDW/+mwPrjuT8oTJZQmPVlDX5+Py0XeiWgiZOPgP8165B KN7amE/p62uTgnywFWaaYWP0WK/bwtpBbpo7qrATfyQ2YmfTgNiCEPAjEjET47nIdmP0 gFnTaZm5lyUA2jAPzE3wyPtYt7p53gPjSCoDzvYMBCyRmZmMw4roi1BcCG4f6Xc4PD7P wDSrLBF2dYQrvcFqSp4prp/t+ny0KSzrJxNlf4gu5Wp4D5yQB3/jHsCdtTmFPDTqMyz/ J9vb1KwbBv9vVzYZsv19QhadLd3SCrkmPLzqkDELSAMnxGurV+D8SuQ+xjpOPC8qjDeu oi3g== X-Gm-Message-State: AOJu0YyEHB7bwRjgGdSR3Qb1J4TqfP9KKacjZLJnYAX0aTuddZKlK6pA tPP6162GFHPu5wGhwQi1f4VmjKWZ6FKHjv+5jhsJ+rSJavXiEmFjq9afAOv9gYJaUKCWJSDk2Mx + X-Gm-Gg: ASbGnct+/0+BRdp/eCTdEaCC0zPcUxd0H7ID1hqJxRPOdSZwYW9oCkr+p8seyE9STrZ AcQ+zMfgKqibnQy6hi2d8a/hVPLCiW3ZKVNUYl9HuxsmLZ3AA4J/LDMWljnLXuOpzWgtBpWMRxC dSn+TPaSR/v167qU2bJ8IoneaD5jCOXUYjnJmvko9ojYg34Gh5JW5m/VcdqLEc+dlofkSDjhvo5 S1KvlKZcRAzhkp65WRau+PMQKIPhJau3sINmKyChE04zOzBPIKEb4v0NbWv9rNqMioMAxPbr1/a HTndNLX7HerMAA4HXxn1r/WytyAsH2mhXEjAm/VUac99C0nygJvuqsy7zCiyqUAGGQVxk3bP+65 1sf5Y/lrE2WmRHvPk2g== X-Google-Smtp-Source: AGHT+IFeu46e7LHQ6MyNCXFCxnHyuX7vCIGWrO/EtiZn47VacrN5DdmgWvSrKWY5flVSdhQ2UzUVwg== X-Received: by 2002:a05:6402:540b:b0:5d6:48ef:c19f with SMTP id 4fb4d7f45d1cf-5d81de1c28fmr134000185a12.29.1736100941394; Sun, 05 Jan 2025 10:15:41 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-41-6-15.retail.telecomitalia.it. [79.41.6.15]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0e82f178sm2138185066b.38.2025.01.05.10.15.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Jan 2025 10:15:40 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Maxime Coquelin , Michael Turquette , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 5/6] clk: stm32f4: use FIELD helpers to access the PLLCFGR fields Date: Sun, 5 Jan 2025 19:14:17 +0100 Message-ID: <20250105181525.1370822-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250105181525.1370822-1-dario.binacchi@amarulasolutions.com> References: <20250105181525.1370822-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use GENMASK() along with FIELD_GET() and FIELD_PREP() helpers to access the PLLCFGR fields instead of manually masking and shifting. Signed-off-by: Dario Binacchi --- drivers/clk/clk-stm32f4.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index 07c13ebe327d..db1c56c8d54f 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -5,6 +5,7 @@ * Inspired by clk-asm9260.c . */ =20 +#include #include #include #include @@ -39,6 +40,8 @@ #define STM32F4_RCC_DCKCFGR 0x8c #define STM32F7_RCC_DCKCFGR2 0x90 =20 +#define STM32F4_RCC_PLLCFGR_N_MASK GENMASK(14, 6) + #define NONE -1 #define NO_IDX NONE #define NO_MUX NONE @@ -632,9 +635,11 @@ static unsigned long stm32f4_pll_recalc(struct clk_hw = *hw, { struct clk_gate *gate =3D to_clk_gate(hw); struct stm32f4_pll *pll =3D to_stm32f4_pll(gate); + unsigned long val; unsigned long n; =20 - n =3D (readl(base + pll->offset) >> 6) & 0x1ff; + val =3D readl(base + pll->offset); + n =3D FIELD_GET(STM32F4_RCC_PLLCFGR_N_MASK, val); =20 return parent_rate * n; } @@ -673,9 +678,10 @@ static int stm32f4_pll_set_rate(struct clk_hw *hw, uns= igned long rate, =20 n =3D rate / parent_rate; =20 - val =3D readl(base + pll->offset) & ~(0x1ff << 6); + val =3D readl(base + pll->offset) & ~STM32F4_RCC_PLLCFGR_N_MASK; + val |=3D FIELD_PREP(STM32F4_RCC_PLLCFGR_N_MASK, n); =20 - writel(val | ((n & 0x1ff) << 6), base + pll->offset); + writel(val, base + pll->offset); =20 if (pll_state) stm32f4_pll_enable(hw); --=20 2.43.0 From nobody Wed Feb 11 06:31:24 2026 Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62B8C1D5151 for ; Sun, 5 Jan 2025 18:15:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736100948; cv=none; b=GpDNcua2pHbYUZhx6EfFOi83vReY1LB2sTLMPJZFhm+3EPPra2xkXFJyOr2KvF7N+fYpiqPKgX6kck1xPKZGY7Dz8TTtr1wP7ETMwrK/OK3VpEwNenJ3/geFE54wVGqYug5HZyjl1k9xUdIGBydZ2Dt74JvZ75ACxNC+Aob3xBs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736100948; c=relaxed/simple; bh=D3sK7YbjOg6v1dIHt2H3xYhrp59wINI5DGiX1I55/0k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=twby5hUIYMJe1yjS+V+XhjH5PY6KD9icGYBs50qmpFou1bQyD8Nr60gf1HfyOcaY+6m9e7U41Ptsu+JNvqAGIClpxDAyIC4wteXYwHQyjjUNmcVc//QohZBSUA3oWaBjzVQCbJn9hi4CQnEl2bh3MMxHIMQwr/HSoj5CGenUEms= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=ZBonKFcT; arc=none smtp.client-ip=209.85.218.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="ZBonKFcT" Received: by mail-ej1-f43.google.com with SMTP id a640c23a62f3a-aaec111762bso2171270266b.2 for ; Sun, 05 Jan 2025 10:15:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1736100942; x=1736705742; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CYt+s6fkrUpxe5XF17lxHByzQRCB3AxfRzKWTwCyBC0=; b=ZBonKFcT0UXlEz2PZYdnbgbzSHeKsngeKY2YdyUIPtQ+YVF6SLaizOxIEYeKWxbcSo jbO/UB0l09LaHb42kC7aKRamqM68oHVSeZhM4VdNxUDgPrymm9BpjUW+UOF49txGf1Gk Rt7yK7vlpnlnRPK8KfgcjkfEy4eP6e1qaTYGM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736100942; x=1736705742; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CYt+s6fkrUpxe5XF17lxHByzQRCB3AxfRzKWTwCyBC0=; b=BiG1qDzlDy+F5qcQb2sRu50/R7IHkdLl6ns8uts/pO8Oo75e3YHIOsOMRRtbItufjk 8l/kcufN0sgF6R9k8B6tgEu6zpd/gyWDlas7aTyfvah4pmKryATB+6RV9pkCt3yMHKYz 2HswHPOWPE4wxZtJ7r6rtPaXY6PEWoCg1IqfD3MPu7pFbfXNeVdLRUdZaVMb5STdrxEh pCTRosRAT+TLX0bt9Benlzuvz/V+JmJPz0gYcjsXM+OlCgdGM2f4tcty+pnwlhLa4Zta s+zE8uXcci2uYdNCjH1+VfMK2cu+3tsAD4ytKUPt2ZL62HK+PIV9iO6ZVsP310+j9cs6 bmzw== X-Gm-Message-State: AOJu0YzzZ6rp7cs9bB9ftjFB4eQqqXFLG0E7NTQbQxEPSCDAwoFSHXXV 72fs48OPH8HdDmoLLIXpr1WMi4t+Xnx1MUBsSyemBAEIk/MW69JsIBm6YnHNHWhK8RCiJcwjfe5 3 X-Gm-Gg: ASbGncsfGPVmUYQMEEJuY/vbWMTyoG9z3pj0F7ER42jh4cGacGdLB1wbgyxxCmEZi52 dS7692UjEuGqg+yeHTry4qOTgCYS/n/Q4f2uFiaHmeA64mcF92do7Cc6zYWnw4GCrSwETiP/IM2 bmni4omv907Y0bmZ/NHN7StgKO7OtmL2vUlf4oe6iOV9fi0tMn64jEWjoEGhLEQuXCLEby/phzl svh1u7sWFkc4ScrnZRkJlqsNwseT4samwN2M6uOg1VI+6tya/mWecW8twdqN6GqJnMr6hJPUtYt TRvoKlzMgqJ2Fxp1Caxxlb+MkQjSF3I92o3IKrrIZMjT7T0CCyiQ1/YkGNuVtqa3jH2QsVYA1Y5 atyAhSGvNkIg5qKoPyA== X-Google-Smtp-Source: AGHT+IHKfniWL7KIZr5UBchy8RdTJDMipbRucCKrppnn1VBJEdWfGEKF6uqo/1J4HGrc00eEihpFhA== X-Received: by 2002:a17:907:7e86:b0:aaf:ada2:181e with SMTP id a640c23a62f3a-aafada219d8mr879413566b.26.1736100942566; Sun, 05 Jan 2025 10:15:42 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-41-6-15.retail.telecomitalia.it. [79.41.6.15]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0e82f178sm2138185066b.38.2025.01.05.10.15.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Jan 2025 10:15:42 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Maxime Coquelin , Michael Turquette , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 6/6] clk: stm32f4: support spread spectrum clock generation Date: Sun, 5 Jan 2025 19:14:18 +0100 Message-ID: <20250105181525.1370822-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250105181525.1370822-1-dario.binacchi@amarulasolutions.com> References: <20250105181525.1370822-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support spread spectrum clock generation for the main PLL, the only one for which this functionality is available. Tested on the STM32F469I-DISCO board. Signed-off-by: Dario Binacchi --- drivers/clk/clk-stm32f4.c | 143 +++++++++++++++++++++++++++++++++++++- 1 file changed, 140 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index db1c56c8d54f..6c80c0dbb0a3 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -35,6 +35,7 @@ #define STM32F4_RCC_APB2ENR 0x44 #define STM32F4_RCC_BDCR 0x70 #define STM32F4_RCC_CSR 0x74 +#define STM32F4_RCC_SSCGR 0x80 #define STM32F4_RCC_PLLI2SCFGR 0x84 #define STM32F4_RCC_PLLSAICFGR 0x88 #define STM32F4_RCC_DCKCFGR 0x8c @@ -42,6 +43,12 @@ =20 #define STM32F4_RCC_PLLCFGR_N_MASK GENMASK(14, 6) =20 +#define STM32F4_RCC_SSCGR_SSCGEN BIT(31) +#define STM32F4_RCC_SSCGR_SPREADSEL BIT(30) +#define STM32F4_RCC_SSCGR_RESERVED_MASK GENMASK(29, 28) +#define STM32F4_RCC_SSCGR_INCSTEP_MASK GENMASK(27, 13) +#define STM32F4_RCC_SSCGR_MODPER_MASK GENMASK(12, 0) + #define NONE -1 #define NO_IDX NONE #define NO_MUX NONE @@ -512,6 +519,17 @@ static const struct clk_div_table pll_divr_table[] =3D= { { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, { 0 } }; =20 +enum stm32f4_pll_ssc_mod_type { + STM32F4_PLL_SSC_CENTER_SPREAD, + STM32F4_PLL_SSC_DOWN_SPREAD, +}; + +struct stm32f4_pll_ssc { + unsigned int mod_freq; + unsigned int mod_depth; + enum stm32f4_pll_ssc_mod_type mod_type; +}; + struct stm32f4_pll { spinlock_t *lock; struct clk_gate gate; @@ -519,6 +537,8 @@ struct stm32f4_pll { u8 bit_rdy_idx; u8 status; u8 n_start; + bool ssc_enable; + struct stm32f4_pll_ssc ssc_conf; }; =20 #define to_stm32f4_pll(_gate) container_of(_gate, struct stm32f4_pll, gate) @@ -541,6 +561,7 @@ struct stm32f4_vco_data { u8 offset; u8 bit_idx; u8 bit_rdy_idx; + bool sscg; }; =20 static const struct stm32f4_vco_data vco_data[] =3D { @@ -661,6 +682,34 @@ static long stm32f4_pll_round_rate(struct clk_hw *hw, = unsigned long rate, return *prate * n; } =20 +static void stm32f4_pll_set_ssc(struct clk_hw *hw, unsigned long parent_ra= te, + unsigned int ndiv) +{ + struct clk_gate *gate =3D to_clk_gate(hw); + struct stm32f4_pll *pll =3D to_stm32f4_pll(gate); + struct stm32f4_pll_ssc *ssc =3D &pll->ssc_conf; + u32 modeper, incstep; + u32 sscgr; + + sscgr =3D readl(base + STM32F4_RCC_SSCGR); + /* reserved field must be kept at reset value */ + sscgr &=3D STM32F4_RCC_SSCGR_RESERVED_MASK; + + modeper =3D DIV_ROUND_CLOSEST(parent_rate, 4 * ssc->mod_freq); + incstep =3D DIV_ROUND_CLOSEST(((1 << 15) - 1) * ssc->mod_depth * ndiv, + 5 * 10000 * modeper); + sscgr |=3D STM32F4_RCC_SSCGR_SSCGEN | + FIELD_PREP(STM32F4_RCC_SSCGR_INCSTEP_MASK, incstep) | + FIELD_PREP(STM32F4_RCC_SSCGR_MODPER_MASK, modeper); + + if (ssc->mod_type) + sscgr |=3D STM32F4_RCC_SSCGR_SPREADSEL; + + pr_debug("%s: pll: %s: modeper: %d, incstep: %d, sscgr: 0x%08x\n", + __func__, clk_hw_get_name(hw), modeper, incstep, sscgr); + writel(sscgr, base + STM32F4_RCC_SSCGR); +} + static int stm32f4_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { @@ -683,6 +732,9 @@ static int stm32f4_pll_set_rate(struct clk_hw *hw, unsi= gned long rate, =20 writel(val, base + pll->offset); =20 + if (pll->ssc_enable) + stm32f4_pll_set_ssc(hw, parent_rate, n); + if (pll_state) stm32f4_pll_enable(hw); =20 @@ -788,6 +840,87 @@ static struct clk_hw *clk_register_pll_div(const char = *name, return hw; } =20 +static int stm32f4_pll_init_ssc(struct clk_hw *hw, struct stm32f4_pll_ssc = *conf) +{ + struct clk_gate *gate =3D to_clk_gate(hw); + struct stm32f4_pll *pll =3D to_stm32f4_pll(gate); + struct clk_hw *parent; + unsigned long parent_rate; + int pll_state; + unsigned long n, val; + + parent =3D clk_hw_get_parent(hw); + if (!parent) { + pr_err("%s: failed to get clock parent\n", __func__); + return -ENODEV; + } + + parent_rate =3D clk_hw_get_rate(parent); + + pll->ssc_enable =3D true; + memcpy(&pll->ssc_conf, conf, sizeof(pll->ssc_conf)); + + pll_state =3D stm32f4_pll_is_enabled(hw); + + if (pll_state) + stm32f4_pll_disable(hw); + + val =3D readl(base + pll->offset); + n =3D FIELD_GET(STM32F4_RCC_PLLCFGR_N_MASK, val); + + pr_debug("%s: pll: %s, parent: %s, parent-rate: %lu, n: %lu\n", + __func__, clk_hw_get_name(hw), clk_hw_get_name(parent), + parent_rate, n); + + stm32f4_pll_set_ssc(hw, parent_rate, n); + + if (pll_state) + stm32f4_pll_enable(hw); + + return 0; +} + +static int stm32f4_pll_ssc_parse_dt(struct device_node *np, + struct stm32f4_pll_ssc *conf) +{ + int ret; + const char *s; + + if (!conf) + return -EINVAL; + + ret =3D of_property_read_u32(np, "st,ssc-modfreq-hz", &conf->mod_freq); + if (ret) + return ret; + + ret =3D of_property_read_u32(np, "st,ssc-moddepth-permyriad", + &conf->mod_depth); + if (ret) { + pr_err("%pOF: missing st,ssc-moddepth-permyriad\n", np); + return ret; + } + + ret =3D of_property_read_string(np, "st,ssc-modmethod", &s); + if (ret) { + pr_err("%pOF: missing st,ssc-modmethod\n", np); + return ret; + } + + if (!strcmp(s, "down-spread")) { + conf->mod_type =3D STM32F4_PLL_SSC_DOWN_SPREAD; + } else if (!strcmp(s, "center-spread")) { + conf->mod_type =3D STM32F4_PLL_SSC_CENTER_SPREAD; + } else { + pr_err("%pOF: wrong value (%s) for fsl,ssc-modmethod\n", np, s); + return -EINVAL; + } + + pr_debug("%pOF: SSCG settings: mod_freq: %d, mod_depth: %d mod_method: %s= [%d]\n", + np, conf->mod_freq, conf->mod_depth, s, conf->mod_type); + + return 0; +} + static struct clk_hw *stm32f4_rcc_register_pll(const char *pllsrc, const struct stm32f4_pll_data *data, spinlock_t *lock) { @@ -1695,7 +1828,8 @@ static void __init stm32f4_rcc_init(struct device_nod= e *np) const struct of_device_id *match; const struct stm32f4_clk_data *data; unsigned long pllm; - struct clk_hw *pll_src_hw; + struct clk_hw *pll_src_hw, *pll_vco_hw; + struct stm32f4_pll_ssc ssc_conf; =20 base =3D of_iomap(np, 0); if (!base) { @@ -1754,8 +1888,8 @@ static void __init stm32f4_rcc_init(struct device_nod= e *np) clk_hw_register_fixed_factor(NULL, "vco_in", pll_src, 0, 1, pllm); =20 - stm32f4_rcc_register_pll("vco_in", &data->pll_data[0], - &stm32f4_clk_lock); + pll_vco_hw =3D stm32f4_rcc_register_pll("vco_in", &data->pll_data[0], + &stm32f4_clk_lock); =20 clks[PLL_VCO_I2S] =3D stm32f4_rcc_register_pll("vco_in", &data->pll_data[1], &stm32f4_clk_lock); @@ -1900,6 +2034,9 @@ static void __init stm32f4_rcc_init(struct device_nod= e *np) =20 of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL); =20 + if (!stm32f4_pll_ssc_parse_dt(np, &ssc_conf)) + stm32f4_pll_init_ssc(pll_vco_hw, &ssc_conf); + return; fail: kfree(clks); --=20 2.43.0