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Sun, 05 Jan 2025 02:01:34 -0800 (PST) From: Ivan Sergeev Date: Sun, 05 Jan 2025 13:01:28 +0300 Subject: [PATCH v5 1/2] dt-bindings: arm: rockchip: Add BigTreeTech CB2 and Pi2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250105-bigtreetech-cb2-v5-1-923f911b10c0@gmail.com> References: <20250105-bigtreetech-cb2-v5-0-923f911b10c0@gmail.com> In-Reply-To: <20250105-bigtreetech-cb2-v5-0-923f911b10c0@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Ivan Sergeev , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1174; i=ivan8215145640@gmail.com; h=from:subject:message-id; bh=p5DkTJDu5QlNVWl35gjaVUthknkZBv6iZeP84hntyqE=; b=owEBbQKS/ZANAwAIAbzfXRlQM5b9AcsmYgBnelh8wbKwjV0jSnORnKj5gri6tWjV1nKWx9W3i G5KSaDFdBiJAjMEAAEIAB0WIQROCZtApKFz1fvvsOS8310ZUDOW/QUCZ3pYfAAKCRC8310ZUDOW /VAFEADFqODzeMLOEs3mBaz1dwUu5ZF5X1/KDWLNtr77NscD0wHI0qzttXH04B59w11+Iz0vDHT 9QOB2jXHT6we52Vwlic38wD6K8e7vRYjuyY/XVjMAwG/vBVhAE//TNRlngowg2Qv1F7s9KFlIBI BMTLSugnG+t0MDgxOBbmMqLoBU64p8kVCFeav+7KSgilDEJGmjoo4e5DY7lypHbJIK3/5DY89A1 Dy60cV0GQT9lvj89AcXi6Pg4qUaWJPQscREDN5qzA8RmSUXy06y0SItzB7g4sSq6nBS+JJGIJ2E OCEvKGSchJenHCT73iEWKSQQ3N7sS3woilffxgHkb3JeUg5q+un4Ci2IL36KypjDo/TIrR2MYmp q50GR+NM4aMOIgOIX9IEAfhVqHD9pNHK1W5m09Gt1rDlO+oEN7+wBR4fdKTVJYnedZQNhsEyNYR 5H8A4YHGrprOQLWsTTs6XAWVuQNFg5W8lJ/tAV4Mr3xOS3zhfiNOB0oIGmTbk1tM06JYNwfaC7H SbVdssc7BJftFz5hgqHxc7wvtDEgDVA6FuWnSKJLZXeLFe15KhFAjp5WOebWFjBm1Voyd744YAn NDTk1KBnvEUp5QHrHgxwKIef5I+UmBAc3KvavlzhCm1Dtx7hWqBji8zANxDqk+As192n18zhD6H IMDVC2E08q6+W+w== X-Developer-Key: i=ivan8215145640@gmail.com; a=openpgp; fpr=4E099B40A4A173D5FBEFB0E4BCDF5D19503396FD BigTreeTech CB2 and Pi2 are Rockchip RK3566 based boards Acked-by: Krzysztof Kozlowski Signed-off-by: Ivan Sergeev --- Documentation/devicetree/bindings/arm/rockchip.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 753199a12923fadaa48c407a8e55e7854db7203e..349453b1676bfac45abf5cd49d6= bd9f847281213 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -81,6 +81,17 @@ properties: - const: azw,beelink-a1 - const: rockchip,rk3328 =20 + - description: BigTreeTech CB2 Manta M4/8P + items: + - const: bigtreetech,cb2-manta + - const: bigtreetech,cb2 + - const: rockchip,rk3566 + + - description: BigTreeTech Pi 2 + items: + - const: bigtreetech,pi2 + - const: rockchip,rk3566 + - description: bq Curie 2 tablet items: - const: mundoreader,bq-curie2 --=20 2.45.2 From nobody Thu Feb 12 20:15:30 2026 Received: from mail-lf1-f46.google.com (mail-lf1-f46.google.com [209.85.167.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E523B1B960; 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Sun, 05 Jan 2025 02:01:36 -0800 (PST) Received: from JetTurbine.homenetwork ([2a0e:e6c0:20d3:2100::1d]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54223813806sm4580828e87.114.2025.01.05.02.01.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Jan 2025 02:01:34 -0800 (PST) From: Ivan Sergeev Date: Sun, 05 Jan 2025 13:01:29 +0300 Subject: [PATCH v5 2/2] arm64: dts: rockchip: Add BigTreeTech CB2 and Pi2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250105-bigtreetech-cb2-v5-2-923f911b10c0@gmail.com> References: <20250105-bigtreetech-cb2-v5-0-923f911b10c0@gmail.com> In-Reply-To: <20250105-bigtreetech-cb2-v5-0-923f911b10c0@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Ivan Sergeev X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=4E099B40A4A173D5FBEFB0E4BCDF5D19503396FD BigTreeTech CB2 and Pi2 share a lot of hardware configuration, so a common dtsi file was used to define common nodes and properties. This is similar to how BigTreeTech CB1 and Pi are implemented. Signed-off-by: Ivan Sergeev --- arch/arm64/boot/dts/rockchip/Makefile | 2 + .../dts/rockchip/rk3566-bigtreetech-cb2-manta.dts | 10 + .../boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi | 919 +++++++++++++++++= ++++ .../boot/dts/rockchip/rk3566-bigtreetech-pi2.dts | 10 + 4 files changed, 941 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 86cc418a2255cdc22f1d503e9519d2d9572d4e9d..99266316a6003e5a8a4dadbd05b= 8453beb2c3efc 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -111,6 +111,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-box-demo.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-lckfb-tspi.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-lubancat-1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-nanopi-r3s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-bigtreetech-cb2-manta.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-bigtreetech-pi2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-fastrhino-r66s.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2-manta.dts = b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2-manta.dts new file mode 100644 index 0000000000000000000000000000000000000000..97415d099d886aba97c9b652af3= d03573f5e74d7 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2-manta.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-bigtreetech-cb2.dtsi" + +/ { + model =3D "BigTreeTech CB2"; + compatible =3D "bigtreetech,cb2-manta", "bigtreetech,cb2", "rockchip,rk35= 66"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi b/arc= h/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..8f528dfd427621c287bfecbaebf= ad3ad302b44a5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi @@ -0,0 +1,919 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3566.dtsi" + +/ { + aliases { + ethernet0 =3D &gmac1; + mmc0 =3D &sdhci; + mmc1 =3D &sdmmc0; + }; + + chosen: chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + fan: pwm-fan { + compatible =3D "pwm-fan"; + #cooling-cells =3D <2>; + pwms =3D <&pwm7 0 50000 0>; + cooling-levels =3D <0 50 100 150 200 255>; + }; + + hdmi-con { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint =3D <&hdmi_out_con>; + }; + }; + }; + + leds: leds { + compatible =3D "gpio-leds"; + + led-0 { + gpios =3D <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; + function =3D LED_FUNCTION_POWER; + color =3D ; + linux,default-trigger =3D "default-on"; + pinctrl-names =3D "default"; + pinctrl-0 =3D<&blue_led>; + }; + + led-1 { + gpios =3D <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + function =3D LED_FUNCTION_HEARTBEAT; + color =3D ; + linux,default-trigger =3D "heartbeat"; + pinctrl-names =3D "default"; + pinctrl-0 =3D<&heartbeat_led>; + }; + }; + + rk809-sound { + compatible =3D "simple-audio-card"; + simple-audio-card,format =3D "i2s"; + simple-audio-card,name =3D "Analog RK809"; + simple-audio-card,mclk-fs =3D <256>; + + simple-audio-card,cpu { + sound-dai =3D <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai =3D <&rk809>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + clocks =3D <&rk809 1>; + clock-names =3D "ext_clock"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_enable_h>; + post-power-on-delay-ms =3D <200>; + reset-gpios =3D <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + vcc_5v: regulator-vcc-5v { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vbus: regulator-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "vbus"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + vcc3v3_pcie: regulator-vcc3v3-pcie { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_pcie"; + enable-active-high; + gpios =3D <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_drv>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vbus>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vbus>; + }; + + vcc5v0_usb: regulator-vcc5v0-usb { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vbus>; + }; + + vcc_sd: regulator-vcc-sd { + compatible =3D "regulator-fixed"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "vcc_sd"; + vin-supply =3D <&vcc3v3_sys>; + }; + + vcc5v0_host: regulator-vcc5v0-host { + compatible =3D "regulator-fixed"; + enable-active-high; + gpios =3D <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_host_en>; + regulator-name =3D "vcc5v0_host3"; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + vcc5v0_otg: regulator-vcc5v0-otg { + compatible =3D "regulator-fixed"; + enable-active-high; + gpios =3D <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_otg_en>; + regulator-name =3D "vcc5v0_otg3"; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + vcc5v0_usb2t: regulator-vcc5v0-usb2t { + compatible =3D "regulator-fixed"; + enable-active-high; + gpios =3D <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_usb2t_en>; + regulator-name =3D "vcc5v0_usb2t"; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + vcc5v0_usb2b: regulator-vcc5v0-usb2b { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_usb2b_en>; + regulator-name =3D "vcc5v0_usb2b"; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + ext_cam_clk: ext-cam-clk { + status =3D "okay"; + compatible =3D "fixed-clock"; + clock-frequency =3D <25000000>; + clock-output-names =3D "ext_cam_clk"; + #clock-cells =3D <0>; + }; + + can_mcp2515_osc: can-mcp2515-osc { + compatible =3D "fixed-clock"; + clock-frequency =3D <8000000>; + #clock-cells =3D <0>; + }; +}; + +&combphy1 { + status =3D "okay"; +}; + +&combphy2 { + status =3D "okay"; +}; + +&cpu0 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply =3D <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks =3D <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents =3D <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_= 2TOP>; + assigned-clock-rates =3D <0>, <125000000>; + clock_in_out =3D "input"; + phy-mode =3D "rgmii-id"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; + phy-handle =3D <&rgmii_phy0>; + status =3D "okay"; +}; + +&mdio1 { + rgmii_phy0: phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reset-gpios =3D <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; + reset-delay-us =3D <20000>; + reset-post-delay-us =3D <100000>; + reg =3D <0x0>; + }; +}; + +&gpu { + mali-supply =3D <&vdd_gpu>; + status =3D "okay"; +}; + +&hdmi { + avdd-0v9-supply =3D <&vdda0v9_image>; + avdd-1v8-supply =3D <&vcca1v8_image>; + status =3D "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint =3D <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; + + vdd_cpu: regulator@1c { + compatible =3D "tcs,tcs4525"; + reg =3D <0x1c>; + vin-supply =3D <&vcc5v0_sys>; + regulator-name =3D "vdd_cpu"; + regulator-min-microvolt =3D <712500>; + regulator-max-microvolt =3D <1390000>; + regulator-initial-mode =3D <1>; + regulator-ramp-delay =3D <2300>; + fcs,suspend-voltage-selector =3D <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible =3D "rockchip,rk809"; + reg =3D <0x20>; + interrupt-parent =3D <&gpio0>; + interrupts =3D <3 IRQ_TYPE_LEVEL_LOW>; + + assigned-clocks =3D <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents =3D <&cru CLK_I2S1_8CH_TX>; + #clock-cells =3D <1>; + clock-names =3D "mclk"; + clocks =3D <&cru I2S1_MCLKOUT_TX>; + pinctrl-names =3D "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 =3D <&pmic_int>, <&i2s1m0_mclk>; + #sound-dai-cells =3D <0>; + + system-power-controller; + wakeup-source; + + vcc1-supply =3D <&vcc3v3_sys>; + vcc2-supply =3D <&vcc3v3_sys>; + vcc3-supply =3D <&vcc3v3_sys>; + vcc4-supply =3D <&vcc3v3_sys>; + vcc5-supply =3D <&vcc3v3_sys>; + vcc6-supply =3D <&vcc3v3_sys>; + vcc7-supply =3D <&vcc3v3_sys>; + vcc8-supply =3D <&vcc3v3_sys>; + vcc9-supply =3D <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + regulator-initial-mode =3D <0x2>; + regulator-name =3D "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + regulator-initial-mode =3D <0x2>; + regulator-name =3D "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode =3D <0x2>; + regulator-name =3D "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + regulator-initial-mode =3D <0x2>; + regulator-name =3D "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-name =3D "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + codec { + rockchip,mic-in-differential; + }; + }; +}; + +&i2c2 { + pinctrl-0 =3D <&i2c2m1_xfer>; +}; + +&i2c3 { + status =3D "okay"; + + tft_tp: touchscreen@48 { + compatible =3D "ti,tsc2007"; + reg =3D <0x48>; + status =3D "okay"; + ti,x-plate-ohms =3D <660>; + ti,rt-thr =3D <3000>; + ti,fuzzx =3D <32>; + ti,fuzzy =3D <16>; + }; +}; + +&i2s0_8ch { + status =3D "okay"; +}; + +&i2s1_8ch { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status =3D "okay"; +}; + +&spi1 { + pinctrl-0 =3D <&spi1m1_cs0 &spi1m1_pins>; + + can_mcp2515: can@0 { + compatible =3D "microchip,mcp2515"; + reg =3D <0x00>; + interrupt-parent =3D <&gpio4>; + interrupts =3D <3 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency =3D <10000000>; + clocks =3D <&can_mcp2515_osc>; + vdd-supply =3D <&vcc3v3_sys>; + xceiver-supply =3D <&vcc3v3_sys>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcp2515_int_pin>; + }; +}; + +&spi3 { + pinctrl-0 =3D <&spi3m1_cs0 &spi3m1_pins>; +}; + +&pcie2x1 { + reset-gpios =3D <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_reset_h>; + vpcie3v3-supply =3D <&vcc3v3_pcie>; + status =3D "okay"; +}; + +&pinctrl { + sd { + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins =3D <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins =3D <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins =3D <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins =3D <0 RK_PA2 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins =3D <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins =3D <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake: wifi-host-wake-l { + rockchip,pins =3D <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins =3D <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins =3D <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb2t_en: vcc5v0_usb2t-en { + rockchip,pins =3D <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb2b_en: vcc5v0-usb2b-en { + rockchip,pins =3D <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + work-led { + heartbeat_led: led-heartbeat { + rockchip,pins =3D <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + blue_led: led-blue { + rockchip,pins =3D <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins =3D <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pcie { + pcie_drv: pcie-drv { + rockchip,pins =3D <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_reset_h: pcie-reset-h { + rockchip,pins =3D <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + edp { + edp_hpd: edp-hpd { + rockchip,pins =3D <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl_en: bl-en { + rockchip,pins =3D <0 RK_PB5 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + bt { + bt_enable: bt-enable-h { + rockchip,pins =3D <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_host_wake: bt-host-wake-l { + rockchip,pins =3D <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake: bt-wake-l { + rockchip,pins =3D <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + mcp2515_int_pin { + mcp2515_int_pin: mcp2515-int-pin { + rockchip,pins =3D <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + status =3D "okay"; + pmuio1-supply =3D <&vcc3v3_pmu>; + pmuio2-supply =3D <&vcc3v3_pmu>; + vccio1-supply =3D <&vcc_3v3>; + vccio2-supply =3D <&vcc_1v8>; + vccio3-supply =3D <&vccio_sd>; + vccio4-supply =3D <&vcc_1v8>; + vccio5-supply =3D <&vcc_3v3>; + vccio6-supply =3D <&vcc_3v3>; + vccio7-supply =3D <&vcc_3v3>; +}; + +&pwm0 { + pinctrl-0 =3D <&pwm0m1_pins>; +}; + +&pwm7 { + status =3D "disabled"; +}; + +&pwm12 { + pinctrl-0 =3D <&pwm12m1_pins>; +}; + +&pwm13 { + pinctrl-0 =3D <&pwm13m1_pins>; +}; + +&pwm14 { + pinctrl-0 =3D <&pwm14m1_pins>; +}; + +&pwm15 { + pinctrl-0 =3D <&pwm15m1_pins>; +}; + +&saradc { + status =3D "okay"; + vref-supply =3D <&vcca_1v8>; +}; + +&sdhci { + bus-width =3D <8>; + max-frequency =3D <200000000>; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&emmc_bus8 &emmc_clk &emmc_cmd>; + status =3D "okay"; +}; + +&sdmmc0 { + max-frequency =3D <150000000>; + bus-width =3D <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + vmmc-supply =3D <&vcc_sd>; + vqmmc-supply =3D <&vccio_sd>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status =3D "okay"; +}; + +&sdmmc1 { + /* WiFi & BT combo module AMPAK AP6256 */ + #address-cells =3D <1>; + #size-cells =3D <0>; + max-frequency =3D <150000000>; + bus-width =3D <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq =3D <&sdio_pwrseq>; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + rockchip,default-sample-phase =3D <90>; + status =3D "okay"; + + sdio-wifi@1 { + compatible =3D "brcm,bcm4329-fmac"; + reg =3D <1>; + interrupt-parent =3D <&gpio2>; + interrupts =3D <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "host-wake"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_host_wake>; + brcm,drive-strength =3D <10>; + }; +}; + +&sfc { + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; +}; + +&tsadc { + status =3D "okay"; +}; + +&uart1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + dma-names =3D "tx","rx"; + + bluetooth { + compatible =3D "brcm,bcm4345c5"; + clocks =3D <&rk809 1>; + clock-names =3D "lpo"; + device-wakeup-gpios =3D <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios =3D <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + shutdown-gpios =3D <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&bt_host_wake &bt_wake &bt_enable>; + vbat-supply =3D <&vcc3v3_sys>; + vddio-supply =3D <&vcca1v8_pmu>; + }; +}; + +&uart2 { + status =3D "okay"; +}; + +&uart5 { + pinctrl-0 =3D <&uart5m1_xfer>; +}; + +&uart7 { + pinctrl-0 =3D <&uart7m2_xfer>; +}; + +&usb2phy0 { + status =3D "okay"; +}; + +&usb2phy0_host { + phy-supply =3D <&vcc5v0_host>; + status =3D "okay"; +}; + +&usb2phy0_otg { + phy-supply =3D <&vcc5v0_otg>; + status =3D "okay"; +}; + +&usb2phy1 { + status =3D "okay"; +}; + +&usb2phy1_host { + phy-supply =3D <&vcc5v0_usb2t>; + status =3D "okay"; +}; + +&usb2phy1_otg { + phy-supply =3D <&vcc5v0_usb2b>; + status =3D "okay"; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&usb_host0_xhci { + dr_mode =3D "host"; + extcon =3D <&usb2phy0>; + status =3D "okay"; +}; + +&usb_host1_ehci { + status =3D "okay"; +}; + +&usb_host1_ohci { + status =3D "okay"; +}; + +&usb_host1_xhci { + status =3D "okay"; +}; + +&vop { + assigned-clocks =3D <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents =3D <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status =3D "okay"; +}; + +&vop_mmu { + status =3D "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg =3D ; + remote-endpoint =3D <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-pi2.dts b/arch= /arm64/boot/dts/rockchip/rk3566-bigtreetech-pi2.dts new file mode 100644 index 0000000000000000000000000000000000000000..7cd444caa18bc9f6cf7afe04a77= 7aecdce2fc93e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-pi2.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-bigtreetech-cb2.dtsi" + +/ { + model =3D "BigTreeTech Pi 2"; + compatible =3D "bigtreetech,pi2", "rockchip,rk3566"; +}; --=20 2.45.2