From nobody Wed Feb 11 08:37:29 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9A5F11FC7DA; Fri, 3 Jan 2025 18:16:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735928211; cv=none; b=YMfG3x+RLQ3gDCg+aJLddZhDZaZpTQqgJJ7xXw52rH30jMAYho3C9euqwfoT5KSL4iJRq4GRgC0GlzgiVrzDxRSq7caJ65iR5P6aIi4C8k/NUmDVj4xpdrJyl+EekWOPW8EDSxgyh2+d8NY8h+TzILCfY80V54n5I/fSRYqhxZs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735928211; c=relaxed/simple; bh=FpOYtp+Gobi2p79XP2kkX0uxilorrMJxF0WI+r186rc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=D/zmxgm3R3TlCQLJoejP8bW+sGYYWblKsq/aNN4hr4OlffKGRaYAgf8hHSUVXkfPXlBEpzDMbxdW7ymVVsSA3dLLJCquPv24455+Uw6SWF93GMZROe6uSBwKhskfw0r4bfdYLEiuQna2v5sCanOTLpy/563/LrP1cQ97FJY6uJg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0AB951C01; Fri, 3 Jan 2025 10:17:16 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8D3B53F673; Fri, 3 Jan 2025 10:16:45 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King Subject: [PATCH v4 2/4] arm64: dts: morello: Add support for common functionalities Date: Fri, 3 Jan 2025 18:16:21 +0000 Message-ID: <20250103181623.1980433-3-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250103181623.1980433-1-vincenzo.frascino@arm.com> References: <20250103181623.1980433-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share some functionalities that have conveniently been included in morello.dtsi to avoid duplication. Introduce morello.dtsi. Note: Morello fvp will be introduced with a future patch series. Signed-off-by: Vincenzo Frascino --- arch/arm64/boot/dts/arm/morello.dtsi | 467 +++++++++++++++++++++++++++ 1 file changed, 467 insertions(+) create mode 100644 arch/arm64/boot/dts/arm/morello.dtsi diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm= /morello.dtsi new file mode 100644 index 000000000000..0089b4f2eca7 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello.dtsi @@ -0,0 +1,467 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. + */ + +#include + +/ { + interrupt-parent =3D <&gic>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + clocks { + soc_refclk50mhz: clock-50000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <50000000>; + clock-output-names =3D "apb_pclk"; + }; + + soc_uartclk: clock-50000000-uart { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <50000000>; + clock-output-names =3D "uartclk"; + }; + + soc_refclk85mhz: clock-85000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <85000000>; + clock-output-names =3D "iofpga:aclk"; + }; + + dpu_aclk: clock-350000000 { + /* 77.1 MHz derived from 24 MHz reference clock */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <350000000>; + clock-output-names =3D "aclk"; + }; + + dpu_pixel_clk: clock-148500000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <148500000>; + clock-output-names =3D "pxclk"; + }; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "arm,neoverse-n1"; + reg =3D <0x0 0x0>; + device_type =3D "cpu"; + enable-method =3D "psci"; + /* 4 ways set associative */ + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <512>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_0>; + clocks =3D <&scmi_dvfs 0>; + + l2_0: l2-cache-0 { + compatible =3D "cache"; + cache-level =3D <2>; + /* 8 ways set associative */ + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; + cache-unified; + next-level-cache =3D <&l3_0>; + + l3_0: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-size =3D <0x100000>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + compatible =3D "arm,neoverse-n1"; + reg =3D <0x0 0x100>; + device_type =3D "cpu"; + enable-method =3D "psci"; + /* 4 ways set associative */ + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <512>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_1>; + clocks =3D <&scmi_dvfs 0>; + + l2_1: l2-cache-1 { + compatible =3D "cache"; + cache-level =3D <2>; + /* 8 ways set associative */ + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu2: cpu@10000 { + compatible =3D "arm,neoverse-n1"; + reg =3D <0x0 0x10000>; + device_type =3D "cpu"; + enable-method =3D "psci"; + /* 4 ways set associative */ + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <512>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_2>; + clocks =3D <&scmi_dvfs 1>; + + l2_2: l2-cache-2 { + compatible =3D "cache"; + cache-level =3D <2>; + /* 8 ways set associative */ + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu3: cpu@10100 { + compatible =3D "arm,neoverse-n1"; + reg =3D <0x0 0x10100>; + device_type =3D "cpu"; + enable-method =3D "psci"; + /* 4 ways set associative */ + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <512>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_3>; + clocks =3D <&scmi_dvfs 1>; + + l2_3: l2-cache-3 { + compatible =3D "cache"; + cache-level =3D <2>; + /* 8 ways set associative */ + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + }; + + firmware { + interrupt-parent =3D <&gic>; + + scmi { + compatible =3D "arm,scmi"; + mbox-names =3D "tx", "rx"; + mboxes =3D <&mailbox 1 0>, <&mailbox 1 1>; + shmem =3D <&cpu_scp_hpri0>, <&cpu_scp_hpri1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_dvfs: protocol@13 { + reg =3D <0x13>; + #clock-cells =3D <1>; + }; + + scmi_clk: protocol@14 { + reg =3D <0x14>; + #clock-cells =3D <1>; + }; + }; + }; + + /* The first bank of memory, memory map is actually provided by UEFI. */ + memory@80000000 { + device_type =3D "memory"; + /* [0x80000000-0xffffffff] */ + reg =3D <0x00000000 0x80000000 0x0 0x7f000000>; + }; + + memory@8080000000 { + device_type =3D "memory"; + /* [0x8080000000-0x83f7ffffff] */ + reg =3D <0x00000080 0x80000000 0x3 0x78000000>; + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + secure-firmware@ff000000 { + reg =3D <0x0 0xff000000 0x0 0x01000000>; + no-map; + }; + }; + + spe-pmu { + compatible =3D "arm,statistical-profiling-extension-v1"; + interrupts =3D ; + }; + + soc: soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + ranges; + + dp0: display@2cc00000 { + compatible =3D "arm,mali-d32", "arm,mali-d71"; + reg =3D <0x0 0x2cc00000 0x0 0x20000>; + interrupts =3D <0 69 4>; + clocks =3D <&dpu_aclk>; + clock-names =3D "aclk"; + iommus =3D <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>, + <&smmu_dp 8>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + pl0: pipeline@0 { + reg =3D <0>; + clocks =3D <&dpu_pixel_clk>; + clock-names =3D "pxclk"; + port { + dp_pl0_out0: endpoint { + remote-endpoint =3D <&tda998x_0_input>; + }; + }; + }; + }; + + i2c0: i2c@1c0f0000 { + compatible =3D "cdns,i2c-r1p14"; + reg =3D <0x0 0x1c0f0000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&dpu_aclk>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + hdmi_tx: hdmi-transmitter@70 { + compatible =3D "nxp,tda998x"; + reg =3D <0x70>; + video-ports =3D <0x234501>; + port { + tda998x_0_input: endpoint { + remote-endpoint =3D <&dp_pl0_out0>; + }; + }; + }; + }; + + gic: interrupt-controller@2c010000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x30000000 0x0 0x10000>, /* GICD */ + <0x0 0x300c0000 0x0 0x80000>; /* GICR */ + + interrupts =3D ; + + #interrupt-cells =3D <3>; + interrupt-controller; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + its1: msi-controller@30040000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x30040000 0x0 0x20000>; + + msi-controller; + #msi-cells =3D <1>; + }; + + its2: msi-controller@30060000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x30060000 0x0 0x20000>; + + msi-controller; + #msi-cells =3D <1>; + }; + + its_ccix: msi-controller@30080000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x30080000 0x0 0x20000>; + + msi-controller; + #msi-cells =3D <1>; + }; + + its_pcie: msi-controller@300a0000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x300a0000 0x0 0x20000>; + + msi-controller; + #msi-cells =3D <1>; + }; + }; + + smmu_dp: iommu@2ce00000 { + compatible =3D "arm,smmu-v3"; + reg =3D <0x0 0x2ce00000 0x0 0x40000>; + + interrupts =3D , + , + ; + interrupt-names =3D "eventq", "gerror", "cmdq-sync"; + #iommu-cells =3D <1>; + }; + + smmu_ccix: iommu@4f000000 { + compatible =3D "arm,smmu-v3"; + reg =3D <0x0 0x4f000000 0x0 0x40000>; + + interrupts =3D , + , + , + ; + interrupt-names =3D "eventq", "gerror", "priq", "cmdq-sync"; + msi-parent =3D <&its1 0>; + #iommu-cells =3D <1>; + dma-coherent; + }; + + smmu_pcie: iommu@4f400000 { + compatible =3D "arm,smmu-v3"; + reg =3D <0x0 0x4f400000 0x0 0x40000>; + + interrupts =3D , + , + , + ; + interrupt-names =3D "eventq", "gerror", "priq", "cmdq-sync"; + msi-parent =3D <&its2 0>; + #iommu-cells =3D <1>; + dma-coherent; + }; + + mailbox: mhu@45000000 { + compatible =3D "arm,mhu-doorbell", "arm,primecell"; + reg =3D <0x0 0x45000000 0x0 0x1000>; + + interrupts =3D , + ; + #mbox-cells =3D <2>; + clocks =3D <&soc_refclk50mhz>; + clock-names =3D "apb_pclk"; + }; + + pcie_ctlr: pcie@28c0000000 { + device_type =3D "pci"; + compatible =3D "pci-host-ecam-generic"; + reg =3D <0x28 0xC0000000 0 0x10000000>; + ranges =3D <0x01000000 0x00 0x00000000 0x00 0x6f000000 0x00 0x00800000>, + <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0f000000>, + <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1f 0xc0000000>; + bus-range =3D <0 255>; + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + dma-coherent; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>; + msi-map =3D <0 &its_pcie 0 0x10000>; + iommu-map =3D <0 &smmu_pcie 0 0x10000>; + }; + + ccix_pcie_ctlr: pcie@4fc0000000 { + device_type =3D "pci"; + compatible =3D "pci-host-ecam-generic"; + reg =3D <0x4f 0xC0000000 0 0x10000000>; + ranges =3D <0x01000000 0x00 0x00000000 0x00 0x7f000000 0x00 0x00800000>, + <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0f000000>, + <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1f 0xc0000000>; + bus-range =3D <0 255>; + linux,pci-domain =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + dma-coherent; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>; + msi-map =3D <0 &its_ccix 0 0x10000>; + iommu-map =3D <0 &smmu_ccix 0 0x10000>; + }; + + uart0: serial@2a400000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x0 0x2a400000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&soc_uartclk>, <&soc_refclk50mhz>; + clock-names =3D "uartclk", "apb_pclk"; + + status =3D "disabled"; + }; + + sram: sram@45200000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0x06000000 0x0 0x8000>; + ranges =3D <0 0x0 0x06000000 0x8000>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpu_scp_hpri0: scp-sram@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x80>; + }; + + cpu_scp_hpri1: scp-sram@80 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x80 0x80>; + }; + }; + + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; +}; --=20 2.43.0