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([82.78.167.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0e8953b6sm1932984066b.65.2025.01.03.08.38.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jan 2025 08:38:37 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, ulf.hansson@linaro.org Cc: claudiu.beznea@tuxon.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 5/6] arm64: dts: renesas: r9a08g045: Add TSU node Date: Fri, 3 Jan 2025 18:38:04 +0200 Message-ID: <20250103163805.1775705-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> References: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add TSU node along with thermal zones and keep it enabled in the SoC DTSI. The temperature reported by the TSU can only be read through channel 8 of the ADC. Therefore, enable the ADC by default. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 43 ++++++++++++++++++- .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 -- 2 files changed, 42 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g045.dtsi index a9b98db9ef95..fd74138198a8 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -205,7 +205,6 @@ adc: adc@10058000 { #address-cells =3D <1>; #size-cells =3D <0>; #io-channel-cells =3D <1>; - status =3D "disabled"; =20 channel@0 { reg =3D <0>; @@ -244,6 +243,17 @@ channel@8 { }; }; =20 + tsu: thermal@10059000 { + compatible =3D "renesas,r9a08g045-tsu"; + reg =3D <0 0x10059000 0 0x1000>; + clocks =3D <&cpg CPG_MOD R9A08G045_TSU_PCLK>; + resets =3D <&cpg R9A08G045_TSU_PRESETN>; + power-domains =3D <&cpg>; + #thermal-sensor-cells =3D <0>; + io-channels =3D <&adc 8>; + io-channel-names =3D "tsu"; + }; + vbattb: clock-controller@1005c000 { compatible =3D "renesas,r9a08g045-vbattb"; reg =3D <0 0x1005c000 0 0x1000>; @@ -690,6 +700,37 @@ timer { "hyp-virt"; }; =20 + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + thermal-sensors =3D <&tsu>; + sustainable-power =3D <423>; + + cooling-maps { + map0 { + trip =3D <&target>; + cooling-device =3D <&cpu0 0 2>; + contribution =3D <1024>; + }; + }; + + trips { + sensor_crit: sensor-crit { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + + target: trip-point { + temperature =3D <100000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + }; + vbattb_xtal: vbattb-xtal { compatible =3D "fixed-clock"; #clock-cells =3D <0>; diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3s-smarc-som.dtsi index ef12c1c462a7..041d256d7b79 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -102,10 +102,6 @@ x3_clk: x3-clock { }; }; =20 -&adc { - status =3D "okay"; -}; - #if SW_CONFIG3 =3D=3D SW_ON ð0 { pinctrl-0 =3D <ð0_pins>; --=20 2.43.0