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([82.78.167.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0e8953b6sm1932984066b.65.2025.01.03.08.38.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jan 2025 08:38:29 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, ulf.hansson@linaro.org Cc: claudiu.beznea@tuxon.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 1/6] clk: renesas: r9a08g045: Add clocks, resets and power domain support for the TSU IP Date: Fri, 3 Jan 2025 18:38:00 +0200 Message-ID: <20250103163805.1775705-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> References: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add clocks, resets and power domains for the TSU IP available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a08g045-cpg.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a0= 8g045-cpg.c index 0e7e3bf05b52..bc44e08e7eb9 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -241,6 +241,7 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = =3D { DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0), DEF_MOD("adc_adclk", R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0), DEF_MOD("adc_pclk", R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1), + DEF_MOD("tsu_pclk", R9A08G045_TSU_PCLK, R9A08G045_CLK_TSU, 0x5ac, 0), DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0), }; =20 @@ -279,6 +280,7 @@ static const struct rzg2l_reset r9a08g045_resets[] =3D { DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2), DEF_RST(R9A08G045_ADC_PRESETN, 0x8a8, 0), DEF_RST(R9A08G045_ADC_ADRST_N, 0x8a8, 1), + DEF_RST(R9A08G045_TSU_PRESETN, 0x8ac, 0), DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0), }; 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([82.78.167.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0e8953b6sm1932984066b.65.2025.01.03.08.38.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jan 2025 08:38:31 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, ulf.hansson@linaro.org Cc: claudiu.beznea@tuxon.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 2/6] thermal: of: Export non-devres helper to register/unregister thermal zone Date: Fri, 3 Jan 2025 18:38:01 +0200 Message-ID: <20250103163805.1775705-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> References: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea On the Renesas RZ/G3S (and other Renesas SoCs, e.g., RZ/G2{L, LC, UL}), clocks are managed through PM domains. These PM domains, registered on behalf of the clock controller driver, are configured with GENPD_FLAG_PM_CLK. In most of the Renesas drivers used by RZ SoCs, the clocks are enabled/disabled using runtime PM APIs. During probe, devices are attached to the PM domain controlling their clocks. Similarly, during removal, devices are detached from the PM domain. The detachment call stack is as follows: device_driver_detach() -> device_release_driver_internal() -> __device_release_driver() -> device_remove() -> platform_remove() -> dev_pm_domain_detach() In the upcoming Renesas RZ/G3S thermal driver, the struct thermal_zone_device_ops::change_mode API is implemented to start/stop the thermal sensor unit. Register settings are updated within the change_mode API. In case devres helpers are used for thermal zone register/unregister the struct thermal_zone_device_ops::change_mode API is invoked when the driver is unbound. The identified call stack is as follows: device_driver_detach() -> device_release_driver_internal() -> device_unbind_cleanup() -> devres_release_all() -> devm_thermal_of_zone_release() -> thermal_zone_device_disable() -> thermal_zone_device_set_mode() -> rzg3s_thermal_change_mode() The device_unbind_cleanup() function is called after the thermal device is detached from the PM domain (via dev_pm_domain_detach()). The rzg3s_thermal_change_mode() implementation calls pm_runtime_resume_and_get()/pm_runtime_put_autosuspend() before/after accessing the registers. However, during the unbind scenario, the devm_thermal_of_zone_release() is invoked after dev_pm_domain_detach(). Consequently, the clocks are not enabled, as the device is removed from the PM domain at this time, leading to an Asynchronous SError Interrupt. The system cannot be used after this. Add thermal_of_zone_register()/thermal_of_zone_unregister(). These will be used in the upcomming RZ/G3S thermal driver. Signed-off-by: Claudiu Beznea Reviewed-by: Ulf Hansson --- drivers/thermal/thermal_of.c | 8 +++++--- include/linux/thermal.h | 14 ++++++++++++++ 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/thermal/thermal_of.c b/drivers/thermal/thermal_of.c index fab11b98ca49..8fc35d20db60 100644 --- a/drivers/thermal/thermal_of.c +++ b/drivers/thermal/thermal_of.c @@ -329,11 +329,12 @@ static bool thermal_of_should_bind(struct thermal_zon= e_device *tz, * * @tz: a pointer to the thermal zone structure */ -static void thermal_of_zone_unregister(struct thermal_zone_device *tz) +void thermal_of_zone_unregister(struct thermal_zone_device *tz) { thermal_zone_device_disable(tz); thermal_zone_device_unregister(tz); } +EXPORT_SYMBOL_GPL(thermal_of_zone_unregister); =20 /** * thermal_of_zone_register - Register a thermal zone with device node @@ -355,8 +356,8 @@ static void thermal_of_zone_unregister(struct thermal_z= one_device *tz) * - ENOMEM: if one structure can not be allocated * - Other negative errors are returned by the underlying called functions */ -static struct thermal_zone_device *thermal_of_zone_register(struct device_= node *sensor, int id, void *data, - const struct thermal_zone_device_ops *ops) +struct thermal_zone_device *thermal_of_zone_register(struct device_node *s= ensor, int id, void *data, + const struct thermal_zone_device_ops *ops) { struct thermal_zone_device_ops of_ops =3D *ops; struct thermal_zone_device *tz; @@ -429,6 +430,7 @@ static struct thermal_zone_device *thermal_of_zone_regi= ster(struct device_node * =20 return ERR_PTR(ret); } +EXPORT_SYMBOL_GPL(thermal_of_zone_register); =20 static void devm_thermal_of_zone_release(struct device *dev, void *res) { diff --git a/include/linux/thermal.h b/include/linux/thermal.h index 69f9bedd0ee8..adbb4092a064 100644 --- a/include/linux/thermal.h +++ b/include/linux/thermal.h @@ -195,13 +195,23 @@ struct thermal_zone_params { =20 /* Function declarations */ #ifdef CONFIG_THERMAL_OF +struct thermal_zone_device *thermal_of_zone_register(struct device_node *s= ensor, int id, void *data, + const struct thermal_zone_device_ops *ops); struct thermal_zone_device *devm_thermal_of_zone_register(struct device *d= ev, int id, void *data, const struct thermal_zone_device_ops *ops); =20 +void thermal_of_zone_unregister(struct thermal_zone_device *tz); void devm_thermal_of_zone_unregister(struct device *dev, struct thermal_zo= ne_device *tz); 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([82.78.167.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0e8953b6sm1932984066b.65.2025.01.03.08.38.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jan 2025 08:38:33 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, ulf.hansson@linaro.org Cc: claudiu.beznea@tuxon.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 3/6] dt-bindings: thermal: r9a08g045-tsu: Document the TSU unit Date: Fri, 3 Jan 2025 18:38:02 +0200 Message-ID: <20250103163805.1775705-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> References: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The Renesas RZ/G3S SoC includes a Thermal Sensor Unit (TSU) block designed to measure the junction temperature. The temperature is measured using the RZ/G3S ADC, with a dedicated ADC channel directly connected to the TSU. Add documentation for it. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring (Arm) --- .../thermal/renesas,r9a08g045-tsu.yaml | 93 +++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/renesas,r9a08= g045-tsu.yaml diff --git a/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-ts= u.yaml b/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.ya= ml new file mode 100644 index 000000000000..573e2b9d3752 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/renesas,r9a08g045-tsu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3S Thermal Sensor Unit + +description: + The thermal sensor unit (TSU) measures the temperature(Tj) inside + the LSI. + +maintainers: + - Claudiu Beznea + +$ref: thermal-sensor.yaml# + +properties: + compatible: + const: renesas,r9a08g045-tsu + + reg: + maxItems: 1 + + clocks: + items: + - description: TSU module clock + + power-domains: + maxItems: 1 + + resets: + items: + - description: TSU module reset + + io-channels: + items: + - description: ADC channel which reports the TSU temperature + + io-channel-names: + items: + - const: tsu + + "#thermal-sensor-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - power-domains + - resets + - io-channels + - io-channel-names + - '#thermal-sensor-cells' + +additionalProperties: false + +examples: + - | + #include + + tsu: thermal@10059000 { + compatible =3D "renesas,r9a08g045-tsu"; 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([82.78.167.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0e8953b6sm1932984066b.65.2025.01.03.08.38.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jan 2025 08:38:35 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, ulf.hansson@linaro.org Cc: claudiu.beznea@tuxon.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 4/6] thermal: renesas: rzg3s: Add thermal driver for the Renesas RZ/G3S SoC Date: Fri, 3 Jan 2025 18:38:03 +0200 Message-ID: <20250103163805.1775705-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> References: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The Renesas RZ/G3S SoC features a Thermal Sensor Unit (TSU) that reports the junction temperature. The temperature is reported through a dedicated ADC channel. Add a driver for the Renesas RZ/G3S TSU. Signed-off-by: Claudiu Beznea --- MAINTAINERS | 7 + drivers/thermal/renesas/Kconfig | 8 + drivers/thermal/renesas/Makefile | 1 + drivers/thermal/renesas/rzg3s_thermal.c | 301 ++++++++++++++++++++++++ 4 files changed, 317 insertions(+) create mode 100644 drivers/thermal/renesas/rzg3s_thermal.c diff --git a/MAINTAINERS b/MAINTAINERS index d2ab799a0659..0b5854dc2d5d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20131,6 +20131,13 @@ S: Maintained F: Documentation/devicetree/bindings/iio/potentiometer/renesas,x9250.yaml F: drivers/iio/potentiometer/x9250.c =20 +RENESAS RZ/G3S THERMAL SENSOR UNIT DRIVER +M: Claudiu Beznea +L: linux-pm@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml +F: drivers/thermal/renesas/rzg3s_thermal.c + RESET CONTROLLER FRAMEWORK M: Philipp Zabel S: Maintained diff --git a/drivers/thermal/renesas/Kconfig b/drivers/thermal/renesas/Kcon= fig index dcf5fc5ae08e..566478797095 100644 --- a/drivers/thermal/renesas/Kconfig +++ b/drivers/thermal/renesas/Kconfig @@ -26,3 +26,11 @@ config RZG2L_THERMAL help Enable this to plug the RZ/G2L thermal sensor driver into the Linux thermal framework. + +config RZG3S_THERMAL + tristate "Renesas RZ/G3S thermal driver" + depends on ARCH_R9A08G045 || COMPILE_TEST + depends on OF && IIO && RZG2L_ADC + help + Enable this to plug the RZ/G3S thermal sensor driver into the Linux + thermal framework. diff --git a/drivers/thermal/renesas/Makefile b/drivers/thermal/renesas/Mak= efile index bf9cb3cb94d6..1feb5ab78827 100644 --- a/drivers/thermal/renesas/Makefile +++ b/drivers/thermal/renesas/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_RCAR_GEN3_THERMAL) +=3D rcar_gen3_thermal.o obj-$(CONFIG_RCAR_THERMAL) +=3D rcar_thermal.o obj-$(CONFIG_RZG2L_THERMAL) +=3D rzg2l_thermal.o +obj-$(CONFIG_RZG3S_THERMAL) +=3D rzg3s_thermal.o diff --git a/drivers/thermal/renesas/rzg3s_thermal.c b/drivers/thermal/rene= sas/rzg3s_thermal.c new file mode 100644 index 000000000000..6719f9ca05eb --- /dev/null +++ b/drivers/thermal/renesas/rzg3s_thermal.c @@ -0,0 +1,301 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G3S TSU Thermal Sensor Driver + * + * Copyright (C) 2024 Renesas Electronics Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../thermal_hwmon.h" + +#define TSU_SM 0x0 +#define TSU_SM_EN BIT(0) +#define TSU_SM_OE BIT(1) +#define OTPTSUTRIM_REG(n) (0x18 + (n) * 0x4) +#define OTPTSUTRIM_EN_MASK BIT(31) +#define OTPTSUTRIM_MASK GENMASK(11, 0) + +#define TSU_READ_STEPS 8 + +/* Default calibration values, if FUSE values are missing. */ +#define SW_CALIB0_VAL 1297 +#define SW_CALIB1_VAL 751 + +#define MCELSIUS(temp) ((temp) * MILLIDEGREE_PER_DEGREE) + +/** + * struct rzg3s_thermal_priv - RZ/G3S thermal private data structure + * @base: TSU base address + * @dev: device pointer + * @tz: thermal zone pointer + * @rstc: reset control + * @channel: IIO channel to read the TSU + * @mode: current device mode + * @calib0: calibration value + * @calib1: calibration value + */ +struct rzg3s_thermal_priv { + void __iomem *base; + struct device *dev; + struct thermal_zone_device *tz; + struct reset_control *rstc; + struct iio_channel *channel; + enum thermal_device_mode mode; + u16 calib0; + u16 calib1; +}; + +static int rzg3s_thermal_get_temp(struct thermal_zone_device *tz, int *tem= p) +{ + struct rzg3s_thermal_priv *priv =3D thermal_zone_device_priv(tz); + struct device *dev =3D priv->dev; + u32 ts_code_ave =3D 0; + int ret, val; + + if (priv->mode !=3D THERMAL_DEVICE_ENABLED) + return -EAGAIN; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + for (u8 i =3D 0; i < TSU_READ_STEPS; i++) { + ret =3D iio_read_channel_raw(priv->channel, &val); + if (ret < 0) + goto rpm_put; + + ts_code_ave +=3D val; + /* + * According to the HW manual (section 40.4.4 Procedure for Measuring the + * Temperature) we need to wait here at leat 3us. + */ + usleep_range(5, 10); + } + + ret =3D 0; + ts_code_ave =3D DIV_ROUND_CLOSEST(ts_code_ave, TSU_READ_STEPS); + + /* + * According to the HW manual (section 40.4.4 Procedure for Measuring the= Temperature) + * the computation formula is as follows: + * + * Tj =3D (ts_code_ave - priv->calib1) * 165 / (priv->calib0 - priv->cali= b1) - 40 + */ + *temp =3D DIV_ROUND_CLOSEST((ts_code_ave - priv->calib1) * 165, + (priv->calib0 - priv->calib1)) - 40; + + /* Report it in mili degrees Celsius and round it up to 0.5 degrees Celsi= us. */ + *temp =3D roundup(MCELSIUS(*temp), 500); + +rpm_put: + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + return ret; +} + +static void rzg3s_thermal_set_mode(struct rzg3s_thermal_priv *priv, + enum thermal_device_mode mode) +{ + struct device *dev =3D priv->dev; + int ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return; + + if (mode =3D=3D THERMAL_DEVICE_DISABLED) { + writel(0, priv->base + TSU_SM); + } else { + writel(TSU_SM_EN, priv->base + TSU_SM); + /* + * According to the HW manual (section 40.4.1 Procedure for + * Starting the TSU) we need to wait here 30us or more. + */ + usleep_range(30, 40); + + writel(TSU_SM_OE | TSU_SM_EN, priv->base + TSU_SM); + /* + * According to the HW manual (section 40.4.1 Procedure for + * Starting the TSU) we need to wait here 50us or more. + */ + usleep_range(50, 60); + } + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); +} + +static int rzg3s_thermal_change_mode(struct thermal_zone_device *tz, + enum thermal_device_mode mode) +{ + struct rzg3s_thermal_priv *priv =3D thermal_zone_device_priv(tz); + + if (priv->mode =3D=3D mode) + return 0; + + rzg3s_thermal_set_mode(priv, mode); + priv->mode =3D mode; + + return 0; +} + +static const struct thermal_zone_device_ops rzg3s_tz_of_ops =3D { + .get_temp =3D rzg3s_thermal_get_temp, + .change_mode =3D rzg3s_thermal_change_mode, +}; + +static int rzg3s_thermal_read_calib(struct rzg3s_thermal_priv *priv) +{ + struct device *dev =3D priv->dev; + u32 val; + int ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + val =3D readl(priv->base + OTPTSUTRIM_REG(0)); + if (val & OTPTSUTRIM_EN_MASK) + priv->calib0 =3D FIELD_GET(OTPTSUTRIM_MASK, val); + else + priv->calib0 =3D SW_CALIB0_VAL; + + val =3D readl(priv->base + OTPTSUTRIM_REG(1)); + if (val & OTPTSUTRIM_EN_MASK) + priv->calib1 =3D FIELD_GET(OTPTSUTRIM_MASK, val); + else + priv->calib1 =3D SW_CALIB1_VAL; + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + return 0; +} + +static int rzg3s_thermal_probe(struct platform_device *pdev) +{ + struct rzg3s_thermal_priv *priv; + struct device *dev =3D &pdev->dev; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->channel =3D devm_iio_channel_get(dev, "tsu"); + if (IS_ERR(priv->channel)) + return dev_err_probe(dev, PTR_ERR(priv->channel), "Failed to get IIO cha= nnel!\n"); + + priv->rstc =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); + if (IS_ERR(priv->rstc)) + return dev_err_probe(dev, PTR_ERR(priv->rstc), "Failed to get reset!\n"); + + priv->dev =3D dev; + priv->mode =3D THERMAL_DEVICE_DISABLED; + platform_set_drvdata(pdev, priv); + + pm_runtime_set_autosuspend_delay(dev, 300); + pm_runtime_use_autosuspend(dev); + pm_runtime_enable(dev); + + ret =3D rzg3s_thermal_read_calib(priv); + if (ret) { + dev_err_probe(dev, ret, "Failed to read calibration data!\n"); + goto rpm_disable; + } + + priv->tz =3D thermal_of_zone_register(dev->of_node, 0, priv, &rzg3s_tz_of= _ops); + if (IS_ERR(priv->tz)) { + dev_err_probe(dev, PTR_ERR(priv->tz), "Failed to register thermal zone!\= n"); + goto rpm_disable; + } + + ret =3D thermal_add_hwmon_sysfs(priv->tz); + if (ret) { + dev_err_probe(dev, ret, "Failed to add hwmon sysfs!\n"); + goto tz_unregister; + } + + return 0; + +tz_unregister: + thermal_of_zone_unregister(priv->tz); +rpm_disable: + pm_runtime_disable(dev); + pm_runtime_dont_use_autosuspend(dev); + return ret; +} + +static void rzg3s_thermal_remove(struct platform_device *pdev) +{ + struct rzg3s_thermal_priv *priv =3D dev_get_drvdata(&pdev->dev); + + thermal_remove_hwmon_sysfs(priv->tz); + thermal_of_zone_unregister(priv->tz); + pm_runtime_disable(priv->dev); + pm_runtime_dont_use_autosuspend(priv->dev); +} + +static int rzg3s_thermal_suspend(struct device *dev) +{ + struct rzg3s_thermal_priv *priv =3D dev_get_drvdata(dev); + + rzg3s_thermal_set_mode(priv, THERMAL_DEVICE_DISABLED); + + return reset_control_assert(priv->rstc); +} + +static int rzg3s_thermal_resume(struct device *dev) +{ + struct rzg3s_thermal_priv *priv =3D dev_get_drvdata(dev); + int ret; + + ret =3D reset_control_deassert(priv->rstc); + if (ret) + return ret; + + if (priv->mode !=3D THERMAL_DEVICE_DISABLED) + rzg3s_thermal_set_mode(priv, priv->mode); + + return 0; +} + +static const struct dev_pm_ops rzg3s_thermal_pm_ops =3D { + SYSTEM_SLEEP_PM_OPS(rzg3s_thermal_suspend, rzg3s_thermal_resume) +}; + +static const struct of_device_id rzg3s_thermal_dt_ids[] =3D { + { .compatible =3D "renesas,r9a08g045-tsu" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rzg3s_thermal_dt_ids); + +static struct platform_driver rzg3s_thermal_driver =3D { + .driver =3D { + .name =3D "rzg3s_thermal", + .of_match_table =3D rzg3s_thermal_dt_ids, + .pm =3D pm_ptr(&rzg3s_thermal_pm_ops), + }, + .probe =3D rzg3s_thermal_probe, + .remove =3D rzg3s_thermal_remove, +}; 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([82.78.167.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0e8953b6sm1932984066b.65.2025.01.03.08.38.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jan 2025 08:38:37 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, ulf.hansson@linaro.org Cc: claudiu.beznea@tuxon.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 5/6] arm64: dts: renesas: r9a08g045: Add TSU node Date: Fri, 3 Jan 2025 18:38:04 +0200 Message-ID: <20250103163805.1775705-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> References: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add TSU node along with thermal zones and keep it enabled in the SoC DTSI. The temperature reported by the TSU can only be read through channel 8 of the ADC. Therefore, enable the ADC by default. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 43 ++++++++++++++++++- .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 -- 2 files changed, 42 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g045.dtsi index a9b98db9ef95..fd74138198a8 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -205,7 +205,6 @@ adc: adc@10058000 { #address-cells =3D <1>; #size-cells =3D <0>; #io-channel-cells =3D <1>; - status =3D "disabled"; =20 channel@0 { reg =3D <0>; @@ -244,6 +243,17 @@ channel@8 { }; }; =20 + tsu: thermal@10059000 { + compatible =3D "renesas,r9a08g045-tsu"; + reg =3D <0 0x10059000 0 0x1000>; + clocks =3D <&cpg CPG_MOD R9A08G045_TSU_PCLK>; + resets =3D <&cpg R9A08G045_TSU_PRESETN>; + power-domains =3D <&cpg>; + #thermal-sensor-cells =3D <0>; + io-channels =3D <&adc 8>; + io-channel-names =3D "tsu"; + }; + vbattb: clock-controller@1005c000 { compatible =3D "renesas,r9a08g045-vbattb"; reg =3D <0 0x1005c000 0 0x1000>; @@ -690,6 +700,37 @@ timer { "hyp-virt"; }; =20 + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + thermal-sensors =3D <&tsu>; + sustainable-power =3D <423>; + + cooling-maps { + map0 { + trip =3D <&target>; + cooling-device =3D <&cpu0 0 2>; + contribution =3D <1024>; + }; + }; + + trips { + sensor_crit: sensor-crit { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + + target: trip-point { + temperature =3D <100000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + }; + vbattb_xtal: vbattb-xtal { compatible =3D "fixed-clock"; #clock-cells =3D <0>; diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3s-smarc-som.dtsi index ef12c1c462a7..041d256d7b79 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -102,10 +102,6 @@ x3_clk: x3-clock { }; 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([82.78.167.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0e8953b6sm1932984066b.65.2025.01.03.08.38.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jan 2025 08:38:39 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, ulf.hansson@linaro.org Cc: claudiu.beznea@tuxon.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 6/6] arm64: defconfig: Enable RZ/G3S thermal Date: Fri, 3 Jan 2025 18:38:05 +0200 Message-ID: <20250103163805.1775705-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> References: <20250103163805.1775705-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Enable the CONFIG_RZG3S_THERMAL flag for the RZ/G3S SoC. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index dfa5c8d5b658..576a544b8c79 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -706,6 +706,7 @@ CONFIG_ROCKCHIP_THERMAL=3Dm CONFIG_RCAR_THERMAL=3Dy CONFIG_RCAR_GEN3_THERMAL=3Dy CONFIG_RZG2L_THERMAL=3Dy +CONFIG_RZG3S_THERMAL=3Dm CONFIG_ARMADA_THERMAL=3Dy CONFIG_MTK_THERMAL=3Dm CONFIG_MTK_LVTS_THERMAL=3Dm --=20 2.43.0