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Fri, 03 Jan 2025 05:00:26 -0800 (PST) From: Xu Lu To: anup@brainfault.org, tglx@linutronix.de, paul.walmsley@sifive.com Cc: lihangjing@bytedance.com, xieyongji@bytedance.com, guojinhui.liam@bytedance.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Xu Lu Subject: [PATCH] irqchip/riscv-imsic: Support allocating multiple msi-x vectors Date: Fri, 3 Jan 2025 20:59:26 +0800 Message-Id: <20250103125926.54203-1-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This commit modifies alloc and free callback of imsic_base_domain to support allocating and freeing multiple msi-x vectors at once. Signed-off-by: Xu Lu --- drivers/irqchip/irq-riscv-imsic-platform.c | 54 +++++++++++++--------- 1 file changed, 32 insertions(+), 22 deletions(-) diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/i= rq-riscv-imsic-platform.c index c708780e8760..d0ea0eb22e2e 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -141,35 +141,45 @@ static struct irq_chip imsic_irq_base_chip =3D { IRQCHIP_MASK_ON_SUSPEND, }; =20 +static void imsic_irq_domain_free(struct irq_domain *domain, unsigned int = virq, + unsigned int nr_irqs) +{ + struct irq_data *d; + int i; + + for (i =3D 0; i < nr_irqs; i++) { + d =3D irq_domain_get_irq_data(domain, virq + i); + imsic_vector_free(irq_data_get_irq_chip_data(d)); + } + irq_domain_free_irqs_top(domain, virq, nr_irqs); +} + static int imsic_irq_domain_alloc(struct irq_domain *domain, unsigned int = virq, unsigned int nr_irqs, void *args) { struct imsic_vector *vec; - - /* Multi-MSI is not supported yet. */ - if (nr_irqs > 1) - return -EOPNOTSUPP; - - vec =3D imsic_vector_alloc(virq, cpu_online_mask); - if (!vec) - return -ENOSPC; - - irq_domain_set_info(domain, virq, virq, &imsic_irq_base_chip, vec, - handle_simple_irq, NULL, NULL); - irq_set_noprobe(virq); - irq_set_affinity(virq, cpu_online_mask); - irq_data_update_effective_affinity(irq_get_irq_data(virq), cpumask_of(vec= ->cpu)); + int i, err; + + for (i =3D 0; i < nr_irqs; i++) { + vec =3D imsic_vector_alloc(virq + i, cpu_online_mask); + if (!vec) { + err =3D -ENOSPC; + goto error; + } + + irq_domain_set_info(domain, virq + i, virq + i, &imsic_irq_base_chip, + vec, handle_simple_irq, NULL, NULL); + irq_set_noprobe(virq + i); + irq_set_affinity(virq + i, cpu_online_mask); + irq_data_update_effective_affinity(irq_get_irq_data(virq + i), + cpumask_of(vec->cpu)); + } =20 return 0; -} - -static void imsic_irq_domain_free(struct irq_domain *domain, unsigned int = virq, - unsigned int nr_irqs) -{ - struct irq_data *d =3D irq_domain_get_irq_data(domain, virq); =20 - imsic_vector_free(irq_data_get_irq_chip_data(d)); - irq_domain_free_irqs_parent(domain, virq, nr_irqs); +error: + imsic_irq_domain_free(domain, virq, i); + return err; } =20 static int imsic_irq_domain_select(struct irq_domain *domain, struct irq_f= wspec *fwspec, --=20 2.20.1