From nobody Wed Dec 17 16:09:33 2025 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BCD611F9435 for ; Fri, 3 Jan 2025 09:44:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.190 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735897499; cv=none; b=BimJ6GS9LrMCgdQNStzWZKti7K5+XJvs8Rh0qV+1D5QO03VAN9JIwhEMba6LtAI/PgX5yFbVGiukCjybAl6QsVsqclJ5HaQa36p+yRkZBXPPyO453uAEl/MlgkKARfnB9hLwmhGBhLvpk0+MC388NAS224b/zcAjhq38z5KLsaA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735897499; c=relaxed/simple; bh=Ypc7cx9moxdXbH+v5NFw2Lzis/VmFhOoXiE+LRSRX2s=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=p8hPn77S6HHcRjXflVAW4fJsfj0AXUCztxQQyDDDVN0HjkvVzdxGTdF7IljnEHOp63hlbLMYZvKkOpL9X5w917NEuatJ16wnj8vtqXxZHG0Sx0VVTnK2qgYOM+sVYzKi7RySDizID+LzN5UN/wbF+/S1EPTI9vx4ebs0tE2t4XA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.190 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.162.112]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4YPdsc4qHcz22kQZ; Fri, 3 Jan 2025 17:42:44 +0800 (CST) Received: from kwepemd500013.china.huawei.com (unknown [7.221.188.12]) by mail.maildlp.com (Postfix) with ESMTPS id 49D8F1401F3; Fri, 3 Jan 2025 17:44:54 +0800 (CST) Received: from localhost.huawei.com (10.169.71.169) by kwepemd500013.china.huawei.com (7.221.188.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.34; Fri, 3 Jan 2025 17:44:52 +0800 From: Yongbang Shi To: , , , , , , , CC: , , , , , , , , Subject: [PATCH v9 drm-dp 5/5] drm/hisilicon/hibmc: add dp module in hibmc Date: Fri, 3 Jan 2025 17:38:24 +0800 Message-ID: <20250103093824.1963816-6-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250103093824.1963816-1-shiyongbang@huawei.com> References: <20250103093824.1963816-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To kwepemd500013.china.huawei.com (7.221.188.12) Content-Type: text/plain; charset="utf-8" From: Baihan Li To support DP interface displaying in hibmc driver. Add a encoder and connector for DP modual. The HPD function and get_edid function will be add in next series, so temporarily using 1024x768 as default in hibmc_dp_connector_get_modes() Signed-off-by: Baihan Li Signed-off-by: Yongbang Shi Reviewed-by: Dmitry Baryshkov Reviewed-by: Tian Tao --- ChangeLog: v8 -> v9: - changing bahan li to Baihan Li, clear sign-off mismatches warnings, sug= gested by Dmitry Baryshkov. v7 -> v8: - adding pci_set_master() in hibmc_pci_probe(). v6 -> v7: - lowercasing hex, suggested by Dmitry Baryshkov. v5 -> v6: - adding hpd and get_edid comments in the beginning of patch, suggested b= y Dmitry Baryshkov. v3 -> v4: - static inline hibmc_dp_prepare(), suggested by Dmitry Baryshkov. --- drivers/gpu/drm/hisilicon/hibmc/Makefile | 2 +- .../gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c | 118 ++++++++++++++++++ .../gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 14 +++ .../gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h | 5 + 4 files changed, 138 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c diff --git a/drivers/gpu/drm/hisilicon/hibmc/Makefile b/drivers/gpu/drm/his= ilicon/hibmc/Makefile index 214228052ccf..95a4ed599d98 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/Makefile +++ b/drivers/gpu/drm/hisilicon/hibmc/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only hibmc-drm-y :=3D hibmc_drm_drv.o hibmc_drm_de.o hibmc_drm_vdac.o hibmc_drm= _i2c.o \ - dp/dp_aux.o dp/dp_link.o dp/dp_hw.o + dp/dp_aux.o dp/dp_link.o dp/dp_hw.o hibmc_drm_dp.o =20 obj-$(CONFIG_DRM_HISI_HIBMC) +=3D hibmc-drm.o diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c b/drivers/gpu/d= rm/hisilicon/hibmc/hibmc_drm_dp.c new file mode 100644 index 000000000000..603d6b198a54 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright (c) 2024 Hisilicon Limited. + +#include + +#include +#include +#include +#include +#include +#include + +#include "hibmc_drm_drv.h" +#include "dp/dp_hw.h" + +static int hibmc_dp_connector_get_modes(struct drm_connector *connector) +{ + int count; + + count =3D drm_add_modes_noedid(connector, connector->dev->mode_config.max= _width, + connector->dev->mode_config.max_height); + drm_set_preferred_mode(connector, 1024, 768); // temporary implementation + + return count; +} + +static const struct drm_connector_helper_funcs hibmc_dp_conn_helper_funcs = =3D { + .get_modes =3D hibmc_dp_connector_get_modes, +}; + +static const struct drm_connector_funcs hibmc_dp_conn_funcs =3D { + .reset =3D drm_atomic_helper_connector_reset, + .fill_modes =3D drm_helper_probe_single_connector_modes, + .destroy =3D drm_connector_cleanup, + .atomic_duplicate_state =3D drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_connector_destroy_state, +}; + +static inline int hibmc_dp_prepare(struct hibmc_dp *dp, struct drm_display= _mode *mode) +{ + int ret; + + hibmc_dp_display_en(dp, false); + + ret =3D hibmc_dp_mode_set(dp, mode); + if (ret) + drm_err(dp->drm_dev, "hibmc dp mode set failed: %d\n", ret); + + return ret; +} + +static void hibmc_dp_encoder_enable(struct drm_encoder *drm_encoder, + struct drm_atomic_state *state) +{ + struct hibmc_dp *dp =3D container_of(drm_encoder, struct hibmc_dp, encode= r); + struct drm_display_mode *mode =3D &drm_encoder->crtc->state->mode; + + if (hibmc_dp_prepare(dp, mode)) + return; + + hibmc_dp_display_en(dp, true); +} + +static void hibmc_dp_encoder_disable(struct drm_encoder *drm_encoder, + struct drm_atomic_state *state) +{ + struct hibmc_dp *dp =3D container_of(drm_encoder, struct hibmc_dp, encode= r); + + hibmc_dp_display_en(dp, false); +} + +static const struct drm_encoder_helper_funcs hibmc_dp_encoder_helper_funcs= =3D { + .atomic_enable =3D hibmc_dp_encoder_enable, + .atomic_disable =3D hibmc_dp_encoder_disable, +}; + +int hibmc_dp_init(struct hibmc_drm_private *priv) +{ + struct drm_device *dev =3D &priv->dev; + struct drm_crtc *crtc =3D &priv->crtc; + struct hibmc_dp *dp =3D &priv->dp; + struct drm_connector *connector =3D &dp->connector; + struct drm_encoder *encoder =3D &dp->encoder; + int ret; + + dp->mmio =3D priv->mmio; + dp->drm_dev =3D dev; + + ret =3D hibmc_dp_hw_init(&priv->dp); + if (ret) { + drm_err(dev, "hibmc dp hw init failed: %d\n", ret); + return ret; + } + + hibmc_dp_display_en(&priv->dp, false); + + encoder->possible_crtcs =3D drm_crtc_mask(crtc); + ret =3D drmm_encoder_init(dev, encoder, NULL, DRM_MODE_ENCODER_TMDS, NULL= ); + if (ret) { + drm_err(dev, "init dp encoder failed: %d\n", ret); + return ret; + } + + drm_encoder_helper_add(encoder, &hibmc_dp_encoder_helper_funcs); + + ret =3D drm_connector_init(dev, connector, &hibmc_dp_conn_funcs, + DRM_MODE_CONNECTOR_DisplayPort); + if (ret) { + drm_err(dev, "init dp connector failed: %d\n", ret); + return ret; + } + + drm_connector_helper_add(connector, &hibmc_dp_conn_helper_funcs); + + drm_connector_attach_encoder(connector, encoder); + + return 0; +} diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c b/drivers/gpu/= drm/hisilicon/hibmc/hibmc_drm_drv.c index 8c488c98ac97..ee1a87ac6afb 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c @@ -28,6 +28,10 @@ #include "hibmc_drm_drv.h" #include "hibmc_drm_regs.h" =20 +#define HIBMC_DP_HOST_SERDES_CTRL 0x1f001c +#define HIBMC_DP_HOST_SERDES_CTRL_VAL 0x8a00 +#define HIBMC_DP_HOST_SERDES_CTRL_MASK 0x7ffff + DEFINE_DRM_GEM_FOPS(hibmc_fops); =20 static irqreturn_t hibmc_interrupt(int irq, void *arg) @@ -118,6 +122,14 @@ static int hibmc_kms_init(struct hibmc_drm_private *pr= iv) return ret; } =20 + /* if DP existed, init DP */ + if ((readl(priv->mmio + HIBMC_DP_HOST_SERDES_CTRL) & + HIBMC_DP_HOST_SERDES_CTRL_MASK) =3D=3D HIBMC_DP_HOST_SERDES_CTRL_VAL= ) { + ret =3D hibmc_dp_init(priv); + if (ret) + drm_err(dev, "failed to init dp: %d\n", ret); + } + ret =3D hibmc_vdac_init(priv); if (ret) { drm_err(dev, "failed to init vdac: %d\n", ret); @@ -328,6 +340,8 @@ static int hibmc_pci_probe(struct pci_dev *pdev, goto err_return; } =20 + pci_set_master(pdev); + ret =3D hibmc_load(dev); if (ret) { drm_err(dev, "failed to load hibmc: %d\n", ret); diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h b/drivers/gpu/= drm/hisilicon/hibmc/hibmc_drm_drv.h index 42f0ab8f9b5a..d982f1e4b958 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h @@ -20,6 +20,8 @@ =20 #include =20 +#include "dp/dp_hw.h" + struct hibmc_vdac { struct drm_device *dev; struct drm_encoder encoder; @@ -37,6 +39,7 @@ struct hibmc_drm_private { struct drm_plane primary_plane; struct drm_crtc crtc; struct hibmc_vdac vdac; + struct hibmc_dp dp; }; =20 static inline struct hibmc_vdac *to_hibmc_vdac(struct drm_connector *conne= ctor) @@ -59,4 +62,6 @@ int hibmc_vdac_init(struct hibmc_drm_private *priv); =20 int hibmc_ddc_create(struct drm_device *drm_dev, struct hibmc_vdac *connec= tor); =20 +int hibmc_dp_init(struct hibmc_drm_private *priv); + #endif --=20 2.33.0