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Fri, 03 Jan 2025 08:02:47 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50382ka3025017 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 3 Jan 2025 08:02:46 GMT Received: from yuanfang4-gv.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 3 Jan 2025 00:02:41 -0800 From: Yuanfang Zhang Date: Fri, 3 Jan 2025 16:01:54 +0800 Subject: [PATCH] coresight-tmc: stop disabling tmc when flush timeout Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250103-fix_cpu_hung-v1-1-a7b9b3893d44@quicinc.com> X-B4-Tracking: v=1; b=H4sIAHGZd2cC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDI1MDQwNj3bTMivjkgtL4jNK8dN0k00RLU0Nzy8SURBMloJaColSgPNi46Nj aWgB8lWKNXgAAAA== X-Change-ID: 20250103-fix_cpu_hung-b5a95179ada4 To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" CC: , , , , Yuanfang Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1735891361; l=3946; i=quic_yuanfang@quicinc.com; s=20241209; h=from:subject:message-id; bh=mHCVMcot2Zwb+s1j6evKoS89X4IykPu7hzPnsebYG0Q=; b=thL05qqkoOMJGWFsAJOl0U4XDF8EFiIG4B1kMc2HiQiJWyivOahUPpTWLlb9ddrAbY3+f96SI 4hXcanDZoslCS1AGP68/YDi5Xx1QvJxD1PwmKHN+q0rT0BvBZeuHKVw X-Developer-Key: i=quic_yuanfang@quicinc.com; a=ed25519; pk=ZrIjRVq9LN8/zCQGbDEwrZK/sfnVjwQ2elyEZAOaV1Q= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: o7QuROQGLRAtYOtN6LQEQCnznVNsNqzf X-Proofpoint-GUID: o7QuROQGLRAtYOtN6LQEQCnznVNsNqzf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 mlxscore=0 suspectscore=0 impostorscore=0 adultscore=0 mlxlogscore=886 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501030069 When multiple ETMs are enabled simultaneously, the time required to complete a flush in the process of reading the TMC device node may exceed the default wait time of 100us. If the TMC capture is stopped while any ETM has not completed its flush, it can cause the corresponding CPU to hang. Fix the by checking the TMCReady bit after the flush. If TMCReady bit is set, TraceCaptEn bit can be clear; otherwise, return directly and stop the TMC read. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 17 +++++++++++++++-- drivers/hwtracing/coresight/coresight-tmc-etr.c | 22 +++++++++++++++++----- 2 files changed, 32 insertions(+), 7 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtr= acing/coresight/coresight-tmc-etf.c index d4f641cd9de69488fe3d1c1dc9b5a9eafb55ed59..bded290c42891d782344d9a6e63= ebdbed6719133 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -80,11 +80,21 @@ static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata) return; } =20 -static void __tmc_etb_disable_hw(struct tmc_drvdata *drvdata) +static int __tmc_etb_disable_hw(struct tmc_drvdata *drvdata) { + int rc; + CS_UNLOCK(drvdata->base); =20 tmc_flush_and_stop(drvdata); + + rc =3D tmc_wait_for_tmcready(drvdata); + if (rc) { + dev_err(&drvdata->csdev->dev, + "Failed to disable : TMC is not ready\n"); + CS_LOCK(drvdata->base); + return rc; + } /* * When operating in sysFS mode the content of the buffer needs to be * read before the TMC is disabled. @@ -94,6 +104,7 @@ static void __tmc_etb_disable_hw(struct tmc_drvdata *drv= data) tmc_disable_hw(drvdata); =20 CS_LOCK(drvdata->base); + return 0; } =20 static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata) @@ -650,7 +661,9 @@ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata) ret =3D -EINVAL; goto out; } - __tmc_etb_disable_hw(drvdata); + ret =3D __tmc_etb_disable_hw(drvdata); + if (ret) + goto out; } =20 drvdata->reading =3D true; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index a48bb85d0e7f44a25b813f3c828cc3d705d16012..63a1f7501562fa0b5c2fe6ea53d= ce4d82842bec3 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1135,11 +1135,21 @@ static void tmc_etr_sync_sysfs_buf(struct tmc_drvda= ta *drvdata) } } =20 -static void __tmc_etr_disable_hw(struct tmc_drvdata *drvdata) +static int __tmc_etr_disable_hw(struct tmc_drvdata *drvdata) { + int rc; + CS_UNLOCK(drvdata->base); =20 tmc_flush_and_stop(drvdata); + + rc =3D tmc_wait_for_tmcready(drvdata); + if (rc) { + dev_err(&drvdata->csdev->dev, + "Failed to disable : TMC is not ready\n"); + CS_LOCK(drvdata->base); + return rc; + } /* * When operating in sysFS mode the content of the buffer needs to be * read before the TMC is disabled. @@ -1150,7 +1160,7 @@ static void __tmc_etr_disable_hw(struct tmc_drvdata *= drvdata) tmc_disable_hw(drvdata); =20 CS_LOCK(drvdata->base); - + return 0; } =20 void tmc_etr_disable_hw(struct tmc_drvdata *drvdata) @@ -1779,9 +1789,11 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) } =20 /* Disable the TMC if we are trying to read from a running session. */ - if (coresight_get_mode(drvdata->csdev) =3D=3D CS_MODE_SYSFS) - __tmc_etr_disable_hw(drvdata); - + if (coresight_get_mode(drvdata->csdev) =3D=3D CS_MODE_SYSFS) { + ret =3D __tmc_etr_disable_hw(drvdata); + if (ret) + goto out; + } drvdata->reading =3D true; out: spin_unlock_irqrestore(&drvdata->spinlock, flags); --- base-commit: fac04efc5c793dccbd07e2d59af9f90b7fc0dca4 change-id: 20250103-fix_cpu_hung-b5a95179ada4 Best regards, --=20 Yuanfang Zhang