From nobody Fri Feb 13 00:21:34 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 513D41B4147; Thu, 2 Jan 2025 15:54:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735833280; cv=none; b=YfKv/xvoZhbGvqSRXKPc4lOciHD1BQteNsDOFmqnHL/36fsGj+S8Ojbg8mKVG+y6Ee8n3QSvaEFs91MjYc78J56KGm46b3PiRtKYHD3ObXEEI5FNv+qqWhH8MLpyOg/NlJUdMZF/+v8bIHRAyyFP4/0FRrf+uuCzAqYEurNSmSo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735833280; c=relaxed/simple; bh=6NTLdpqRX3agd8O8UGyvvQg8oU1AoCJ5xGZ1jLdV5W0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=J137lDAz+VsoH0oDdsU8NPtit2b22cTFSagFs+4Yvmb6ehsOSA6aoYCi+x0RqQzZbFi7nuvoU3lEXQu7czaFJmc2iaQeWF6d9SCNe7Xd0EE9wOWqePsbeM0pC9CCHfDvuycIeAdk6i3IsI+pqB4+v7IZgMX+GwXXRtNI4LUebWg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E4495153B; Thu, 2 Jan 2025 07:55:06 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9A5293F673; Thu, 2 Jan 2025 07:54:36 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King Subject: [PATCH v3 3/4] arm64: dts: morello: Add support for soc dts Date: Thu, 2 Jan 2025 15:54:15 +0000 Message-ID: <20250102155416.13159-4-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250102155416.13159-1-vincenzo.frascino@arm.com> References: <20250102155416.13159-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. Introduce Morello SoC dts. Signed-off-by: Vincenzo Frascino --- arch/arm64/boot/dts/arm/Makefile | 1 + arch/arm64/boot/dts/arm/morello-sdp.dts | 55 +++++++++++++++++++++++++ 2 files changed, 56 insertions(+) create mode 100644 arch/arm64/boot/dts/arm/morello-sdp.dts diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Mak= efile index d908e96d7ddc..869667bef7c0 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) +=3D rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D fvp-base-revc.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D corstone1000-fvp.dtb corstone1000-mps3.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) +=3D morello-sdp.dtb diff --git a/arch/arm64/boot/dts/arm/morello-sdp.dts b/arch/arm64/boot/dts/= arm/morello-sdp.dts new file mode 100644 index 000000000000..68926f511362 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello-sdp.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + + */ + +/dts-v1/; +#include "morello.dtsi" + +/ { + model =3D "Arm Morello System Development Platform"; + compatible =3D "arm,morello-sdp", "arm,morello"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&gic { + reg =3D <0x0 0x30000000 0 0x10000>, /* GICD */ + <0x0 0x300c0000 0 0x80000>; /* GICR */ + interrupts =3D ; + + its1: msi-controller@30040000 { + compatible =3D "arm,gic-v3-its"; + msi-controller; + #msi-cells =3D <1>; + reg =3D <0x0 0x30040000 0x0 0x20000>; + }; + + its2: msi-controller@30060000 { + compatible =3D "arm,gic-v3-its"; + msi-controller; + #msi-cells =3D <1>; + reg =3D <0x0 0x30060000 0x0 0x20000>; + }; + + its_ccix: msi-controller@30080000 { + compatible =3D "arm,gic-v3-its"; + msi-controller; + #msi-cells =3D <1>; + reg =3D <0x0 0x30080000 0x0 0x20000>; + }; + + its_pcie: msi-controller@300a0000 { + compatible =3D "arm,gic-v3-its"; + msi-controller; + #msi-cells =3D <1>; + reg =3D <0x0 0x300a0000 0x0 0x20000>; + }; +}; --=20 2.43.0