From nobody Thu Feb 12 23:05:25 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 77D581B415A; Thu, 2 Jan 2025 15:54:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735833276; cv=none; b=BbypbuaeVlJm6THn4SoDwN/+ulw9nC3428NLC7bQfd9ozh7dqaKFfMuDEQ6I0I02Q7P/pos6OK718vbST/rRPZwoJwtt4SQCGHFTP0SlTmZV0Pmz/ga0dj8ydNbxa74DYjvnB3cpJ5JLFsiBOJon7GQPXQR5LYwbVfbdvyMRS5k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735833276; c=relaxed/simple; bh=P2Fvk5LmaPoZy212Xdx8JKIQDkLJwVEJ9beOsLFSR7k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dmDOIZOQ+6Osgi55vuatyKFih7uwg/3GuTu51fFidTKR1UJWSMfw9xLt6I4DDuIbhGz7p0jgluOD29HN4oiawIFFTaUtgcyt9M3Etz7vqBtXQsCrP8mYAcTa0Njf0jgzbZqK4BNC6YgAabj3+bBIraSmDYmIiGPKmycfC3UmAew= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0713A153B; Thu, 2 Jan 2025 07:55:02 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B1BB53F673; Thu, 2 Jan 2025 07:54:31 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King Subject: [PATCH v3 1/4] dt-bindings: arm: Add Morello compatibility Date: Thu, 2 Jan 2025 15:54:13 +0000 Message-ID: <20250102155416.13159-2-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250102155416.13159-1-vincenzo.frascino@arm.com> References: <20250102155416.13159-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatibility to Arm Morello System Development Platform. Note: Morello is at the same time the name of an Architecture [1], an SoC [2] and a Board [2]. To distinguish in between Architecture/SoC and Board we refer to the first as arm,morello and to the second as arm,morello-sdp. [1] https://developer.arm.com/Architectures/Morello [2] https://www.morello-project.org/ Signed-off-by: Vincenzo Frascino Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml b= /Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml index 8dd6b6446394..40e7910756c8 100644 --- a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml +++ b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml @@ -118,6 +118,10 @@ properties: items: - const: arm,foundation-aarch64 - const: arm,vexpress + - description: Arm Morello System Development Platform + items: + - const: arm,morello-sdp + - const: arm,morello =20 arm,vexpress,position: description: When daughterboards are stacked on one site, their positi= on --=20 2.43.0 From nobody Thu Feb 12 23:05:25 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C7DAA1B424D; Thu, 2 Jan 2025 15:54:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735833278; cv=none; b=plfG2r1XbFI+ew1eyRxHzobUdUQ5RP3+KiA0qGoO+m2HcOq7iqgMYbyDmKdb3RZwvOx2kM94F8nYXEbk2HZMDqA2x7DWqBoxc3d2bgLilsM+3HVQUs1eFg7Lb04PllA5TAF1WRaGvOvHuwqYJWQ3YfImnJEH+VGWgdYQBqbiUdE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735833278; c=relaxed/simple; bh=rY+X6NnhbpsH2egYnx5nNAevAgvsxJrWiZWQ4wvfXLc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Srn6xnN+MCUblwJWG7bWxy6WZNvhmN5XLCVJmc+jH7hKuRVNnc1Ow98Ed0+E8i218GhXGAkwCKXcnBGAg0MTN4ZVnubRwqTgH0SiEPaFfb5Y9a89dF1WDfQggBZrh5Lga/bAvk2yvpyyOrBLleZq+xQmx4/29Mf9+Kq++aM1518= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 75A0211FB; Thu, 2 Jan 2025 07:55:04 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2B9483F673; Thu, 2 Jan 2025 07:54:34 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King Subject: [PATCH v3 2/4] arm64: dts: morello: Add support for common functionalities Date: Thu, 2 Jan 2025 15:54:14 +0000 Message-ID: <20250102155416.13159-3-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250102155416.13159-1-vincenzo.frascino@arm.com> References: <20250102155416.13159-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share some functionalities that have conveniently been included in morello.dtsi to avoid duplication. Introduce morello.dtsi. Note: Morello fvp will be introduced with a future patch series. Signed-off-by: Vincenzo Frascino --- arch/arm64/boot/dts/arm/morello.dtsi | 341 +++++++++++++++++++++++++++ 1 file changed, 341 insertions(+) create mode 100644 arch/arm64/boot/dts/arm/morello.dtsi diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm= /morello.dtsi new file mode 100644 index 000000000000..67bc960f4596 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello.dtsi @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. + */ + +#include + +/ { + interrupt-parent =3D <&gic>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + chosen { }; + + clocks { + soc_refclk50mhz: clock-50000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <50000000>; + clock-output-names =3D "apb_pclk"; + }; + + soc_refclk85mhz: clock-85000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <85000000>; + clock-output-names =3D "iofpga:aclk"; + }; + + soc_uartclk: clock-50000000-uart { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <50000000>; + clock-output-names =3D "uartclk"; + }; + + dpu_aclk: dpu-aclk { + /* 77.1 MHz derived from 24 MHz reference clock */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <350000000>; + clock-output-names =3D "aclk"; + }; + + dpu_pixel_clk: dpu-pixel-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <148500000>; + clock-output-names =3D "pxclk"; + }; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu0@0 { + compatible =3D "arm,neoverse-n1"; + reg =3D <0x0 0x0>; + device_type =3D "cpu"; + enable-method =3D "psci"; + clocks =3D <&scmi_dvfs 0>; + }; + + cpu1: cpu1@100 { + compatible =3D "arm,neoverse-n1"; + reg =3D <0x0 0x100>; + device_type =3D "cpu"; + enable-method =3D "psci"; + clocks =3D <&scmi_dvfs 0>; + }; + + cpu2: cpu2@10000 { + compatible =3D "arm,neoverse-n1"; + reg =3D <0x0 0x10000>; + device_type =3D "cpu"; + enable-method =3D "psci"; + clocks =3D <&scmi_dvfs 1>; + }; + + cpu3: cpu3@10100 { + compatible =3D "arm,neoverse-n1"; + reg =3D <0x0 0x10100>; + device_type =3D "cpu"; + enable-method =3D "psci"; + clocks =3D <&scmi_dvfs 1>; + }; + }; + + firmware { + interrupt-parent =3D <&gic>; + + scmi { + compatible =3D "arm,scmi"; + mbox-names =3D "tx", "rx"; + mboxes =3D <&mailbox 1 0>, <&mailbox 1 1>; + shmem =3D <&cpu_scp_hpri0>, <&cpu_scp_hpri1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_dvfs: protocol@13 { + reg =3D <0x13>; + #clock-cells =3D <1>; + }; + + scmi_clk: protocol@14 { + reg =3D <0x14>; + #clock-cells =3D <1>; + }; + }; + }; + + /* The first bank of memory, memory map is actually provided by UEFI. */ + memory@80000000 { + device_type =3D "memory"; + /* [0x80000000-0xffffffff] */ + reg =3D <0x00000000 0x80000000 0x0 0x7F000000>; + }; + + memory@8080000000 { + device_type =3D "memory"; + /* [0x8080000000-0x83f7ffffff] */ + reg =3D <0x00000080 0x80000000 0x3 0x78000000>; + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + secure-firmware@ff000000 { + reg =3D <0 0xff000000 0 0x01000000>; + no-map; + }; + }; + + spe-pmu { + compatible =3D "arm,statistical-profiling-extension-v1"; + interrupts =3D ; + }; + + soc: soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + ranges; + + dp0: display@2cc00000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "arm,mali-d32", "arm,mali-d71"; + reg =3D <0 0x2cc00000 0 0x20000>; + interrupts =3D <0 69 4>; + clocks =3D <&dpu_aclk>; + clock-names =3D "aclk"; + iommus =3D <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>, + <&smmu_dp 8>; + + pl0: pipeline@0 { + reg =3D <0>; + clocks =3D <&dpu_pixel_clk>; + clock-names =3D "pxclk"; + port { + dp_pl0_out0: endpoint { + remote-endpoint =3D <&tda998x_0_input>; + }; + }; + }; + }; + + i2c: i2c@1c0f0000 { + compatible =3D "cdns,i2c-r1p14"; + reg =3D <0x0 0x1c0f0000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <100000>; + interrupts =3D ; + clocks =3D <&dpu_aclk>; + + hdmi_tx: hdmi-transmitter@70 { + compatible =3D "nxp,tda998x"; + reg =3D <0x70>; + video-ports =3D <0x234501>; + port { + tda998x_0_input: endpoint { + remote-endpoint =3D <&dp_pl0_out0>; + }; + }; + }; + }; + + gic: interrupt-controller@2c010000 { + compatible =3D "arm,gic-v3"; + #address-cells =3D <2>; + #interrupt-cells =3D <3>; + #size-cells =3D <2>; + ranges; + interrupt-controller; + }; + + smmu_dp: iommu@2ce00000 { + compatible =3D "arm,smmu-v3"; + reg =3D <0 0x2ce00000 0 0x40000>; + interrupts =3D , + , + ; + interrupt-names =3D "eventq", "gerror", "cmdq-sync"; + #iommu-cells =3D <1>; + }; + + smmu_ccix: iommu@4f000000 { + compatible =3D "arm,smmu-v3"; + reg =3D <0 0x4f000000 0 0x40000>; + interrupts =3D , + , + , + ; + interrupt-names =3D "eventq", "gerror", "priq", "cmdq-sync"; + msi-parent =3D <&its1 0>; + #iommu-cells =3D <1>; + dma-coherent; + }; + + smmu_pcie: iommu@4f400000 { + compatible =3D "arm,smmu-v3"; + reg =3D <0 0x4f400000 0 0x40000>; + interrupts =3D , + , + , + ; + interrupt-names =3D "eventq", "gerror", "priq", "cmdq-sync"; + msi-parent =3D <&its2 0>; + #iommu-cells =3D <1>; + dma-coherent; + }; + + mailbox: mhu@45000000 { + compatible =3D "arm,mhu-doorbell", "arm,primecell"; + reg =3D <0x0 0x45000000 0x0 0x1000>; + interrupts =3D , + ; + #mbox-cells =3D <2>; + clocks =3D <&soc_refclk50mhz>; + clock-names =3D "apb_pclk"; + }; + + pcie_ctlr: pcie@28c0000000 { + compatible =3D "pci-host-ecam-generic"; + device_type =3D "pci"; + reg =3D <0x28 0xC0000000 0 0x10000000>; + ranges =3D <0x01000000 0x00 0x00000000 0x00 0x6F000000 0x00 0x00800000>, + <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0F000000>, + <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1F 0xC0000000>; + bus-range =3D <0 255>; + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + dma-coherent; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>; + msi-map =3D <0 &its_pcie 0 0x10000>; + iommu-map =3D <0 &smmu_pcie 0 0x10000>; + }; + + ccix_pcie_ctlr: pcie@4fc0000000 { + compatible =3D "pci-host-ecam-generic"; + device_type =3D "pci"; + reg =3D <0x4F 0xC0000000 0 0x10000000>; + ranges =3D <0x01000000 0x00 0x00000000 0x00 0x7F000000 0x00 0x00800000>, + <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0F000000>, + <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1F 0xC0000000>; + bus-range =3D <0 255>; + linux,pci-domain =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + dma-coherent; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>; + msi-map =3D <0 &its_ccix 0 0x10000>; + iommu-map =3D <0 &smmu_ccix 0 0x10000>; + }; + + uart0: serial@2a400000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x0 0x2a400000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&soc_uartclk>, <&soc_refclk50mhz>; + clock-names =3D "uartclk", "apb_pclk"; + + status =3D "disabled"; + }; + + sram: sram@45200000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0x06000000 0x0 0x8000>; + ranges =3D <0 0x0 0x06000000 0x8000>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpu_scp_hpri0: scp-sram@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x80>; + }; + + cpu_scp_hpri1: scp-sram@80 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x80 0x80>; + }; + }; + + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; +}; --=20 2.43.0 From nobody Thu Feb 12 23:05:25 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 513D41B4147; Thu, 2 Jan 2025 15:54:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735833280; cv=none; b=YfKv/xvoZhbGvqSRXKPc4lOciHD1BQteNsDOFmqnHL/36fsGj+S8Ojbg8mKVG+y6Ee8n3QSvaEFs91MjYc78J56KGm46b3PiRtKYHD3ObXEEI5FNv+qqWhH8MLpyOg/NlJUdMZF/+v8bIHRAyyFP4/0FRrf+uuCzAqYEurNSmSo= ARC-Message-Signature: i=1; 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Thu, 2 Jan 2025 07:54:36 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King Subject: [PATCH v3 3/4] arm64: dts: morello: Add support for soc dts Date: Thu, 2 Jan 2025 15:54:15 +0000 Message-ID: <20250102155416.13159-4-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250102155416.13159-1-vincenzo.frascino@arm.com> References: <20250102155416.13159-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. Introduce Morello SoC dts. Signed-off-by: Vincenzo Frascino --- arch/arm64/boot/dts/arm/Makefile | 1 + arch/arm64/boot/dts/arm/morello-sdp.dts | 55 +++++++++++++++++++++++++ 2 files changed, 56 insertions(+) create mode 100644 arch/arm64/boot/dts/arm/morello-sdp.dts diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Mak= efile index d908e96d7ddc..869667bef7c0 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) +=3D rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D fvp-base-revc.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D corstone1000-fvp.dtb corstone1000-mps3.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) +=3D morello-sdp.dtb diff --git a/arch/arm64/boot/dts/arm/morello-sdp.dts b/arch/arm64/boot/dts/= arm/morello-sdp.dts new file mode 100644 index 000000000000..68926f511362 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello-sdp.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + + */ + +/dts-v1/; +#include "morello.dtsi" + +/ { + model =3D "Arm Morello System Development Platform"; + compatible =3D "arm,morello-sdp", "arm,morello"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&gic { + reg =3D <0x0 0x30000000 0 0x10000>, /* GICD */ + <0x0 0x300c0000 0 0x80000>; /* GICR */ + interrupts =3D ; + + its1: msi-controller@30040000 { + compatible =3D "arm,gic-v3-its"; + msi-controller; + #msi-cells =3D <1>; + reg =3D <0x0 0x30040000 0x0 0x20000>; + }; + + its2: msi-controller@30060000 { + compatible =3D "arm,gic-v3-its"; + msi-controller; + #msi-cells =3D <1>; + reg =3D <0x0 0x30060000 0x0 0x20000>; + }; + + its_ccix: msi-controller@30080000 { + compatible =3D "arm,gic-v3-its"; + msi-controller; + #msi-cells =3D <1>; + reg =3D <0x0 0x30080000 0x0 0x20000>; + }; + + its_pcie: msi-controller@300a0000 { + compatible =3D "arm,gic-v3-its"; + msi-controller; + #msi-cells =3D <1>; + reg =3D <0x0 0x300a0000 0x0 0x20000>; + }; +}; --=20 2.43.0 From nobody Thu Feb 12 23:05:25 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C7C961B5ED1; Thu, 2 Jan 2025 15:54:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735833283; cv=none; b=auXM/5/joCjXX9rEyXf0GcELFpCcNB5mkscUvAQ7+EHyet/O0QSOwBKbwkrSZfcHXjdO1gArq/0QrWZ7dKrUI6O3baitlrREM6bi6CabycuvNXT5K/w3nZB3uiyWJH8QyG64DC5iZufBoTcj0iJx/NEf7HfVUUutk2BKTtVxZ/g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735833283; c=relaxed/simple; bh=gq14HYvVc8qU+vwUoRluBQU09Ex6oii7YLx5K32/2wQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hOW30ug611BRSQUCmln416LtpFnyeWGInaVRT6whrKQhXctyx+oK7kh0KLUY/OUx456hIFw4XLXkIyhxdruQ8/66legPUx7Ybii+dyhh26ldhovyFZt/rWgwQMou1uC16lco3p6qwZyaRthzh87v2iMdhw2l0IAcX93CmLGNN1U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5EA4E11FB; Thu, 2 Jan 2025 07:55:09 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1469A3F673; Thu, 2 Jan 2025 07:54:38 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King Subject: [PATCH v3 4/4] MAINTAINERS: Add Vincenzo Frascino as Arm Morello Maintainer Date: Thu, 2 Jan 2025 15:54:16 +0000 Message-ID: <20250102155416.13159-5-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250102155416.13159-1-vincenzo.frascino@arm.com> References: <20250102155416.13159-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Vincenzo Frascino as Arm Morello Software Development Platform Maintainer. Signed-off-by: Vincenzo Frascino Reviewed-by: Krzysztof Kozlowski --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 910305c11e8a..8b2d20fc8cdb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2711,6 +2711,12 @@ F: arch/arm/boot/dts/socionext/milbeaut* F: arch/arm/mach-milbeaut/ N: milbeaut =20 +ARM/MORELLO PLATFORM +M: Vincenzo Frascino +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: arch/arm64/boot/dts/arm/morello* + ARM/MOXA ART SOC M: Krzysztof Kozlowski L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) --=20 2.43.0