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Thu, 2 Jan 2025 13:34:41 -0500 (EST) From: Jiaxun Yang Date: Thu, 02 Jan 2025 18:34:35 +0000 Subject: [PATCH 2/3] loongarch: Introduce sys_loongarch_flush_icache syscall Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250102-la32-uapi-v1-2-db32aa769b88@flygoat.com> References: <20250102-la32-uapi-v1-0-db32aa769b88@flygoat.com> In-Reply-To: <20250102-la32-uapi-v1-0-db32aa769b88@flygoat.com> To: Huacai Chen , WANG Xuerui Cc: Arnd Bergmann , loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5030; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=w4f3TlGw9XqnVwPa+FzSha4Az1WTx3zGdxtidn31rb4=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhvSyO3Z/38ufjGVmL2Jc/6X52XGDO5dsV1QoV1YeUZtfU rz3E49MRykLgxgXg6yYIkuIgFLfhsaLC64/yPoDM4eVCWQIAxenAEzkaTrD/xiRSzWJuQV7/ITa q6qu/NrENflx2aKnJ/uTnqzY/15AyYvhf+Dq0+dbvjf9TZ1ZO1VoQrWMqqSJwRaHX12T75hvnV4 5mRcA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 On LoongArch CPUs with ICACHET, writes automatically sync to both local and remote instruction caches. CPUs without this feature lack userspace cache flush instructions, requiring a syscall to maintain I/D cache coherence and propagate to remote caches. sys_loongarch_flush_icache() is defined to flush the instruction cache over an address range, with the flush applying to either all threads or just the caller. Currently all LoongArch64 implementations from Loongson comes with ICACHET, however most LoongArch32 implementations including openLA500 and emerging third party LoongArch64 implementations such as WiredNG are coming without ICACHET. Sadly many user space applications are assuming ICACHET support, we can't recall those binaries. So we'd better get UAPI for cacheflush ready soonish and encourage application to start using it. The syscall resolves to a ibar for now, it should be revised when we have actual non-ICACHET support in kernel. Signed-off-by: Jiaxun Yang --- arch/loongarch/include/asm/cacheflush.h | 6 ++++++ arch/loongarch/include/asm/syscall.h | 2 ++ arch/loongarch/kernel/Makefile.syscalls | 3 +-- arch/loongarch/kernel/syscall.c | 28 ++++++++++++++++++++++++++++ scripts/syscall.tbl | 2 ++ 5 files changed, 39 insertions(+), 2 deletions(-) diff --git a/arch/loongarch/include/asm/cacheflush.h b/arch/loongarch/inclu= de/asm/cacheflush.h index f8754d08a31ab07490717c31b9253871668b9a76..94f4a47f00860977db0b360965a= 22ff0a461c098 100644 --- a/arch/loongarch/include/asm/cacheflush.h +++ b/arch/loongarch/include/asm/cacheflush.h @@ -80,6 +80,12 @@ static inline void flush_cache_line(int leaf, unsigned l= ong addr) } } =20 +/* + * Bits in sys_loongarch_flush_icache()'s flags argument. + */ +#define SYS_LOONGARCH_FLUSH_ICACHE_LOCAL 1UL +#define SYS_LOONGARCH_FLUSH_ICACHE_ALL (SYS_LOONGARCH_FLUSH_ICACHE_LOCAL) + #include =20 #endif /* _ASM_CACHEFLUSH_H */ diff --git a/arch/loongarch/include/asm/syscall.h b/arch/loongarch/include/= asm/syscall.h index e286dc58476e6e6c5d126866a8590a96e4b4089a..6bd414a98a757de3c1bc78643fa= 1749f07efb1c0 100644 --- a/arch/loongarch/include/asm/syscall.h +++ b/arch/loongarch/include/asm/syscall.h @@ -71,4 +71,6 @@ static inline bool arch_syscall_is_vdso_sigreturn(struct = pt_regs *regs) return false; } =20 +asmlinkage long sys_loongarch_flush_icache(uintptr_t, uintptr_t, uintptr_t= ); + #endif /* __ASM_LOONGARCH_SYSCALL_H */ diff --git a/arch/loongarch/kernel/Makefile.syscalls b/arch/loongarch/kerne= l/Makefile.syscalls index ab7d9baa29152da97932c7e447a183fba265451c..11665e3000beffd24ef9d683a4a= c337554e0b320 100644 --- a/arch/loongarch/kernel/Makefile.syscalls +++ b/arch/loongarch/kernel/Makefile.syscalls @@ -1,4 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 =20 -# No special ABIs on loongarch so far -syscall_abis_64 +=3D +syscall_abis_64 +=3D loongarch diff --git a/arch/loongarch/kernel/syscall.c b/arch/loongarch/kernel/syscal= l.c index b267db6ed79c20199504247c181cc245ef86abfd..2bc164d972b4d41c39e91481803= d42bfd0184d3f 100644 --- a/arch/loongarch/kernel/syscall.c +++ b/arch/loongarch/kernel/syscall.c @@ -15,6 +15,7 @@ #include =20 #include +#include #include #include #include @@ -51,6 +52,33 @@ SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned lon= g, len, unsigned long, } #endif =20 +/* + * On LoongArch CPUs with ICACHET, writes automatically sync to both local= and + * remote instruction caches. CPUs without this feature lack userspace cac= he + * flush instructions, requiring a syscall to maintain I/D cache coherence= and + * propagate to remote caches. + * + * sys_loongarch_flush_icache() is defined to flush the instruction cache + * over an address range, with the flush applying to either all threads or + * just the caller. + */ +SYSCALL_DEFINE3(loongarch_flush_icache, uintptr_t, start, uintptr_t, end, + uintptr_t, flags) +{ + /* Check the reserved flags. */ + if (unlikely(flags & ~SYS_LOONGARCH_FLUSH_ICACHE_ALL)) + return -EINVAL; + + /* + * SYS_LOONGARCH_FLUSH_ICACHE_LOCAL is not handled so far, needs + * to be realized when non-ICACHET CPUs are supported. + */ + + flush_icache_user_range(start, end); + + return 0; +} + void *sys_call_table[__NR_syscalls] =3D { [0 ... __NR_syscalls - 1] =3D sys_ni_syscall, #ifdef CONFIG_64BIT diff --git a/scripts/syscall.tbl b/scripts/syscall.tbl index ebbdb3c42e9f74613b003014c0baf44c842bb756..723fe859956809f26d6ec50ad78= 12933531ef687 100644 --- a/scripts/syscall.tbl +++ b/scripts/syscall.tbl @@ -298,6 +298,8 @@ 244 csky set_thread_area sys_set_thread_area 245 csky cacheflush sys_cacheflush =20 +259 loongarch loongarch_flush_icache sys_loongarch_flush_icache + 244 nios2 cacheflush sys_cacheflush =20 244 or1k or1k_atomic sys_or1k_atomic --=20 2.43.0