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Thu, 2 Jan 2025 13:34:39 -0500 (EST) From: Jiaxun Yang Date: Thu, 02 Jan 2025 18:34:34 +0000 Subject: [PATCH 1/3] loongarch: Wire up 32 bit syscalls Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250102-la32-uapi-v1-1-db32aa769b88@flygoat.com> References: <20250102-la32-uapi-v1-0-db32aa769b88@flygoat.com> In-Reply-To: <20250102-la32-uapi-v1-0-db32aa769b88@flygoat.com> To: Huacai Chen , WANG Xuerui Cc: Arnd Bergmann , loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3169; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=RhHYt62GnA+7j7OdQEjolUMUreWyFbTQWM9dKssd6BA=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhvSyO3YuUouVpjG+er4lYqfpzDtn1le0FRzedOs1d99nP enedXUzOkpZGMS4GGTFFFlCBJT6NjReXHD9QdYfmDmsTCBDGLg4BWAiSkcZ/mmK33vgO/v1ROmb fO1+y66sEOKYUbUq3kX3r02upMrUYDmG/8VbpjTZn1xdLemy1yKm8pzp1C02/Twuv6awhfhFreH 4zAMA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 LoongArch 32-bit UAPI will be using generic syscall table, mostly identical with 64-bit one. It will follow the convention set by RISC-V, being the second 32 bit architecture without time32. Generate unisted_32.h and syscall_table_32.h as necessary, expose united_32.h in unisted.h UAPI, and implement mmap2 which is a part of 32 bit syscalls. Signed-off-by: Jiaxun Yang --- arch/loongarch/include/asm/Kbuild | 1 + arch/loongarch/include/uapi/asm/Kbuild | 1 + arch/loongarch/include/uapi/asm/unistd.h | 6 ++++++ arch/loongarch/kernel/syscall.c | 21 +++++++++++++++++++++ 4 files changed, 29 insertions(+) diff --git a/arch/loongarch/include/asm/Kbuild b/arch/loongarch/include/asm= /Kbuild index 80ddb5edb8455ce206fe1c67c3156c486c07b892..39c6c45e2a759cf900156197764= 64af0a52a5b9a 100644 --- a/arch/loongarch/include/asm/Kbuild +++ b/arch/loongarch/include/asm/Kbuild @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +syscall-y +=3D syscall_table_32.h syscall-y +=3D syscall_table_64.h generated-y +=3D orc_hash.h =20 diff --git a/arch/loongarch/include/uapi/asm/Kbuild b/arch/loongarch/includ= e/uapi/asm/Kbuild index 517761419999a898ab3d73b2568eea160795faec..89ac01faa5aef5f35837b8c4acc= 583082c30db53 100644 --- a/arch/loongarch/include/uapi/asm/Kbuild +++ b/arch/loongarch/include/uapi/asm/Kbuild @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +syscall-y +=3D unistd_32.h syscall-y +=3D unistd_64.h diff --git a/arch/loongarch/include/uapi/asm/unistd.h b/arch/loongarch/incl= ude/uapi/asm/unistd.h index 1f01980f9c94826957c9729c09c550cd090e4850..38c8bce307450f37b9cc72193c6= 999664a34b152 100644 --- a/arch/loongarch/include/uapi/asm/unistd.h +++ b/arch/loongarch/include/uapi/asm/unistd.h @@ -1,3 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ =20 +#include + +#if __BITS_PER_LONG =3D=3D 64 #include +#else +#include +#endif diff --git a/arch/loongarch/kernel/syscall.c b/arch/loongarch/kernel/syscal= l.c index 168bd97540f8cfc9be26d75843c5066c6630a0d2..b267db6ed79c20199504247c181= cc245ef86abfd 100644 --- a/arch/loongarch/kernel/syscall.c +++ b/arch/loongarch/kernel/syscall.c @@ -34,9 +34,30 @@ SYSCALL_DEFINE6(mmap, unsigned long, addr, unsigned long= , len, unsigned long, return ksys_mmap_pgoff(addr, len, prot, flags, fd, offset >> PAGE_SHIFT); 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Thu, 2 Jan 2025 13:34:41 -0500 (EST) From: Jiaxun Yang Date: Thu, 02 Jan 2025 18:34:35 +0000 Subject: [PATCH 2/3] loongarch: Introduce sys_loongarch_flush_icache syscall Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250102-la32-uapi-v1-2-db32aa769b88@flygoat.com> References: <20250102-la32-uapi-v1-0-db32aa769b88@flygoat.com> In-Reply-To: <20250102-la32-uapi-v1-0-db32aa769b88@flygoat.com> To: Huacai Chen , WANG Xuerui Cc: Arnd Bergmann , loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5030; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=w4f3TlGw9XqnVwPa+FzSha4Az1WTx3zGdxtidn31rb4=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhvSyO3Z/38ufjGVmL2Jc/6X52XGDO5dsV1QoV1YeUZtfU rz3E49MRykLgxgXg6yYIkuIgFLfhsaLC64/yPoDM4eVCWQIAxenAEzkaTrD/xiRSzWJuQV7/ITa q6qu/NrENflx2aKnJ/uTnqzY/15AyYvhf+Dq0+dbvjf9TZ1ZO1VoQrWMqqSJwRaHX12T75hvnV4 5mRcA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 On LoongArch CPUs with ICACHET, writes automatically sync to both local and remote instruction caches. CPUs without this feature lack userspace cache flush instructions, requiring a syscall to maintain I/D cache coherence and propagate to remote caches. sys_loongarch_flush_icache() is defined to flush the instruction cache over an address range, with the flush applying to either all threads or just the caller. Currently all LoongArch64 implementations from Loongson comes with ICACHET, however most LoongArch32 implementations including openLA500 and emerging third party LoongArch64 implementations such as WiredNG are coming without ICACHET. Sadly many user space applications are assuming ICACHET support, we can't recall those binaries. So we'd better get UAPI for cacheflush ready soonish and encourage application to start using it. The syscall resolves to a ibar for now, it should be revised when we have actual non-ICACHET support in kernel. Signed-off-by: Jiaxun Yang --- arch/loongarch/include/asm/cacheflush.h | 6 ++++++ arch/loongarch/include/asm/syscall.h | 2 ++ arch/loongarch/kernel/Makefile.syscalls | 3 +-- arch/loongarch/kernel/syscall.c | 28 ++++++++++++++++++++++++++++ scripts/syscall.tbl | 2 ++ 5 files changed, 39 insertions(+), 2 deletions(-) diff --git a/arch/loongarch/include/asm/cacheflush.h b/arch/loongarch/inclu= de/asm/cacheflush.h index f8754d08a31ab07490717c31b9253871668b9a76..94f4a47f00860977db0b360965a= 22ff0a461c098 100644 --- a/arch/loongarch/include/asm/cacheflush.h +++ b/arch/loongarch/include/asm/cacheflush.h @@ -80,6 +80,12 @@ static inline void flush_cache_line(int leaf, unsigned l= ong addr) } } =20 +/* + * Bits in sys_loongarch_flush_icache()'s flags argument. + */ +#define SYS_LOONGARCH_FLUSH_ICACHE_LOCAL 1UL +#define SYS_LOONGARCH_FLUSH_ICACHE_ALL (SYS_LOONGARCH_FLUSH_ICACHE_LOCAL) + #include =20 #endif /* _ASM_CACHEFLUSH_H */ diff --git a/arch/loongarch/include/asm/syscall.h b/arch/loongarch/include/= asm/syscall.h index e286dc58476e6e6c5d126866a8590a96e4b4089a..6bd414a98a757de3c1bc78643fa= 1749f07efb1c0 100644 --- a/arch/loongarch/include/asm/syscall.h +++ b/arch/loongarch/include/asm/syscall.h @@ -71,4 +71,6 @@ static inline bool arch_syscall_is_vdso_sigreturn(struct = pt_regs *regs) return false; } =20 +asmlinkage long sys_loongarch_flush_icache(uintptr_t, uintptr_t, uintptr_t= ); + #endif /* __ASM_LOONGARCH_SYSCALL_H */ diff --git a/arch/loongarch/kernel/Makefile.syscalls b/arch/loongarch/kerne= l/Makefile.syscalls index ab7d9baa29152da97932c7e447a183fba265451c..11665e3000beffd24ef9d683a4a= c337554e0b320 100644 --- a/arch/loongarch/kernel/Makefile.syscalls +++ b/arch/loongarch/kernel/Makefile.syscalls @@ -1,4 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 =20 -# No special ABIs on loongarch so far -syscall_abis_64 +=3D +syscall_abis_64 +=3D loongarch diff --git a/arch/loongarch/kernel/syscall.c b/arch/loongarch/kernel/syscal= l.c index b267db6ed79c20199504247c181cc245ef86abfd..2bc164d972b4d41c39e91481803= d42bfd0184d3f 100644 --- a/arch/loongarch/kernel/syscall.c +++ b/arch/loongarch/kernel/syscall.c @@ -15,6 +15,7 @@ #include =20 #include +#include #include #include #include @@ -51,6 +52,33 @@ SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned lon= g, len, unsigned long, } #endif =20 +/* + * On LoongArch CPUs with ICACHET, writes automatically sync to both local= and + * remote instruction caches. CPUs without this feature lack userspace cac= he + * flush instructions, requiring a syscall to maintain I/D cache coherence= and + * propagate to remote caches. + * + * sys_loongarch_flush_icache() is defined to flush the instruction cache + * over an address range, with the flush applying to either all threads or + * just the caller. + */ +SYSCALL_DEFINE3(loongarch_flush_icache, uintptr_t, start, uintptr_t, end, + uintptr_t, flags) +{ + /* Check the reserved flags. */ + if (unlikely(flags & ~SYS_LOONGARCH_FLUSH_ICACHE_ALL)) + return -EINVAL; + + /* + * SYS_LOONGARCH_FLUSH_ICACHE_LOCAL is not handled so far, needs + * to be realized when non-ICACHET CPUs are supported. + */ + + flush_icache_user_range(start, end); + + return 0; +} + void *sys_call_table[__NR_syscalls] =3D { [0 ... __NR_syscalls - 1] =3D sys_ni_syscall, #ifdef CONFIG_64BIT diff --git a/scripts/syscall.tbl b/scripts/syscall.tbl index ebbdb3c42e9f74613b003014c0baf44c842bb756..723fe859956809f26d6ec50ad78= 12933531ef687 100644 --- a/scripts/syscall.tbl +++ b/scripts/syscall.tbl @@ -298,6 +298,8 @@ 244 csky set_thread_area sys_set_thread_area 245 csky cacheflush sys_cacheflush =20 +259 loongarch loongarch_flush_icache sys_loongarch_flush_icache + 244 nios2 cacheflush sys_cacheflush =20 244 or1k or1k_atomic sys_or1k_atomic --=20 2.43.0 From nobody Thu Feb 12 23:03:15 2026 Received: from fhigh-a3-smtp.messagingengine.com (fhigh-a3-smtp.messagingengine.com [103.168.172.154]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9CD11B87C8; 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Thu, 2 Jan 2025 13:34:43 -0500 (EST) From: Jiaxun Yang Date: Thu, 02 Jan 2025 18:34:36 +0000 Subject: [PATCH 3/3] loongarch: vdso: Introduce __vdso_flush_icache function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250102-la32-uapi-v1-3-db32aa769b88@flygoat.com> References: <20250102-la32-uapi-v1-0-db32aa769b88@flygoat.com> In-Reply-To: <20250102-la32-uapi-v1-0-db32aa769b88@flygoat.com> To: Huacai Chen , WANG Xuerui Cc: Arnd Bergmann , loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6056; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=yOrtMqTEXajMX/FmL8KpbG69isM181QHBtawwM9Q2fc=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhvSyO3avLnAolIdL3+PyClOY/MVxXwCP8ARNNrmJd7j1u w6cV/neUcrCIMbFICumyBIioNS3ofHigusPsv7AzGFlAhnCwMUpABOZGsTw35lt6S0lt8OLz1k2 ihTwzVC7cme2WqP1vumHJd1Cs/6kz2VkmK74OXm1vIbd4qcnPhQY7PxWmfoy9e+a017u92aLv6u 24wUA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Introduce __vdso_flush_icache function for performing cache flush in userspace whenever possible. It will use ibar in userspace if CPU comes with ICACHET support, and fallback to syscall if not. It also made infra ready for possible future userspace cache flush instruction. Signed-off-by: Jiaxun Yang --- arch/loongarch/include/asm/vdso/vdso.h | 10 ++++++ arch/loongarch/include/asm/vdso/vsyscall.h | 1 + arch/loongarch/kernel/vdso.c | 2 ++ arch/loongarch/mm/cache.c | 3 ++ arch/loongarch/vdso/Makefile | 2 +- arch/loongarch/vdso/flush_icache.c | 50 ++++++++++++++++++++++++++= ++++ arch/loongarch/vdso/vdso.lds.S | 5 +++ 7 files changed, 72 insertions(+), 1 deletion(-) diff --git a/arch/loongarch/include/asm/vdso/vdso.h b/arch/loongarch/includ= e/asm/vdso/vdso.h index 1c183a9b2115a29a997ec8db0e788d87fb191dce..215b8c85fb2347a2ba9b53167a4= 343086efb9af3 100644 --- a/arch/loongarch/include/asm/vdso/vdso.h +++ b/arch/loongarch/include/asm/vdso/vdso.h @@ -13,6 +13,15 @@ #include #include =20 +enum vdso_icacle_flush_mode { + VDSO_ICACLE_FLUSH_IBAR, + VDSO_ICACLE_FLUSH_FALLBACK, +}; + +struct vdso_icache_flush_data { + enum vdso_icacle_flush_mode mode; +}; + struct vdso_pcpu_data { u32 node; } ____cacheline_aligned_in_smp; @@ -20,6 +29,7 @@ struct vdso_pcpu_data { struct loongarch_vdso_data { struct vdso_pcpu_data pdata[NR_CPUS]; struct vdso_rng_data rng_data; + struct vdso_icache_flush_data icache_flush_data; }; =20 /* diff --git a/arch/loongarch/include/asm/vdso/vsyscall.h b/arch/loongarch/in= clude/asm/vdso/vsyscall.h index 8987e951d0a93c34ca75de676fb9c191ff4ef3c2..a02663ddf7cdccbe4b0e4c4d87b= 65874ab14070a 100644 --- a/arch/loongarch/include/asm/vdso/vsyscall.h +++ b/arch/loongarch/include/asm/vdso/vsyscall.h @@ -8,6 +8,7 @@ =20 extern struct vdso_data *vdso_data; extern struct vdso_rng_data *vdso_rng_data; +extern struct vdso_icache_flush_data *vdso_icache_flush_data; =20 static __always_inline struct vdso_data *__loongarch_get_k_vdso_data(void) diff --git a/arch/loongarch/kernel/vdso.c b/arch/loongarch/kernel/vdso.c index 05e5fbac102a902016e633db75d9aff7ed550c50..4085452b3e1081e115d346f5870= d54dad5c6ef54 100644 --- a/arch/loongarch/kernel/vdso.c +++ b/arch/loongarch/kernel/vdso.c @@ -36,6 +36,8 @@ static union { struct vdso_data *vdso_data =3D generic_vdso_data.data; struct vdso_pcpu_data *vdso_pdata =3D loongarch_vdso_data.vdata.pdata; struct vdso_rng_data *vdso_rng_data =3D &loongarch_vdso_data.vdata.rng_dat= a; +struct vdso_icache_flush_data *vdso_icache_flush_data =3D + &loongarch_vdso_data.vdata.icache_flush_data; =20 static int vdso_mremap(const struct vm_special_mapping *sm, struct vm_area= _struct *new_vma) { diff --git a/arch/loongarch/mm/cache.c b/arch/loongarch/mm/cache.c index 6be04d36ca0769658a2b52d25af50dd6ad7e07e0..a424a9b24827e5eb83a8d4db7da= 76b42ba3f4d8b 100644 --- a/arch/loongarch/mm/cache.c +++ b/arch/loongarch/mm/cache.c @@ -24,6 +24,7 @@ #include #include #include +#include =20 void cache_error_setup(void) { @@ -156,6 +157,8 @@ void cpu_cache_init(void) =20 current_cpu_data.cache_leaves_present =3D leaf; current_cpu_data.options |=3D LOONGARCH_CPU_PREFETCH; + + vdso_icache_flush_data->mode =3D VDSO_ICACLE_FLUSH_IBAR; } =20 static const pgprot_t protection_map[16] =3D { diff --git a/arch/loongarch/vdso/Makefile b/arch/loongarch/vdso/Makefile index fdde1bcd4e2663bd400dcc6becc4261b7d5dce3a..8407d85548a4d4ff03571f35317= ba2a0881f684c 100644 --- a/arch/loongarch/vdso/Makefile +++ b/arch/loongarch/vdso/Makefile @@ -4,7 +4,7 @@ # Include the generic Makefile to check the built vdso. include $(srctree)/lib/vdso/Makefile =20 -obj-vdso-y :=3D elf.o vgetcpu.o vgettimeofday.o vgetrandom.o \ +obj-vdso-y :=3D elf.o flush_icache.o vgetcpu.o vgettimeofday.o vgetrandom.= o \ vgetrandom-chacha.o sigreturn.o =20 # Common compiler flags between ABIs. diff --git a/arch/loongarch/vdso/flush_icache.c b/arch/loongarch/vdso/flush= _icache.c new file mode 100644 index 0000000000000000000000000000000000000000..e1f95572175a0bf4c136afd1107= ea2f8d8933b21 --- /dev/null +++ b/arch/loongarch/vdso/flush_icache.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Fast user context implementation of getcpu() + */ + +#include +#include + +static int flush_icache_ibar(void) +{ + __asm__ __volatile__ ("\tibar 0\n"::); + + return 0; +} + +static int flush_icache_fallback(uintptr_t start, uintptr_t end, + uintptr_t flags) +{ + register long _num __asm__ ("a7") =3D __NR_loongarch_flush_icache; + register long _arg1 __asm__ ("a0") =3D (long)(start); + register long _arg2 __asm__ ("a1") =3D (long)(end); + register long _arg3 __asm__ ("a2") =3D (long)(flags); + + __asm__ volatile ( + "syscall 0\n" + : "+r"(_arg1) + : "r"(_arg2), "r"(_arg3), + "r"(_num) + : "memory", "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", + "$t6", "$t7", "$t8" + ); + + return _arg1; +} + +extern int __vdso_flush_icache(uintptr_t start, uintptr_t end, + uintptr_t flags); +int __vdso_flush_icache(uintptr_t start, uintptr_t end, uintptr_t flags) +{ + + switch (_loongarch_data.icache_flush_data.mode) { + case VDSO_ICACLE_FLUSH_IBAR: + return flush_icache_ibar(); + case VDSO_ICACLE_FLUSH_FALLBACK: + default: + return flush_icache_fallback(start, end, flags); + } + + return -EINVAL; +} diff --git a/arch/loongarch/vdso/vdso.lds.S b/arch/loongarch/vdso/vdso.lds.S index 160cfaef2de45b1243502c7356f8a913658548fe..a1023d10fbb7b45c2a70ead0304= c2753c05f9654 100644 --- a/arch/loongarch/vdso/vdso.lds.S +++ b/arch/loongarch/vdso/vdso.lds.S @@ -72,6 +72,11 @@ VERSION __vdso_rt_sigreturn; local: *; }; + LINUX_6.14 { + global: + __vdso_flush_icache; + local: *; + }; } =20 /* --=20 2.43.0