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Thu, 2 Jan 2025 09:05:16 -0500 (EST) From: Jiaxun Yang Date: Thu, 02 Jan 2025 14:05:17 +0000 Subject: [PATCH] loongarch: time: Derive max_delta from prcfg1 tmrbits Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250102-la-misc-v1-1-8dc7db525e54@flygoat.com> X-B4-Tracking: v=1; b=H4sIAByddmcC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIxNDIyNj3ZxE3dzM4mTdFDNDgxRDkzRLE/NUJaDqgqLUtMwKsEnRsbW1AEa unptZAAAA X-Change-ID: 20241223-la-misc-d610d14f947e To: Huacai Chen , WANG Xuerui Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2205; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=+5CGF9O/RU57EIjL3m6Q442i1J5aD7OVorgwgr+zyFE=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhvSyuXInH/o5Ggc8Lr5h0pP+uLhtnatRV9yOKS/XJdc3P Visy2TWUcrCIMbFICumyBIioNS3ofHigusPsv7AzGFlAhnCwMUpABMxPcfwV3Dz3V+VXCk3N9W/ PudQVv587eWUuLuvAiZfYZQpTdtQy8fw3+nhBFPJrzIvdjnav71i+fTX8bcTV5hwVmdM7uS9/PJ /FycA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 As per arch spec, maximum timer bits is configurable and should not be hardcoded in any way. Use prcfg1 tmrbits to determine clockevent's max_delta to be conformance. Signed-off-by: Jiaxun Yang --- LA32R doesn't have prcfg, maybe we should handle this during cpu-probe and save it in cpuinfo_loongarch, What's your opinion, Huacai? --- arch/loongarch/include/asm/loongarch.h | 1 - arch/loongarch/kernel/time.c | 7 ++++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/includ= e/asm/loongarch.h index 64ad277e096edd7d77af6f37e234d68e571764a4..a3cc4f8d4c4a0b0521ef2b76c87= fa57eca417d75 100644 --- a/arch/loongarch/include/asm/loongarch.h +++ b/arch/loongarch/include/asm/loongarch.h @@ -466,7 +466,6 @@ =20 #define LOONGARCH_CSR_TCFG 0x41 /* Timer config */ #define CSR_TCFG_VAL_SHIFT 2 -#define CSR_TCFG_VAL_WIDTH 48 #define CSR_TCFG_VAL (_ULCAST_(0x3fffffffffff) << CSR_TCFG_VAL_SHIFT) #define CSR_TCFG_PERIOD_SHIFT 1 #define CSR_TCFG_PERIOD (_ULCAST_(0x1) << CSR_TCFG_PERIOD_SHIFT) diff --git a/arch/loongarch/kernel/time.c b/arch/loongarch/kernel/time.c index a07d7eff4dc5fb0f41f5fad02698ff7a84c7bc8a..bde2297f139c2d5e26894a2ebc1= 748cc6fef3146 100644 --- a/arch/loongarch/kernel/time.c +++ b/arch/loongarch/kernel/time.c @@ -126,16 +126,21 @@ void sync_counter(void) =20 int constant_clockevent_init(void) { + uint32_t tmrbits; unsigned int cpu =3D smp_processor_id(); #ifdef CONFIG_PREEMPT_RT unsigned long min_delta =3D 100; #else unsigned long min_delta =3D 1000; #endif - unsigned long max_delta =3D (1UL << 48) - 1; + unsigned long max_delta; struct clock_event_device *cd; static int irq =3D 0, timer_irq_installed =3D 0; =20 + tmrbits =3D read_csr_prcfg1() & CSR_CONF1_TMRBITS; + tmrbits =3D tmrbits >> CSR_CONF1_TMRBITS_SHIFT; + max_delta =3D CLOCKSOURCE_MASK(tmrbits + 1); + if (!timer_irq_installed) { irq =3D get_percpu_irq(INT_TI); if (irq < 0) --- base-commit: 8155b4ef3466f0e289e8fcc9e6e62f3f4dceeac2 change-id: 20241223-la-misc-d610d14f947e Best regards, --=20 Jiaxun Yang