From nobody Thu Feb 12 23:06:00 2026 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B300113E88C for ; Thu, 2 Jan 2025 16:34:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735835654; cv=none; b=FaONw5j1y4GXpYlwhyU60r1lQAm+vRSHLM/KcyT/pqE4sczZFpTbXD3QhJqcgsId/uOVu1qAfo9RxSSAWQZGieHxD5ud1ZhYRWDeUjUPoViwgWB5i5WEwrEGw/TLMxDPcljwR3wXUoDZ42y/ml28dvZClim2F+NbVxRBSyNItVg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735835654; c=relaxed/simple; bh=Zvz8R0sKXW+v8S3Bhes44t7kDwn4HoqHd22h8a2tqs8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FjipUyk8CdNPkOotKpGHVpLjEDZV+AWpMzrRIKqhDIuXI+01fYZNjD5iP/Jkajc5EkKZgZPZ3CeWA2xNn3etvZCHTPHtfwe6tUgLXJVtMaYXS6X4AMvrt8xe6uOOjegRk/LsP0Yo93Hp2RPhW7BXd3fpKVSRg5NnHVW7TYCQCac= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=GXPsb/iD; arc=none smtp.client-ip=209.85.221.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="GXPsb/iD" Received: by mail-wr1-f54.google.com with SMTP id ffacd0b85a97d-385ef8b64b3so9076251f8f.0 for ; Thu, 02 Jan 2025 08:34:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1735835650; x=1736440450; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=LRM8PRQcYeaW9hfyEb3e4N6uuVKnpIRL7yayrrVI6Qw=; b=GXPsb/iDDUeQ7ANXvfwKg9CPm8tP0GHZ2l68ywOt3WrkndYVJn2kny7xg5EU3F2d5S tyy6nTYUbntdopshf17JrCXkGLdvp2vzuF7Z2bGqeYxfdIIyWReENTltKqMexlnW4NN1 dmgviT5PubyHn7uLfGsuAsdkMO6sJUeMUg2yjcu4+HsrZxBO4KFL8vVbyEJLQGqEUljX 0+v6towTZlXCLjb+8BK02bGsFNEPu2m83ymeGlAHpf5R8izWDWifw+v4FcVVBwBdrMlX zJ/sWVeaUP/J6XKkq/GDATPKTacDhiCXHiGaaYWrvdzLDxDNDSDvM72Y9MjlVk6WEMCN pvRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735835650; x=1736440450; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LRM8PRQcYeaW9hfyEb3e4N6uuVKnpIRL7yayrrVI6Qw=; b=OgHPdETPnSk749pc85TcaudiafTc0WG98ZBo4J00gpZ5tyx5mioJToDPcEsxVqKmyB oXw1w2rDPUhGfAK0EhgA+t1ASDYX567/2huI+dfktO/MrUcGkQWIUO/jQLsBJ/L6ZjrI xQPB7j/g1pdEW48KV5dLmmok5n6W5T5AOnmkHWlL1oQOeV6EXmZ/DalY0H8u6ILkh6Cm EFZR6A3FE13WJirESGH7PB/ggYQTQUdVsBnsrSEXaaZqQaxog0fVwgZH7cwkDfw5ViQb N5ysB28ee1fdZqgWQgkrXiDLFfsINlCzpCtZ7T1cZORF32qF3iWbWD7GpzxLGTRZFG/L 0eTg== X-Forwarded-Encrypted: i=1; AJvYcCUdKng3v5eltIlKgyQSvrI1HMWgQ/9bbYcYtuv3Fat7y1/+UpXEt9R3vBAYHKV/08p80w5fDywBOmhfCrk=@vger.kernel.org X-Gm-Message-State: AOJu0YxKUB3D6yTc6AHXOSd84ugcob7amGUdpkRVJBO8Jg+AjKd+sLBl rrJ0tYo4TKOInVVwx1o+bcPWnW7LS4Yrb0fwBC9Nv+dgGDJ14rmayBQFDzsqIw0= X-Gm-Gg: ASbGncvsS/67uPqGcD1CE9eHn0eT7bgwNxk1olA7KYOaFjSoVG1BC2l8CJolLsQ1yFP QBeKDQL2dQ4fsGKz8cAtmLB7t9/WrPK15rvdi5ty0pkUUb1dejed2QxWYvOf6WDy7GavKuYSxXN dMHptJknSaf+Rne5N7X3Yy20Xem5G898YzTNoQ/YQk0s/nLz2vxCPRjcigjfdSn0gfqleTtlhV5 KJYyar4DF17KAXgFntp1ScAACwdJPMbbS1VhgUtf9ZMduRqhdSYTjkrLFqyA+xL7A== X-Google-Smtp-Source: AGHT+IGZKYxx/OlYnS6ngsg5g+Cup4DnewIH5nbGpaqK7uKGJpkBI9NyYRPPLk8irCMYMufLgwLxmg== X-Received: by 2002:a05:6000:1a8e:b0:386:407c:40b9 with SMTP id ffacd0b85a97d-38a221fe0ddmr36101367f8f.28.1735835649785; Thu, 02 Jan 2025 08:34:09 -0800 (PST) Received: from [127.0.1.1] ([176.61.106.227]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43656b3b295sm499265665e9.33.2025.01.02.08.34.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jan 2025 08:34:09 -0800 (PST) From: Bryan O'Donoghue Date: Thu, 02 Jan 2025 16:32:06 +0000 Subject: [PATCH v3 1/6] dt-bindings: i2c: qcom-cci: Document x1e80100 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-1-cb66d55d20cc@linaro.org> References: <20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-0-cb66d55d20cc@linaro.org> In-Reply-To: <20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-0-cb66d55d20cc@linaro.org> To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Mauro Carvalho Chehab , Bjorn Andersson , Michael Turquette , Stephen Boyd , Vladimir Zapolskiy , Jagadeesh Kona , Konrad Dybcio Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Krzysztof Kozlowski X-Mailer: b4 0.15-dev-1b0d6 Add the x1e80100 CCI device string compatible. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bryan O'Donoghue --- Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Docu= mentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml index ef26ba6eda28e95875853fe5043fe11deb5af088..73144473b9b24e574bfc6bd7d89= 08f2f3895e087 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml @@ -34,6 +34,7 @@ properties: - qcom,sm8450-cci - qcom,sm8550-cci - qcom,sm8650-cci + - qcom,x1e80100-cci - const: qcom,msm8996-cci # CCI v2 =20 "#address-cells": @@ -224,6 +225,7 @@ allOf: enum: - qcom,sm8550-cci - qcom,sm8650-cci + - qcom,x1e80100-cci then: properties: clocks: --=20 2.45.2 From nobody Thu Feb 12 23:06:00 2026 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E7DB5914C for ; Thu, 2 Jan 2025 16:34:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735835656; cv=none; b=buxu8nts+i+hFjK+Fo331tXUTTlw9dKybdiOtACQt3dxlxJ08yiB5iPvGcnGXNbLKxGiL7dZYD0hPVjjjsXcNL0DyP9pAOzLcz5gcE5O1CEBPvzobhTkmXf/Zx3XRT5gYBjavs7iJrG6cl1gCMB14P/rygFk55TjWViZ90JsFhs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735835656; c=relaxed/simple; bh=40WKbX29Iuf0zZZzggGz1hwKcr+5M95z+Oavg/DIjfU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aZYydZ6tuk+S9e2tGwqBssCUp1dKtvQFfGvTCNqJYzNaN1Om/fFFXuXmXaiFnOIh7Se9K9YuU+xzoR/rpsLrw9173qk7PNuzS82HvFAT4Y4Tm6xaIR5evCw6HmmpJVBGEOjerN7UhInzJsJTVf2VAT+mo8Z5inXeQF2CBN4tQ40= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=Kv8JZtlB; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Kv8JZtlB" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-4363ae65100so119814295e9.0 for ; Thu, 02 Jan 2025 08:34:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1735835651; x=1736440451; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=OFa9CDvSl76k0Hh3vGlZYLlV6eb7UtNlguj/xJD/WKM=; b=Kv8JZtlBOgo+V15XJQ9fo5QiBS1pIXFgyYHCNR469DkqtNBzPaJxbXx1eDv5e2iEDJ WZeZXM52Lk71Il3HFI3RASPrvEH4Hq/N10PIsgzZ79W98q+Pfpnx59coEJczwoS5cZJu 4PsCYRDqoO6SWG6Kb1o8q+Pg8UQ5bbPJVKswQAWQznNmqBzOzmGH0h706f95eF9lzOju 2+qdMFTN1CqG9e5Ui+JP0q9rtXnKag+rcHeOxGdEkCsv9kkk3a0KiskUbI89Re+IJ7AR 4Hl1bXzW31dU6VgcApiWCb+L8OFQx83EPEvdgXG4y7/WSkU2YRFrQAYTvLDKLVWmePtV bFAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735835651; x=1736440451; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OFa9CDvSl76k0Hh3vGlZYLlV6eb7UtNlguj/xJD/WKM=; b=ln3iBiiAx9qXIgSUEFjdgoF/Sl9cOAo0CJb6UhW134EVjdT0+5Mvw52jDTuRhKJ7Nt CCmiI1uMIJJq/3WFNt/t0KxalDduu2g0UnrqKVrB9DeYEVDP8mCL1rf8/sjRb2EfKxoM 0IMDroREZg9K+rLbND7eO092lOM6d/E852gf86BONdOBL7h9mM3V1y83dgbPWt2C3YPe JmWiKqW8ueocJCed8Dlk3CWd+/tIGSDqeOeOWpXI+BfsjsB1rg/tSNrCXOBQiRfCkxhP sbdQNwbjh6rcnZ8WFZPN+FhLWtJ16HQpcOmDRStkTwmQ9QS/Y4k8mKXdCRRW6J8SWNGd AJXQ== X-Forwarded-Encrypted: i=1; AJvYcCXSYJ9OdH+flCkH/JsFfxnWmEB9FnZ0rbHjXbmoRj70e6zKunyMWiffC3GOc4HoWWZAHsf3cIsrhA220s0=@vger.kernel.org X-Gm-Message-State: AOJu0Yzf+/EEIxCWzP2tPlGD2jjIzPnFwQmy2QLy7HVD8ATobGzJ9E3k LlpKTdkqTLrf1dc5n0ZgSNwIpypwexYZBYX1dtS56lPbIGyObl9Ce/HbPEa8bqw= X-Gm-Gg: ASbGnctuEhC4i8eHeWZ0EVZ7lUGRyKpmzvJZNsjziuwhVDGcQAFjcQK3yLrKkT3pn3V k7zY5A0IAj/u8yt5euopieku6P/6LD4dSg5NycWvci5SFhLC4IaulbCvr3CacxyvFFrNpyGFt6L o43Kg6sblDO2x/tFLX81ixI7xZC+1KutcnM2Tj1cJNGCJgkR0WGQIkymgaGmxo/guUgPMDx4HHD uNQx6ceIjKD8XqDioA9tJE1qCYZuJVSG/sOCnUWBICmU5RJWJdPBUumyLqnNlBbvg== X-Google-Smtp-Source: AGHT+IHWgH76ldo5RFigeNbW999eG6qs/T9kBRAOvHKJHVOur8IF0AIVTPV3mVfNpHNdb+0us1WqcA== X-Received: by 2002:a05:600c:5246:b0:434:a781:f5d9 with SMTP id 5b1f17b1804b1-4366854c073mr381151545e9.11.1735835651405; Thu, 02 Jan 2025 08:34:11 -0800 (PST) Received: from [127.0.1.1] ([176.61.106.227]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43656b3b295sm499265665e9.33.2025.01.02.08.34.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jan 2025 08:34:10 -0800 (PST) From: Bryan O'Donoghue Date: Thu, 02 Jan 2025 16:32:07 +0000 Subject: [PATCH v3 2/6] dt-bindings: clock: move qcom,x1e80100-camcc to its own file Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-2-cb66d55d20cc@linaro.org> References: <20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-0-cb66d55d20cc@linaro.org> In-Reply-To: <20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-0-cb66d55d20cc@linaro.org> To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Mauro Carvalho Chehab , Bjorn Andersson , Michael Turquette , Stephen Boyd , Vladimir Zapolskiy , Jagadeesh Kona , Konrad Dybcio Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Krzysztof Kozlowski X-Mailer: b4 0.15-dev-1b0d6 Add an x1e80100 camcc binding. x1e80100 has two power-domain parents unlike other similar camcc controllers. Differentiate the new structure into a unique camcc definition. Other similar camcc controller setups can then be easily added to this one. Suggested-by: Krzysztof Kozlowski Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bryan O'Donoghue --- .../bindings/clock/qcom,sm8450-camcc.yaml | 2 - .../bindings/clock/qcom,x1e80100-camcc.yaml | 74 ++++++++++++++++++= ++++ 2 files changed, 74 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml= b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index 0766f66c7dc4f6b81afa01f156c490f4f742fcee..b88b6c9b399a4f8f3c67dd03e6c= fc306963b868f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -19,7 +19,6 @@ description: | include/dt-bindings/clock/qcom,sm8450-camcc.h include/dt-bindings/clock/qcom,sm8550-camcc.h include/dt-bindings/clock/qcom,sm8650-camcc.h - include/dt-bindings/clock/qcom,x1e80100-camcc.h =20 properties: compatible: @@ -29,7 +28,6 @@ properties: - qcom,sm8475-camcc - qcom,sm8550-camcc - qcom,sm8650-camcc - - qcom,x1e80100-camcc =20 clocks: items: diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.ya= ml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..5bbbaa15a26090186e4ee4397ec= ba2f3c2541672 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,x1e80100-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller on x1e80100 + +maintainers: + - Bryan O'Donoghue + +description: | + Qualcomm camera clock control module provides the clocks, resets and pow= er + domains on x1e80100. + + See also: + include/dt-bindings/clock/qcom,x1e80100-camcc.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + enum: + - qcom,x1e80100-camcc + + reg: + maxItems: 1 + + clocks: + items: + - description: Camera AHB clock from GCC + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + + power-domains: + items: + - description: A phandle to the MXC power-domain + - description: A phandle to the MMCX power-domain + + required-opps: + maxItems: 1 + description: + A phandle to an OPP node describing MMCX performance points. + +required: + - compatible + - clocks + - power-domains + - required-opps + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + clock-controller@ade0000 { + compatible =3D "qcom,x1e80100-camcc"; + reg =3D <0xade0000 0x20000>; + clocks =3D <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains =3D <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; +... --=20 2.45.2 From nobody Thu Feb 12 23:06:00 2026 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07913364D6 for ; Thu, 2 Jan 2025 16:34:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735835659; cv=none; b=pK5QnlsZ/CAPRtPvkbqCnvrGSMMOFZq4MmWMO6KAsEHMB/yjKhIwh4nqCQEIc1LJH7H5+1twnE4E/ZaWORkL+NtgsBzPcVkvtTYk8XWwiUcumjGcbDJsxhhBFvQYVKa78IsgbguCZ0NLyFEGnq3ObZm+eX4qhsq4qXqbp/ofjZ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735835659; c=relaxed/simple; bh=jDxdaZzPwCOq55/yTS+t/36ZjSRJTk6rJgDItrVZn80=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Kv+otXrrU4bqOP128PSfbEnLgq9BmRG4TvWCjzx1p5egG3OOjDwx8QukLWcYjk+4nVyDJirf7VuuPZjSnJZYVY/A8sS+/j7V+lek9fS+z5yiKrrB/+II9/S48kGtk+MsVTc0xATz1KBumBoa1c/hPKFcLkNI2r64Af4g4pkAI90= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=PFK0jy8T; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="PFK0jy8T" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-4361f796586so119610895e9.3 for ; Thu, 02 Jan 2025 08:34:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1735835653; x=1736440453; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=8yUM0RNJJgcqSmEds7ciwc93PUjJ/ydQeWI69fYTvlA=; b=PFK0jy8T+PL8GwBIf1InzfTz6ZlwCwddnhcri3zmdewyxeEf/u4gLf6RAl9v9oVmKn V21XPFYJbDzzXOoec70xLv63PiwqJS4D953ky2Vln6u1gS8giHcnZJqQ3mhzREAqkfQ7 y/1VMwqJyWoRAy9tW2+t0zOtHTcawE+jJvQrWdzdpZTOLBENja3ySjRzKzEuoLOiUabw QUSGmDyGrJ6Mxg0JUSmLJa3B0kY2BWNxv0NWL9BaWZdhQWwAzA5julyAuLyrzo0dUq1f elOMOWJqnjV2P2eyCOvQmElur4vA4rZQz8ZM+x7acCLrOHgqbZDS16igiyas+PdSAVFv xekA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735835653; x=1736440453; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8yUM0RNJJgcqSmEds7ciwc93PUjJ/ydQeWI69fYTvlA=; b=WtDGPqwKYxnoo3yzQ8CJaW6LI2BgYKymUnImfQWsQd+NPpWp1NvKPukCRvCMLP45hk xPYZxeNec1t25Q8Kv6z64Wr8eKARsUhsjwQRMn8RgN0PYGD5Zu+HB10dUsUbhPFuGeNv hv5yoNpkfiyqgSNXJf1+uQWm7N/tUMcfXVi0r3/+7NYLHWqOtLnD1St5c2rnlkli01yz sha7QFK8kk8MklYpOnwGnXqdcrq3sMXQ1NfaC7BMkp2adBTCxA705SexsjIastr8lpvV i0WW5zqBMPJCkWz36gN1qBg7QDf1h//Lyal/bH0RKSGu41seb8FIAv8jJH9C6DZtsstM g6tw== X-Forwarded-Encrypted: i=1; AJvYcCW+Xxj0fb6qVHDChv7awW6Chhtw/7wTqSzNqJwf710eDN9AItBqLNWygSI1X+fSF2aVgnEBN2ZtJM2JFpc=@vger.kernel.org X-Gm-Message-State: AOJu0YyV1eve+gqsaaE7NNXis46wJDBUszwbblA2OWjoom1+SNdB3yde 3FVH4ttPjgI7hdaMJ1+/iLbv1t9aDg09ss1YE2bNKu//7Htw+I+6TdTmCKba/To= X-Gm-Gg: ASbGncutRfDsiEIdnszocIv+29HAXFq6hC4pZGTftBlIaTumxqWJUGnYk9b/Dc5QjYU mtbvhwMDXBEw1sd/EX7GolvPaUu8GSjbn0hq7pI0LdaU/kdctF5n8xUEnTytvIO5T/h4GRGQbvo FD9CJ9LvXTckUtRYXqNQhHuNgTS/H54uFnqiWuY0YvsfpT+Ovpmf/vxcZYIklIKXKBa0573euaP p1BlffyCrYhXdoiG6dkXXaYqg+bYsoV2h04K915BHMMuqsIh89URPr1zYx7IAfmWA== X-Google-Smtp-Source: AGHT+IEQ9KTFtjYbnvIG9Zf8XWVBb/RDHKNMPX07pyCVGnjheUSHmki6X++hZkyg/nNOenJ1zpvlXA== X-Received: by 2002:a05:600c:350c:b0:434:9ec0:9e4e with SMTP id 5b1f17b1804b1-43668b5f6f7mr421704515e9.30.1735835652991; Thu, 02 Jan 2025 08:34:12 -0800 (PST) Received: from [127.0.1.1] ([176.61.106.227]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43656b3b295sm499265665e9.33.2025.01.02.08.34.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jan 2025 08:34:12 -0800 (PST) From: Bryan O'Donoghue Date: Thu, 02 Jan 2025 16:32:08 +0000 Subject: [PATCH v3 3/6] dt-bindings: media: Add qcom,x1e80100-camss Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-3-cb66d55d20cc@linaro.org> References: <20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-0-cb66d55d20cc@linaro.org> In-Reply-To: <20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-0-cb66d55d20cc@linaro.org> To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Mauro Carvalho Chehab , Bjorn Andersson , Michael Turquette , Stephen Boyd , Vladimir Zapolskiy , Jagadeesh Kona , Konrad Dybcio Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Krzysztof Kozlowski X-Mailer: b4 0.15-dev-1b0d6 Add bindings for qcom,x1e80100-camss in order to support the camera subsystem for x1e80100 as found in various Co-Pilot laptops. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bryan O'Donoghue --- .../bindings/media/qcom,x1e80100-camss.yaml | 367 +++++++++++++++++= ++++ 1 file changed, 367 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.ya= ml b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml new file mode 100644 index 0000000000000000000000000000000000000000..88eeac262f0e2974d1df43e0df7= 513fffbebd05c --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml @@ -0,0 +1,367 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,x1e80100-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm X1E80100 Camera Subsystem (CAMSS) + +maintainers: + - Bryan O'Donoghue + +description: | + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,x1e80100-camss + + reg: + maxItems: 17 + + reg-names: + items: + - const: csid_wrapper + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy4 + - const: csitpg0 + - const: csitpg1 + - const: csitpg2 + - const: vfe_lite0 + - const: vfe_lite1 + - const: vfe0 + - const: vfe1 + + clocks: + maxItems: 29 + + clock-names: + items: + - const: camnoc_rt_axi + - const: camnoc_nrt_axi + - const: core_ahb + - const: cpas_ahb + - const: cpas_fast_ahb + - const: cpas_vfe0 + - const: cpas_vfe1 + - const: cpas_vfe_lite + - const: cphy_rx_clk_src + - const: csid + - const: csid_csiphy_rx + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy4 + - const: csiphy4_timer + - const: gcc_axi_hf + - const: gcc_axi_sf + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + + interrupts: + maxItems: 13 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy4 + - const: vfe0 + - const: vfe1 + - const: vfe_lite0 + - const: vfe_lite1 + + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: cam_ahb + - const: cam_hf_mnoc + - const: cam_sf_mnoc + - const: cam_sf_icp_mnoc + + iommus: + maxItems: 8 + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switc= h Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switc= h Controller. + - description: Titan Top GDSC - Titan ISP Block, Global Distributed = Switch Controller. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: top + + vdd-csiphy-0p8-supply: + description: + Phandle to a 0.8V regulator supply to a PHY. + + vdd-csiphy-1p2-supply: + description: + Phandle to 1.8V regulator supply to a PHY. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + patternProperties: + "^port@[0-3]+$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + + description: + Input port for receiving CSI data from a CSIPHY. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + - vdd-csiphy-0p8-supply + - vdd-csiphy-1p2-supply + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + camss: isp@acb6000 { + compatible =3D "qcom,x1e80100-camss"; + + reg =3D <0 0x0acb6000 0 0x1000>, + <0 0x0acb7000 0 0x2000>, + <0 0x0acb9000 0 0x2000>, + <0 0x0acbb000 0 0x2000>, + <0 0x0acc6000 0 0x1000>, + <0 0x0acca000 0 0x1000>, + <0 0x0ace4000 0 0x1000>, + <0 0x0ace6000 0 0x1000>, + <0 0x0ace8000 0 0x1000>, + <0 0x0acec000 0 0x4000>, + <0 0x0acf6000 0 0x1000>, + <0 0x0acf7000 0 0x1000>, + <0 0x0acf8000 0 0x1000>, + <0 0x0acc7000 0 0x2000>, + <0 0x0accb000 0 0x2000>, + <0 0x0ac62000 0 0x4000>, + <0 0x0ac71000 0 0x4000>; + + reg-names =3D "csid_wrapper", + "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4", + "csitpg0", + "csitpg1", + "csitpg2", + "vfe_lite0", + "vfe_lite1", + "vfe0", + "vfe1"; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + + clock-names =3D "camnoc_rt_axi", + "camnoc_nrt_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe_lite", + "cphy_rx_clk_src", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy4", + "csiphy4_timer", + "gcc_axi_hf", + "gcc_axi_sf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + ; + + interrupt-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACT= IVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACT= IVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWA= YS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + interconnect-names =3D "cam_ahb", + "cam_hf_mnoc", + "cam_sf_mnoc", + "cam_sf_icp_mnoc"; + + iommus =3D <&apps_smmu 0x800 0x60>, + <&apps_smmu 0x860 0x60>, + <&apps_smmu 0x1800 0x60>, + <&apps_smmu 0x1860 0x60>, + <&apps_smmu 0x18e0 0x00>, + <&apps_smmu 0x1980 0x20>, + <&apps_smmu 0x1900 0x00>, + <&apps_smmu 0x19a0 0x20>; + + power-domains =3D <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + + power-domain-names =3D "ife0", + "ife1", + "top"; + + vdd-csiphy-0p8-supply =3D <&csiphy_0p8_supply>; + vdd-csiphy-1p2-supply =3D <&csiphy_1p2_supply>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + csiphy_ep0: endpoint { + clock-lanes =3D <7>; + data-lanes =3D <0 1>; + remote-endpoint =3D <&sensor_ep>; + }; + }; + }; + }; + }; --=20 2.45.2 From nobody Thu Feb 12 23:06:00 2026 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4921D15F41F for ; Thu, 2 Jan 2025 16:34:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735835660; cv=none; b=mBE/e6CDcpTIlxdE6x0E4AnXz0k6aEeH7BFCBnpQA5KAqxL7DeCCPXUTpFC6jTjtpeQDb5s+bM9g/X5zyMYEWZdFfRHVuz/Rn5VX8g2nQiVGUleXaMAmg4GZiJbHBFLsK3oIrq4auKGiBrU+C3fcz0DQuX0YKesKfqPlb02n7B0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735835660; c=relaxed/simple; bh=X+nwIbBfbLcCZT0e98AgVPsphz3+SNjG2j83drNBAAE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SjjC7KFzffVvhHEt3hKuiIieHP1Hw7XBD1gsARF+2BvDdkAWuGXqGKFTSuqllBGDTj23LGaMGlel7ITCElbIeXAw4QjZcghoVXGU5f45CSostzD5Mzn2kbBcLw7A7PBp7XQPhDhuIkEJGTwSlfp5JcSz1lPxgUFRM2aMky/OV/A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=zu+v2FSI; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="zu+v2FSI" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-43623f0c574so78644375e9.2 for ; Thu, 02 Jan 2025 08:34:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1735835654; x=1736440454; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=4jQuo0hv2fipuMWchCJhbaPZljnbATox/IIGJSDo8Gw=; b=zu+v2FSIBxXWhWF4fJ8b/9YYuT6w68iLvoQGe15bOUpj/PG8Htyoq8CmxG0WAJGL7x 3g/XokqMwmfuN7Yaf0KwOxxG8ldcgFPmdMB2n8qlcEkaBCvSWB3xwMThffRZRvgabWQB 0c4O1u99+vmiHOss8S/cJc3JgLqNpK6+pLhBZ47QmIZJP8cWEbK3zSM5ZVs8W7xJH+oQ 05P00dmRJzqIM7jwJ16RmDndK+E4Cb8PY/OqCHnAmc/aAc/OcY5E/sB7+8Lg0bKUEKnJ 7cmdyYYxn1sgNZu7+2lI5c2s2EqlO53YeA2iYCLZIS5Ro1+SzHUoaMa4V10VufmdmiWl UiEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735835654; x=1736440454; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4jQuo0hv2fipuMWchCJhbaPZljnbATox/IIGJSDo8Gw=; b=XWbJW+QfGhVu0OuuTrwHwho4tShd1cjRR7zqtl+3QjHQLYlcevE8yLj2xHfmkA03p7 yHqbeE0B51TTjx4aPWo3Em/70PK7ifjE8bbO8JgrHTx1eoYZy0hu+NxQWcOslNYUgqrY +JSuwOL1rmHDqqsgRbKpX40NBHEgK9S11UT0z1ITJXyNUOMFz5uRLyk+nUuIdMnb3YI6 UiT/WelyEuqfodTu9Mu4rjAIgGyqwuuqgGQyqdWie/JAzqd20NdtYbXayqpXcUqcNlVv 7NuvLH5sO6d1Tr6grqwVMbgp9rGzPT5BICHfU6jmetqLPqywAoirH09Rmuc2tE3MaY4t NOqQ== X-Forwarded-Encrypted: i=1; AJvYcCXw7zogpaHeup5enDuvHeNzGNMxmtUx2j8C5N72oz88ZUEJdNvvXJFPwhBlgTGoHoWxhBD+D1xCRCdFKNQ=@vger.kernel.org X-Gm-Message-State: AOJu0Yxj8TLbARUSd6oGUSLAXl4NZMhqy5ZtJ73HeTJIsAMpBKzOdQhc dpnI7LOb/JDMsgkvcsQgSuX6esXScJWy22dV5YA19f+sbMSP4av9rCPjMUhjVXU= X-Gm-Gg: ASbGncvZCi/CMJohflM0LoZLmPcaky1w+8w/bppodbdkSAjQJLIEH224db1EJ7QQMBn pGutqJUj14ZtRr8zk957scUXuwQjCLI+XzCjSrSJgozsrOvaCMFmGNP7A4Y0pLF1vHsCeZh0IWc DVMWs63mdChvu7tmqVNyQE3tACMf5WXxmOmJKamSIju+wnJRHm0oDsdRoTc+bclHp/Lu4PoXiEG kxw77yYGgODpPJ9M2Zm29OJ9ZmLRaBsYOy44jomOJVIcQUPp4TpJjw/dfe3lAlaYg== X-Google-Smtp-Source: AGHT+IFGXaGo93pdyDn4mqp8rOY1szIMFAh58hYibFmxhgmI41KP0IOCq/MZvuynZ1a9IB0ztK3dpQ== X-Received: by 2002:a05:600c:4ec9:b0:436:51bb:7a43 with SMTP id 5b1f17b1804b1-4366854852dmr391369655e9.5.1735835654422; Thu, 02 Jan 2025 08:34:14 -0800 (PST) Received: from [127.0.1.1] ([176.61.106.227]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43656b3b295sm499265665e9.33.2025.01.02.08.34.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jan 2025 08:34:14 -0800 (PST) From: Bryan O'Donoghue Date: Thu, 02 Jan 2025 16:32:09 +0000 Subject: [PATCH v3 4/6] arm64: dts: qcom: x1e80100: Add CAMCC block definition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-4-cb66d55d20cc@linaro.org> References: <20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-0-cb66d55d20cc@linaro.org> In-Reply-To: <20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-0-cb66d55d20cc@linaro.org> To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Mauro Carvalho Chehab , Bjorn Andersson , Michael Turquette , Stephen Boyd , Vladimir Zapolskiy , Jagadeesh Kona , Konrad Dybcio Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.15-dev-1b0d6 Add the CAMCC block for x1e80100. The x1e80100 CAMCC block is an iteration of previous CAMCC blocks with the exception of having two required power-domains not just one. Signed-off-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Reviewed-by: Vladimir Zapolskiy --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index c18b99765c25c901b3d0a3fbaddc320c0a8c1716..5c7b0c048d41a4ba3d74bbf7721= 6ad09b652ed30 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include @@ -4647,6 +4648,21 @@ usb_1_ss1_dwc3_ss: endpoint { }; }; =20 + camcc: clock-controller@ade0000 { + compatible =3D "qcom,x1e80100-camcc"; + reg =3D <0 0x0ade0000 0 0x20000>; + clocks =3D <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains =3D <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + mdss: display-subsystem@ae00000 { compatible =3D "qcom,x1e80100-mdss"; reg =3D <0 0x0ae00000 0 0x1000>; --=20 2.45.2 From nobody Thu Feb 12 23:06:00 2026 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA136155A2F for ; Thu, 2 Jan 2025 16:34:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735835663; cv=none; b=PLromrjdhZJFwnSaQWF2sk9BLoLd95LGQfiwd9pZ1Cqe0N8otb600jT+Q69tdtgXTQHp9o2GryJl5Zw9KhLyt3noLtIyWqvgUFYL7ErR8BUSGAIajIX0FIQoiqRtYouYyHrXcZH4iSzPl7ebbAfO0EYgTkL/eUK8/7jJ8YaXs90= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735835663; c=relaxed/simple; bh=fjvzO6KffOj9sfc5EIby2AXHfhoZiX0qQfPWKO/dzKc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OrLr4hYpSsHsTfCHmDIoHyMWd0S9Hgit5arLlSQJICh74H3OCu/IpvM2xVbDZe7FJo8Mul+y+gEJcfiz2ElCxbx6etec6QrbtTmvupZsKL3efgN+jS3hxjNNNffeHHw56wqrEQPVYIXdrO/dLE0eIt+cnQ00RROKCiUu/REXlck= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=hFshTgGR; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="hFshTgGR" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-436341f575fso119720625e9.1 for ; Thu, 02 Jan 2025 08:34:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1735835656; x=1736440456; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=DPzOhMrUaAX5ZkaDgmyUGAbRthcflOScBviLrrbA1DU=; b=hFshTgGRcRKITxUUmhtqBHds8gy5Ktmj7tQV494NcnBcolQgK4MqYCqg8ON5TyIILk Ths0a3lyDwAogG3y5xY4f/UcDHCle6fKaJVyA1Hf42jDxXfZTR4Ifjy/Xi5u+1f5FoRV ppCRWmSfmpfpwCuNItTaBT5H+J6+uUmwKz6X+uFhOtd/K7DlUDvwV0qvruRacpgP4Xcg E4AWAlDIzYWtJTc5DuOLpU+pEMKu6r1C/uq7/4t/a9TZRoFl6Z+LPKoxIBB2qjGw6NdP bZnUPF4nVxu0azaYZOlJV0EgXoFaR6Oq+vT4uqeuHpq+Ju7iKN8dkPtz/UupXV4vfThF XNow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735835656; x=1736440456; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DPzOhMrUaAX5ZkaDgmyUGAbRthcflOScBviLrrbA1DU=; b=NN6QBdGOV0+z3RUCwOiJaF/RuUNa4C3W2iRp4TJl924u+kCBT7b98lWSOpnjPfIhgh sXtIO1QfqON0envsoleL1HHumeoxtUNtmtQPcTZmlH8ybYh75tnEchw6/oHrsgeyrgt9 y6zk4h0TbC9tysKu5H2btt8rxClNg/1eqWauYaGtd0qCjNCvw7UnXqycOh/DQNPy6/lH K8/NGjVzVOzs4xZp5TwvEij1Mr2xmC6ZVxhmDPMVdZuxXHXCBUuBue68mCNGw0IkRqW3 LYVyNVzyi/1cjXgqXegJXCicH8uRWXzjPAiYrL+idOA1BNpAq3BtytuA2Ay/KbOyi3LV xxyg== X-Forwarded-Encrypted: i=1; AJvYcCVRw2/Du36wlKPM5I/MGvbWAPf/0PkzjLngfNtFyag2rCDP1vh9UUywK/tn456LVSzVlQWv8VZLo/z9jnc=@vger.kernel.org X-Gm-Message-State: AOJu0YzHkw0lFvGNpkabAAsdQWAKKkQa+6vRpabiTw5Z5LlizXBJlmNp 9vK/aS7bxKevyGz60AbxBQaReuBJEoRsPUtAsvHVtAePqLJrtKXIo+f6k/LABKk= X-Gm-Gg: ASbGncvvX2j6q0O5NIf/u5cXGC0+wmNYGSdadz1OD/uLym2YBgraocrq/6pXhQKyQW/ ZEm3eCBQ6mfu505wngB6mt92qD/uqPAimg5xIfEmKvHm7tRg47Y84XSjZ5tSHuUP/PHwnbsyQgi TfC4H1RYvfF3VdPag2K/b95XmgPy0x5pfzhtLbPhpraVecr0R0VH2qQ/CeRNWmP18UARsB/+5li FpG+Lbs92q7H1P3pfU+Y13SK51X2Nbtb7LKfr7TXHQlvnuOdNUB/r/ZZmw2rds6iw== X-Google-Smtp-Source: AGHT+IHzGfi8JqgrtJkJCqsaRzgZmxPWRir2HsTiv6pOD1D/PSO5j8J0EGMa87PX9JhMa12ajsfr7w== X-Received: by 2002:a05:600c:4586:b0:431:5c3d:1700 with SMTP id 5b1f17b1804b1-43668a3a3c4mr357327115e9.21.1735835655821; Thu, 02 Jan 2025 08:34:15 -0800 (PST) Received: from [127.0.1.1] ([176.61.106.227]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43656b3b295sm499265665e9.33.2025.01.02.08.34.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jan 2025 08:34:15 -0800 (PST) From: Bryan O'Donoghue Date: Thu, 02 Jan 2025 16:32:10 +0000 Subject: [PATCH v3 5/6] arm64: dts: qcom: x1e80100: Add CCI definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-5-cb66d55d20cc@linaro.org> References: <20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-0-cb66d55d20cc@linaro.org> In-Reply-To: <20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-0-cb66d55d20cc@linaro.org> To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Mauro Carvalho Chehab , Bjorn Andersson , Michael Turquette , Stephen Boyd , Vladimir Zapolskiy , Jagadeesh Kona , Konrad Dybcio Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Konrad Dybcio X-Mailer: b4 0.15-dev-1b0d6 Add in 2 CCI busses. One bus has two CCI bus master pinouts: cci_i2c_scl0 =3D gpio101 cci_i2c_sda0 =3D gpio102 cci_i2c_scl1 =3D gpio103 cci_i2c_sda1 =3D gpio104 A second bus has a single CCI bus master pinout: cci_i2c_scl2 =3D gpio105 cci_i2c_sda2 =3D gpio106 Reviewed-by: Konrad Dybcio Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 150 +++++++++++++++++++++++++++++= ++++ 1 file changed, 150 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index 5c7b0c048d41a4ba3d74bbf77216ad09b652ed30..97ebf5596dfc3caa920ef85722c= a8afd49cd3c24 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -4648,6 +4648,84 @@ usb_1_ss1_dwc3_ss: endpoint { }; }; =20 + cci0: cci@ac15000 { + compatible =3D "qcom,x1e80100-cci", "qcom,msm8996-cci"; + reg =3D <0 0x0ac15000 0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "cci"; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 =3D <&cci0_default>; + pinctrl-1 =3D <&cci0_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci1: cci@ac16000 { + compatible =3D "qcom,x1e80100-cci", "qcom,msm8996-cci"; + reg =3D <0 0x0ac16000 0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "cci"; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 =3D <&cci1_default>; + pinctrl-1 =3D <&cci1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + camcc: clock-controller@ade0000 { compatible =3D "qcom,x1e80100-camcc"; reg =3D <0 0x0ade0000 0 0x20000>; @@ -5271,6 +5349,78 @@ tlmm: pinctrl@f100000 { gpio-ranges =3D <&tlmm 0 0 239>; wakeup-parent =3D <&pdc>; =20 + cci0_default: cci0-default-state { + cci0_i2c0_default: cci0-i2c0-default-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins =3D "gpio101", "gpio102"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + + cci0_i2c1_default: cci0-i2c1-default-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins =3D "gpio103", "gpio104"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci0_sleep: cci0-sleep-state { + cci0_i2c0_sleep: cci0-i2c0-sleep-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins =3D "gpio101", "gpio102"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci0_i2c1_sleep: cci0-i2c1-sleep-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins =3D "gpio103", "gpio104"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci1_default: cci1-default-state { + cci1_i2c0_default: cci1-i2c0-default-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins =3D "gpio105","gpio106"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + + cci1_i2c1_default: cci1-i2c1-default-pins { + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */ + pins =3D "gpio235","gpio236"; + function =3D "aon_cci"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci1_sleep: cci1-sleep-state { + cci1_i2c0_sleep: cci1-i2c0-sleep-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins =3D "gpio105","gpio106"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci1_i2c1_sleep: cci1-i2c1-sleep-pins { + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */ + pins =3D "gpio235","gpio236"; + function =3D "aon_cci"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { /* SDA, SCL */ pins =3D "gpio0", "gpio1"; --=20 2.45.2 From nobody Thu Feb 12 23:06:00 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31EBE152166 for ; Thu, 2 Jan 2025 16:34:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735835665; cv=none; b=EGMfsoVbUqR/NY3xsZD07XDtvoXdvB01bpwqfC06ojxwK9Mb3tQZPtKilxauzjaalhZZZXZuf6SY9Ts8OhwmbBQ5z0rPDW9Fr05uuzTaZnnOuwTxHBEJJfaduvbxCaprAOr1bnSQRoW0AErLs3jTX7fwUO/Hy++kbf4uC34bjYg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735835665; c=relaxed/simple; bh=oNnL8hVQpNoqjucv+4l3yobMYSHjMBJfbEGmFgRGX5E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YWc2yQwObkK1C3AVtq5M3zvPpMBQ3bkF+Fx3KZwXwO78606IE5MNXfYoMuibLUVIERF0khCQlnP3LvbrfnZeQB5dE/wYnuEqX4HOpZS0Cinxjlm34NE6d5HIRBk5rVwfCqWooh00ozJZdMT3tqfKwu2IbI1YjnETduk06dhdI5s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=x85AF694; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="x85AF694" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-4364a37a1d7so121737065e9.3 for ; Thu, 02 Jan 2025 08:34:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1735835657; x=1736440457; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=0b62UCuETWUYjOP9XcQNgSvVluIC9YjgjH3XPmV4qGo=; b=x85AF694XH6KdAyeNKcE7EIlp9dK8dvKXSpb1zFY6EWcWDxI6OSd8wx9sFmAOfHyWn lwIcd53VyhpuO4nJuvyEmAtM3lF7POC0OM6Y6Hb7ecdopO3tA013QykrWHmEh3BwiaGq YeAOxQED0UhoMlIlAip5Mv5CEafX7Y/wRvKrRzXY9TrDWIU8sy6YcQYOnbcq5sngAvZ0 M3/71ikUiM4TIHXI00TsoV+F9sAWT/MIbaFNiTOodGbX206Hx/gt087FVzmYtpRFx3PR I2hLPUbiXHdX/x7OnBxChTqrSe6twbeGyTKOiVHV1puKA6CxCCzgtRVbHRGdi6jJsLDB A5tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735835657; x=1736440457; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0b62UCuETWUYjOP9XcQNgSvVluIC9YjgjH3XPmV4qGo=; b=WGY74nT7ho5zMHT5LxjOstnAxS0edaPTqVfoJOWXu2Set5oge6Wo/hy2seT6K5LKut 9NMMKeQcpQnXO6aUtRGxQjc4ioCfEbT5bEFG9Yx6VlFa4nXGREf5zkecVTJWg83oK5hI Rv8SqTcwNzn60qdP3LfnPU4RXLjg4VG5474rGz1TfrlX0yd4PsCNw48x73Agk+HfBbWB 3YMg1kTVAes8SOgh8+BnNfXdTwK/ovxq7HexF60Zhoft9ZBNYst36gptrs7pF8cAqEn3 yWaeqdZR4CIxUw7bW+m9Tc6sBfN7GlYE4Vhsjbi/TDQwQbhxuDcb82nY7rZxoUhztTXJ V3tw== X-Forwarded-Encrypted: i=1; AJvYcCW57bPH9N5PcmYS3uISDKDXkXbMVytrGXRQhYBNO6geOnmL1ORaGKPil9Ge15miW5U8fkLZM2IUcszkEMY=@vger.kernel.org X-Gm-Message-State: AOJu0Yx00BxPPKs3+3RjSnvOEqqU6rmsa9En2OksFshlK1sDHmvRTT8f AwSlqR0F6sXEbr0RM/EEQtdmykdhBPVXk/Rx1YilwaS14w8dXADANH3xkTgKGgk= X-Gm-Gg: ASbGnct8gcM0fL29lNiyYCOLp3kT4b23Du+ZaRrTvObpTJ8zTWxCjz2Rtls37mf3uC7 BwhN2umhmUAl9ogcVk4XTZ5NviaEFJyKx3oKoOvcPpiQ1v/s2Q0fZCQKFV2hRS2/m9ro7E2BBVJ h+c2zojDberfisgQGrzbf1txXZ7O5WHfPZ9/ZvKcqP9r+TWkS5TstBC+zvdCncuItH40tbbcodE vWaJ8EKzotknyTQ1kDut73kklF/uu3Nbdo08a/WnF8LUkEy0Sl6p/jpPtXMKdYtHw== X-Google-Smtp-Source: AGHT+IGrzTHhkEtGfmbQVMqc/B8UI4MzATc+HmmDKeaJPsd+R/bMiGGQ422VpCY8gq/IyysaVRdEzQ== X-Received: by 2002:a05:600c:35c1:b0:434:a94f:f8a9 with SMTP id 5b1f17b1804b1-43668b7873emr312282565e9.28.1735835657195; Thu, 02 Jan 2025 08:34:17 -0800 (PST) Received: from [127.0.1.1] ([176.61.106.227]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43656b3b295sm499265665e9.33.2025.01.02.08.34.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jan 2025 08:34:16 -0800 (PST) From: Bryan O'Donoghue Date: Thu, 02 Jan 2025 16:32:11 +0000 Subject: [PATCH v3 6/6] arm64: dts: qcom: x1e80100: Add CAMSS block definition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-6-cb66d55d20cc@linaro.org> References: <20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-0-cb66d55d20cc@linaro.org> In-Reply-To: <20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-0-cb66d55d20cc@linaro.org> To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Mauro Carvalho Chehab , Bjorn Andersson , Michael Turquette , Stephen Boyd , Vladimir Zapolskiy , Jagadeesh Kona , Konrad Dybcio Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Konrad Dybcio X-Mailer: b4 0.15-dev-1b0d6 Add dtsi to describe the xe180100 CAMSS block 4 x CSIPHY 2 x CSID 2 x CSID Lite 2 x IFE 2 x IFE Lite Reviewed-by: Konrad Dybcio Signed-off-by: Bryan O'Donoghue Reviewed-by: Vladimir Zapolskiy --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 185 +++++++++++++++++++++++++++++= ++++ 1 file changed, 185 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index 97ebf5596dfc3caa920ef85722ca8afd49cd3c24..0b5b48d2c59e0b18816ea131e0f= 687b8bf84e1da 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -4726,6 +4726,191 @@ cci1_i2c1: i2c-bus@1 { }; }; =20 + camss: isp@acb6000 { + compatible =3D "qcom,x1e80100-camss"; + + reg =3D <0 0x0acb6000 0 0x1000>, + <0 0x0acb7000 0 0x2000>, + <0 0x0acb9000 0 0x2000>, + <0 0x0acbb000 0 0x2000>, + <0 0x0acc6000 0 0x1000>, + <0 0x0acca000 0 0x1000>, + <0 0x0ace4000 0 0x2000>, + <0 0x0ace6000 0 0x2000>, + <0 0x0ace8000 0 0x2000>, + <0 0x0acec000 0 0x2000>, + <0 0x0acf6000 0 0x1000>, + <0 0x0acf7000 0 0x1000>, + <0 0x0acf8000 0 0x1000>, + <0 0x0acc7000 0 0x2000>, + <0 0x0accb000 0 0x2000>, + <0 0x0ac62000 0 0x4000>, + <0 0x0ac71000 0 0x4000>; + reg-names =3D "csid_wrapper", + "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4", + "csitpg0", + "csitpg1", + "csitpg2", + "vfe_lite0", + "vfe_lite1", + "vfe0", + "vfe1"; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names =3D "camnoc_rt_axi", + "camnoc_nrt_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe_lite", + "cphy_rx_clk_src", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy4", + "csiphy4_timer", + "gcc_axi_hf", + "gcc_axi_sf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "cam_ahb", + "cam_hf_mnoc", + "cam_sf_mnoc", + "cam_sf_icp_mnoc"; + + iommus =3D <&apps_smmu 0x800 0x60>, + <&apps_smmu 0x860 0x60>, + <&apps_smmu 0x1800 0x60>, + <&apps_smmu 0x1860 0x60>, + <&apps_smmu 0x18e0 0x00>, + <&apps_smmu 0x1900 0x00>, + <&apps_smmu 0x1980 0x20>, + <&apps_smmu 0x19a0 0x20>; + + power-domains =3D <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names =3D "ife0", + "ife1", + "top"; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + port@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + port@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + port@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + }; + camcc: clock-controller@ade0000 { compatible =3D "qcom,x1e80100-camcc"; reg =3D <0 0x0ade0000 0 0x20000>; --=20 2.45.2