From nobody Sun May 10 06:27:03 2026 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFE9A1B2EFB for ; Mon, 30 Dec 2024 18:06:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735581968; cv=none; b=Cv4vL++53Cg54zb3DS1PSwSsUkMbadO6yMCbOm4UFNKnrFYMfgSDpg299RfguRm1EC9Z1/38zTVDgPqWCKhwtWhVhHMNKPgoqnWpgQ9CappYnSI6Tk+aAMvFG6OuXx2qsKlg0nOODNJxmJ1bE20N3VyPwT8OZDtPzmPcIalyk+g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735581968; c=relaxed/simple; bh=LDcdgOQyY9dwd7dBfRQonNijKD4k7Be4KCxAufSkWW0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nJOXBtYyhJMCAvScra5XQf/OcDbZnnRbNey/RRTygL13UEiGytUG34Zws8FSYG5jS5t5WN4BlqQ41W8RhImL6n1z9jNV01jCLLZ65WlNd4FgmpfhDbAZJPjrYwZ8wkNdlM2l+XG6kWGvHQPq6ZhY2g2U9LWZelOFv0M5AQ6ZWrM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=shelob.surriel.com; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tSJzc-000000008Lf-2Fys; Mon, 30 Dec 2024 12:55:52 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, nadav.amit@gmail.com, zhengqi.arch@bytedance.com, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 01/12] x86/mm: make MMU_GATHER_RCU_TABLE_FREE unconditional Date: Mon, 30 Dec 2024 12:53:02 -0500 Message-ID: <20241230175550.4046587-2-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241230175550.4046587-1-riel@surriel.com> References: <20241230175550.4046587-1-riel@surriel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: riel@surriel.com Content-Type: text/plain; charset="utf-8" Currently x86 uses CONFIG_MMU_GATHER_TABLE_FREE when using paravirt, and not when running on bare metal. There is no real good reason to do things differently for each setup. Make them all the same. After this change, the synchronization between get_user_pages_fast and page table freeing is handled by RCU, which prevents page tables from being reused for other data while get_user_pages_fast is walking them. This allows us to invalidate page tables while other CPUs have interrupts disabled. Signed-off-by: Rik van Riel Suggested-by: Peter Zijlstra --- arch/x86/Kconfig | 2 +- arch/x86/kernel/paravirt.c | 7 +------ 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 9d7bd0ae48c4..e8743f8c9fd0 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -274,7 +274,7 @@ config X86 select HAVE_PCI select HAVE_PERF_REGS select HAVE_PERF_USER_STACK_DUMP - select MMU_GATHER_RCU_TABLE_FREE if PARAVIRT + select MMU_GATHER_RCU_TABLE_FREE select MMU_GATHER_MERGE_VMAS select HAVE_POSIX_CPU_TIMERS_TASK_WORK select HAVE_REGS_AND_STACK_ACCESS_API diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index fec381533555..2b78a6b466ed 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -59,11 +59,6 @@ void __init native_pv_lock_init(void) static_branch_enable(&virt_spin_lock_key); } =20 -static void native_tlb_remove_table(struct mmu_gather *tlb, void *table) -{ - tlb_remove_page(tlb, table); -} - struct static_key paravirt_steal_enabled; struct static_key paravirt_steal_rq_enabled; =20 @@ -191,7 +186,7 @@ struct paravirt_patch_template pv_ops =3D { .mmu.flush_tlb_kernel =3D native_flush_tlb_global, .mmu.flush_tlb_one_user =3D native_flush_tlb_one_user, .mmu.flush_tlb_multi =3D native_flush_tlb_multi, - .mmu.tlb_remove_table =3D native_tlb_remove_table, + .mmu.tlb_remove_table =3D tlb_remove_table, =20 .mmu.exit_mmap =3D paravirt_nop, .mmu.notify_page_enc_status_changed =3D paravirt_nop, --=20 2.47.1 From nobody Sun May 10 06:27:03 2026 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7C1A1B2EFB for ; Mon, 30 Dec 2024 18:06:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735581974; cv=none; b=aeTplltC6bYOW3j+EPCQdwxCJwzsui+0gvIVpUofyI01r3B2Qtu10gKbJTZ60EWzWHg/PR8bF1jRvH5NYaD3MZGEHc1NZ9AV4iI78sMuqb5YM4RLWyBjE+JF2PpVCIRBYnNpZ+PBGwvLF52RqzvqO1S5TpVl/A/W2KHZxHKJjGc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735581974; c=relaxed/simple; bh=ltYDdx6jkK4RDnCyqRr70KPzlYZpXcMH3q9xf7d0zPo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QDK6yKT1qMo6+rYNKJXKUC846LNv4mEbMAxUeE+5G/RZ40iinzvBAlBUOfDBlvsnChon1mlH/oD71CWQ1ygPlpnR1jI4b18lvL+5RF6THJfSFNuCxE61EcPtLC+RFSTDrXZut3nBEdpxCITHabyZ7xSpk6sxLEWxaPLtyEVRNok= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=shelob.surriel.com; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tSJzc-000000008Lf-37RI; Mon, 30 Dec 2024 12:55:52 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, nadav.amit@gmail.com, zhengqi.arch@bytedance.com, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 02/12] x86/mm: remove pv_ops.mmu.tlb_remove_table call Date: Mon, 30 Dec 2024 12:53:03 -0500 Message-ID: <20241230175550.4046587-3-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241230175550.4046587-1-riel@surriel.com> References: <20241230175550.4046587-1-riel@surriel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: riel@surriel.com Content-Type: text/plain; charset="utf-8" Every pv_ops.mmu.tlb_remove_table call ends up calling tlb_remove_table. Get rid of the indirection by simply calling tlb_remove_table directly, and not going through the paravirt function pointers. Signed-off-by: Rik van Riel Suggested-by: Qi Zheng --- arch/x86/hyperv/mmu.c | 1 - arch/x86/include/asm/paravirt.h | 5 ----- arch/x86/include/asm/paravirt_types.h | 2 -- arch/x86/kernel/kvm.c | 1 - arch/x86/kernel/paravirt.c | 1 - arch/x86/mm/pgtable.c | 16 ++++------------ arch/x86/xen/mmu_pv.c | 1 - 7 files changed, 4 insertions(+), 23 deletions(-) diff --git a/arch/x86/hyperv/mmu.c b/arch/x86/hyperv/mmu.c index 1cc113200ff5..cbe6c71e17c1 100644 --- a/arch/x86/hyperv/mmu.c +++ b/arch/x86/hyperv/mmu.c @@ -240,5 +240,4 @@ void hyperv_setup_mmu_ops(void) =20 pr_info("Using hypercall for remote TLB flush\n"); pv_ops.mmu.flush_tlb_multi =3D hyperv_flush_tlb_multi; - pv_ops.mmu.tlb_remove_table =3D tlb_remove_table; } diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravir= t.h index d4eb9e1d61b8..794ba3647c6c 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -91,11 +91,6 @@ static inline void __flush_tlb_multi(const struct cpumas= k *cpumask, PVOP_VCALL2(mmu.flush_tlb_multi, cpumask, info); } =20 -static inline void paravirt_tlb_remove_table(struct mmu_gather *tlb, void = *table) -{ - PVOP_VCALL2(mmu.tlb_remove_table, tlb, table); -} - static inline void paravirt_arch_exit_mmap(struct mm_struct *mm) { PVOP_VCALL1(mmu.exit_mmap, mm); diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/p= aravirt_types.h index 8d4fbe1be489..13405959e4db 100644 --- a/arch/x86/include/asm/paravirt_types.h +++ b/arch/x86/include/asm/paravirt_types.h @@ -136,8 +136,6 @@ struct pv_mmu_ops { void (*flush_tlb_multi)(const struct cpumask *cpus, const struct flush_tlb_info *info); =20 - void (*tlb_remove_table)(struct mmu_gather *tlb, void *table); - /* Hook for intercepting the destruction of an mm_struct. */ void (*exit_mmap)(struct mm_struct *mm); void (*notify_page_enc_status_changed)(unsigned long pfn, int npages, boo= l enc); diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c index 7a422a6c5983..3be9b3342c67 100644 --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -838,7 +838,6 @@ static void __init kvm_guest_init(void) #ifdef CONFIG_SMP if (pv_tlb_flush_supported()) { pv_ops.mmu.flush_tlb_multi =3D kvm_flush_tlb_multi; - pv_ops.mmu.tlb_remove_table =3D tlb_remove_table; pr_info("KVM setup pv remote TLB flush\n"); } =20 diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 2b78a6b466ed..c019771e0123 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -186,7 +186,6 @@ struct paravirt_patch_template pv_ops =3D { .mmu.flush_tlb_kernel =3D native_flush_tlb_global, .mmu.flush_tlb_one_user =3D native_flush_tlb_one_user, .mmu.flush_tlb_multi =3D native_flush_tlb_multi, - .mmu.tlb_remove_table =3D tlb_remove_table, =20 .mmu.exit_mmap =3D paravirt_nop, .mmu.notify_page_enc_status_changed =3D paravirt_nop, diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c index 5745a354a241..3dc4af1f7868 100644 --- a/arch/x86/mm/pgtable.c +++ b/arch/x86/mm/pgtable.c @@ -18,14 +18,6 @@ EXPORT_SYMBOL(physical_mask); #define PGTABLE_HIGHMEM 0 #endif =20 -#ifndef CONFIG_PARAVIRT -static inline -void paravirt_tlb_remove_table(struct mmu_gather *tlb, void *table) -{ - tlb_remove_page(tlb, table); -} -#endif - gfp_t __userpte_alloc_gfp =3D GFP_PGTABLE_USER | PGTABLE_HIGHMEM; =20 pgtable_t pte_alloc_one(struct mm_struct *mm) @@ -54,7 +46,7 @@ void ___pte_free_tlb(struct mmu_gather *tlb, struct page = *pte) { pagetable_pte_dtor(page_ptdesc(pte)); paravirt_release_pte(page_to_pfn(pte)); - paravirt_tlb_remove_table(tlb, pte); + tlb_remove_table(tlb, pte); } =20 #if CONFIG_PGTABLE_LEVELS > 2 @@ -70,7 +62,7 @@ void ___pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd) tlb->need_flush_all =3D 1; #endif pagetable_pmd_dtor(ptdesc); - paravirt_tlb_remove_table(tlb, ptdesc_page(ptdesc)); + tlb_remove_table(tlb, ptdesc_page(ptdesc)); } =20 #if CONFIG_PGTABLE_LEVELS > 3 @@ -80,14 +72,14 @@ void ___pud_free_tlb(struct mmu_gather *tlb, pud_t *pud) =20 pagetable_pud_dtor(ptdesc); paravirt_release_pud(__pa(pud) >> PAGE_SHIFT); - paravirt_tlb_remove_table(tlb, virt_to_page(pud)); + tlb_remove_table(tlb, virt_to_page(pud)); } =20 #if CONFIG_PGTABLE_LEVELS > 4 void ___p4d_free_tlb(struct mmu_gather *tlb, p4d_t *p4d) { paravirt_release_p4d(__pa(p4d) >> PAGE_SHIFT); - paravirt_tlb_remove_table(tlb, virt_to_page(p4d)); + tlb_remove_table(tlb, virt_to_page(p4d)); } #endif /* CONFIG_PGTABLE_LEVELS > 4 */ #endif /* CONFIG_PGTABLE_LEVELS > 3 */ diff --git a/arch/x86/xen/mmu_pv.c b/arch/x86/xen/mmu_pv.c index 55a4996d0c04..041e17282af0 100644 --- a/arch/x86/xen/mmu_pv.c +++ b/arch/x86/xen/mmu_pv.c @@ -2137,7 +2137,6 @@ static const typeof(pv_ops) xen_mmu_ops __initconst = =3D { .flush_tlb_kernel =3D xen_flush_tlb, .flush_tlb_one_user =3D xen_flush_tlb_one_user, .flush_tlb_multi =3D xen_flush_tlb_multi, - .tlb_remove_table =3D tlb_remove_table, =20 .pgd_alloc =3D xen_pgd_alloc, .pgd_free =3D xen_pgd_free, --=20 2.47.1 From nobody Sun May 10 06:27:03 2026 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B0301B3946 for ; Mon, 30 Dec 2024 18:06:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tSJzc-000000008Lf-41s8; Mon, 30 Dec 2024 12:55:52 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, nadav.amit@gmail.com, zhengqi.arch@bytedance.com, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 03/12] x86/mm: add X86_FEATURE_INVLPGB definition. Date: Mon, 30 Dec 2024 12:53:04 -0500 Message-ID: <20241230175550.4046587-4-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241230175550.4046587-1-riel@surriel.com> References: <20241230175550.4046587-1-riel@surriel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: riel@surriel.com Content-Type: text/plain; charset="utf-8" Add the INVPLGB CPUID definition, allowing the kernel to recognize whether the CPU supports the INVLPGB instruction. Signed-off-by: Rik van Riel --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 17b6590748c0..b7209d6c3a5f 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -338,6 +338,7 @@ #define X86_FEATURE_CLZERO (13*32+ 0) /* "clzero" CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* "irperf" Instructions Retired Co= unt */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* "xsaveerptr" Always save/res= tore FP error pointers */ +#define X86_FEATURE_INVLPGB (13*32+ 3) /* "invlpgb" INVLPGB instruction */ #define X86_FEATURE_RDPRU (13*32+ 4) /* "rdpru" Read processor register a= t user level */ #define X86_FEATURE_WBNOINVD (13*32+ 9) /* "wbnoinvd" WBNOINVD instructio= n */ #define X86_FEATURE_AMD_IBPB (13*32+12) /* Indirect Branch Prediction Bar= rier */ --=20 2.47.1 From nobody Sun May 10 06:27:03 2026 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78A7584FAD for ; Mon, 30 Dec 2024 18:05:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735581944; cv=none; b=qcp2CRIVKZ0S6O3Z8I9RYi2BoJIG7hrwJKywOg+UwNG1ZtD+ZjE12UrP4uGmsjHH8up3avn4kxOfvEryqv2aQYOJgLtzYYHWIiT1W1VMNIzIMl5gt4VbzlPDdvulWY7A7FstULHfS/GNP6pyDR9NbOhGT13i9T7nrdkSzqhYUFE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735581944; c=relaxed/simple; bh=JcUJpjUjKvOPZnatAuhHXyFRxyGK2hiNApeectzzoWU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sJzXFcctFUoMDHlQKwCcck7SPbTRSyZf5zD2uosaapl1QolAntqwPstAqEC4LkYbyTqJXWJGsFqKoN+ggExSXMdd8w1u/MM9DGHA7Gbzart2rPQfOWRxGOtPMyZABMpCCMZWHuYpZr/OZlCG8IRoA/fF2/NjdKR12DZPhMBLNWI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=shelob.surriel.com; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tSJzd-000000008Lf-0g30; Mon, 30 Dec 2024 12:55:53 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, nadav.amit@gmail.com, zhengqi.arch@bytedance.com, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 04/12] x86/mm: get INVLPGB count max from CPUID Date: Mon, 30 Dec 2024 12:53:05 -0500 Message-ID: <20241230175550.4046587-5-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241230175550.4046587-1-riel@surriel.com> References: <20241230175550.4046587-1-riel@surriel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: riel@surriel.com Content-Type: text/plain; charset="utf-8" The CPU advertises the maximum number of pages that can be shot down with one INVLPGB instruction in the CPUID data. Save that information for later use. Signed-off-by: Rik van Riel --- arch/x86/include/asm/tlbflush.h | 1 + arch/x86/kernel/cpu/amd.c | 8 ++++++++ arch/x86/kernel/setup.c | 4 ++++ 3 files changed, 13 insertions(+) diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflus= h.h index 02fc2aa06e9e..7d1468a3967b 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -182,6 +182,7 @@ static inline void cr4_init_shadow(void) =20 extern unsigned long mmu_cr4_features; extern u32 *trampoline_cr4_features; +extern u16 invlpgb_count_max; =20 extern void initialize_tlbstate_and_flush(void); =20 diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 79d2e17f6582..226b8fc64bfc 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1135,6 +1135,14 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) tlb_lli_2m[ENTRIES] =3D eax & mask; =20 tlb_lli_4m[ENTRIES] =3D tlb_lli_2m[ENTRIES] >> 1; + + if (c->extended_cpuid_level < 0x80000008) + return; + + cpuid(0x80000008, &eax, &ebx, &ecx, &edx); + + /* Max number of pages INVLPGB can invalidate in one shot */ + invlpgb_count_max =3D (edx & 0xffff) + 1; } =20 static const struct cpu_dev amd_cpu_dev =3D { diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index f1fea506e20f..6c4d08f8f7b1 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -138,6 +138,10 @@ __visible unsigned long mmu_cr4_features __ro_after_in= it; __visible unsigned long mmu_cr4_features __ro_after_init =3D X86_CR4_PAE; #endif =20 +#ifdef CONFIG_CPU_SUP_AMD +u16 invlpgb_count_max __ro_after_init; +#endif + #ifdef CONFIG_IMA static phys_addr_t ima_kexec_buffer_phys; static size_t ima_kexec_buffer_size; --=20 2.47.1 From nobody Sun May 10 06:27:03 2026 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D9471B0410 for ; Mon, 30 Dec 2024 18:06:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735581986; cv=none; b=TKQUYbxpxQNiCIdnt3oNHDGfOORLLA8uwpF+oPDa0K7AqZqy6C338g4idzRLllEbelNBh2UmzBP+JgYpYshqoi+2Inics5LJ8Q1d02/jW9xCyxrxnxvuRLmay8se6QJxSHwhMfm3kJRi17+WPAeKHHkmantr2Lz/57ujq2a271s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735581986; c=relaxed/simple; bh=BKRe6dtVSgt5+YzVA3WqKrrgv4sMToY9ovJrornn6YI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=O6wUS0iOuqiUXQ+xKlOTU2SZvo9LTf3xuWqLToj3myL6/lLpUtS+AhaUf1Aiz8n8nvNx+lptnk4hK0kiSA2+0tCv7UrqddwyJWgGgYQZ7RJNLeVNlN53yjOuEpNRvAauVqWa9KsPE88rMdiNjbYvzh1Z3IYGIaP1Dc4/02GO+AI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=shelob.surriel.com; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tSJzd-000000008Lf-2LNx; Mon, 30 Dec 2024 12:55:53 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, nadav.amit@gmail.com, zhengqi.arch@bytedance.com, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 05/12] x86/mm: add INVLPGB support code Date: Mon, 30 Dec 2024 12:53:06 -0500 Message-ID: <20241230175550.4046587-6-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241230175550.4046587-1-riel@surriel.com> References: <20241230175550.4046587-1-riel@surriel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: riel@surriel.com Content-Type: text/plain; charset="utf-8" Add invlpgb.h with the helper functions and definitions needed to use broadcast TLB invalidation on AMD EPYC 3 and newer CPUs. Signed-off-by: Rik van Riel --- arch/x86/include/asm/invlpgb.h | 93 +++++++++++++++++++++++++++++++++ arch/x86/include/asm/tlbflush.h | 1 + 2 files changed, 94 insertions(+) create mode 100644 arch/x86/include/asm/invlpgb.h diff --git a/arch/x86/include/asm/invlpgb.h b/arch/x86/include/asm/invlpgb.h new file mode 100644 index 000000000000..862775897a54 --- /dev/null +++ b/arch/x86/include/asm/invlpgb.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_INVLPGB +#define _ASM_X86_INVLPGB + +#include + +/* + * INVLPGB does broadcast TLB invalidation across all the CPUs in the syst= em. + * + * The INVLPGB instruction is weakly ordered, and a batch of invalidations= can + * be done in a parallel fashion. + * + * TLBSYNC is used to ensure that pending INVLPGB invalidations initiated = from + * this CPU have completed. + */ +static inline void __invlpgb(unsigned long asid, unsigned long pcid, unsig= ned long addr, + int extra_count, bool pmd_stride, unsigned long flags) +{ + u64 rax =3D addr | flags; + u32 ecx =3D (pmd_stride << 31) | extra_count; + u32 edx =3D (pcid << 16) | asid; + + asm volatile("invlpgb" : : "a" (rax), "c" (ecx), "d" (edx)); +} + +/* + * INVLPGB can be targeted by virtual address, PCID, ASID, or any combinat= ion + * of the three. For example: + * - INVLPGB_VA | INVLPGB_INCLUDE_GLOBAL: invalidate all TLB entries at th= e address + * - INVLPGB_PCID: invalidate all TLB entries matching the= PCID + * + * The first can be used to invalidate (kernel) mappings at a particular + * address across all processes. + * + * The latter invalidates all TLB entries matching a PCID. + */ +#define INVLPGB_VA BIT(0) +#define INVLPGB_PCID BIT(1) +#define INVLPGB_ASID BIT(2) +#define INVLPGB_INCLUDE_GLOBAL BIT(3) +#define INVLPGB_FINAL_ONLY BIT(4) +#define INVLPGB_INCLUDE_NESTED BIT(5) + +/* Flush all mappings for a given pcid and addr, not including globals. */ +static inline void invlpgb_flush_user(unsigned long pcid, + unsigned long addr) +{ + __invlpgb(0, pcid, addr, 0, 0, INVLPGB_PCID | INVLPGB_VA); +} + +static inline void invlpgb_flush_user_nr(unsigned long pcid, unsigned long= addr, + int nr, bool pmd_stride) +{ + __invlpgb(0, pcid, addr, nr - 1, pmd_stride, INVLPGB_PCID | INVLPGB_VA); +} + +/* Flush all mappings for a given ASID, not including globals. */ +static inline void invlpgb_flush_single_asid(unsigned long asid) +{ + __invlpgb(asid, 0, 0, 0, 0, INVLPGB_ASID); +} + +/* Flush all mappings for a given PCID, not including globals. */ +static inline void invlpgb_flush_single_pcid(unsigned long pcid) +{ + __invlpgb(0, pcid, 0, 0, 0, INVLPGB_PCID); +} + +/* Flush all mappings, including globals, for all PCIDs. */ +static inline void invlpgb_flush_all(void) +{ + __invlpgb(0, 0, 0, 0, 0, INVLPGB_INCLUDE_GLOBAL); +} + +/* Flush addr, including globals, for all PCIDs. */ +static inline void invlpgb_flush_addr(unsigned long addr, int nr) +{ + __invlpgb(0, 0, addr, nr - 1, 0, INVLPGB_INCLUDE_GLOBAL); +} + +/* Flush all mappings for all PCIDs except globals. */ +static inline void invlpgb_flush_all_nonglobals(void) +{ + __invlpgb(0, 0, 0, 0, 0, 0); +} + +/* Wait for INVLPGB originated by this CPU to complete. */ +static inline void tlbsync(void) +{ + asm volatile("tlbsync"); +} + +#endif /* _ASM_X86_INVLPGB */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflus= h.h index 7d1468a3967b..20074f17fbcd 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include --=20 2.47.1 From nobody Sun May 10 06:27:03 2026 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06FC41B0427 for ; Mon, 30 Dec 2024 18:05:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735581941; cv=none; b=GA0ZtqoY/eHIq1jLwwK1wlMQL3ZNQ7pJmlIckhXBsHPu2e4vicfp98SiYaqWWbewDOUJl1SfDHgxER44NOU0AWc1BIf9IMB+umq2HCv349vcyGd2sXXyeddgef6WT/lZpG3e4Xnx2qIbpX9iFlIZBeLcecgEUDeyPcT7Qofh740= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735581941; c=relaxed/simple; bh=UTUbLNhwSKotjeAqet+8hPX3oQbWrFlGGAfDGYkfJ3k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RCCva6GW6vUKaCHlpi8Whv4JGFOsEF/PCL+KWoETdZB515N36Ks9lgHMO1ern5BfuQ4VnNWhwFIUZALnXp6CdofBXtoGvlAw87/NjUnhGVDqzI2q2NeECEQlt7+QVtqslRiAceR1cp1gU8MygIzSzWMB9X0yg+Xymxgm7Q1RPOU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=shelob.surriel.com; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tSJzd-000000008Lf-3fUp; Mon, 30 Dec 2024 12:55:53 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, nadav.amit@gmail.com, zhengqi.arch@bytedance.com, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 06/12] x86/mm: use INVLPGB for kernel TLB flushes Date: Mon, 30 Dec 2024 12:53:07 -0500 Message-ID: <20241230175550.4046587-7-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241230175550.4046587-1-riel@surriel.com> References: <20241230175550.4046587-1-riel@surriel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: riel@surriel.com Content-Type: text/plain; charset="utf-8" Use broadcast TLB invalidation for kernel addresses when available. This stops us from having to send IPIs for kernel TLB flushes. Signed-off-by: Rik van Riel --- arch/x86/mm/tlb.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 6cf881a942bb..29207dc5b807 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -1077,6 +1077,32 @@ void flush_tlb_all(void) on_each_cpu(do_flush_tlb_all, NULL, 1); } =20 +static void broadcast_kernel_range_flush(unsigned long start, unsigned lon= g end) +{ + unsigned long addr; + unsigned long maxnr =3D invlpgb_count_max; + unsigned long threshold =3D tlb_single_page_flush_ceiling * maxnr; + + /* + * TLBSYNC only waits for flushes originating on the same CPU. + * Disabling migration allows us to wait on all flushes. + */ + guard(preempt)(); + + if (end =3D=3D TLB_FLUSH_ALL || + (end - start) > threshold << PAGE_SHIFT) { + invlpgb_flush_all(); + } else { + unsigned long nr; + for (addr =3D start; addr < end; addr +=3D nr << PAGE_SHIFT) { + nr =3D min((end - addr) >> PAGE_SHIFT, maxnr); + invlpgb_flush_addr(addr, nr); + } + } + + tlbsync(); +} + static void do_kernel_range_flush(void *info) { struct flush_tlb_info *f =3D info; @@ -1089,6 +1115,11 @@ static void do_kernel_range_flush(void *info) =20 void flush_tlb_kernel_range(unsigned long start, unsigned long end) { + if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) { + broadcast_kernel_range_flush(start, end); + return; + } + /* Balance as user space task's flush, a bit conservative */ if (end =3D=3D TLB_FLUSH_ALL || (end - start) > tlb_single_page_flush_ceiling << PAGE_SHIFT) { --=20 2.47.1 From nobody Sun May 10 06:27:03 2026 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AD751B0439 for ; Mon, 30 Dec 2024 18:06:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735581962; cv=none; b=jI2uGUwbGt9hQJOJPbR2uM/ewzszoewSeJYbP4f/9fj8/lxYVSOubf3bNbJibE5tWOJOFsko+BBxKu7o5+c5bzGGOlLSbk5ZunxESHJqpjmlVy1M6E50XEO1PlZAQRDdktc3mNq4v8flg3/Gg3ZSwpdD19RDhoXJ2TZfRSNqDkA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735581962; c=relaxed/simple; bh=g89Wy/gS6smdXFDHZyp9wPGQ5kue/U/GYy4yWFinses=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=B50gCL7B9AOtnfxNOVd1c8LjzSHDEnBCjCzf1kqHUmQcMGPmx6GM5nQw8mppAZJead9IrVWVAGlpsKu3cree6CBmU8zz8elZVpjA4nqCLV/O2gWGr4UCGkfQDeiltRctb4NMx4fVclHcYxf7sCsMUOixjCWBDlca4MNUrT/SDpw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=shelob.surriel.com; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tSJze-000000008Lf-0aOp; Mon, 30 Dec 2024 12:55:54 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, nadav.amit@gmail.com, zhengqi.arch@bytedance.com, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 07/12] x86/tlb: use INVLPGB in flush_tlb_all Date: Mon, 30 Dec 2024 12:53:08 -0500 Message-ID: <20241230175550.4046587-8-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241230175550.4046587-1-riel@surriel.com> References: <20241230175550.4046587-1-riel@surriel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: riel@surriel.com Content-Type: text/plain; charset="utf-8" The flush_tlb_all() function is not used a whole lot, but we might as well use broadcast TLB flushing there, too. Signed-off-by: Rik van Riel --- arch/x86/mm/tlb.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 29207dc5b807..266d5174fc7b 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -1074,6 +1074,12 @@ static void do_flush_tlb_all(void *info) void flush_tlb_all(void) { count_vm_tlb_event(NR_TLB_REMOTE_FLUSH); + if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) { + guard(preempt)(); + invlpgb_flush_all(); + tlbsync(); + return; + } on_each_cpu(do_flush_tlb_all, NULL, 1); } =20 --=20 2.47.1 From nobody Sun May 10 06:27:03 2026 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 934BFEDE for ; Mon, 30 Dec 2024 18:05:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735581938; cv=none; b=gbS95QQufZ330JFF20+oMx+sCzPkmUdlHAe15WehTB/COTWXfKAu+EWWCzyAsf3GWnjUihPhxN3VJRjA1xoyl53+Izf41tMcuSBQOlorRdEb3HNsS4EEUCCSbhhGLrstJ0r+hsKXLAJG/r0m0HbkwYhWhPFdCHVaV7dkJJJVi08= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735581938; c=relaxed/simple; bh=vwKSnlxhFquP3Wei5VphmF0p+mur2FAnfyMlc3Znmow=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fEYB5zo8+5lfkzmsR0lWm80MWIGrcwGsRflJRkecXMvMjp8aCVNvTx7ScvJTDbMvOj4Uo4FezAUnJoXtSj+UAiqbYTKKysMrN674bI1ItWbWXdb2sy12/Z7uSM8XyY5dPfnq2MO4gjxuZDdorRS4uR0JU3NWEv0eDTCUgUh5hfc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=shelob.surriel.com; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tSJze-000000008Lf-1jF1; Mon, 30 Dec 2024 12:55:54 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, nadav.amit@gmail.com, zhengqi.arch@bytedance.com, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 08/12] x86/mm: use broadcast TLB flushing for page reclaim TLB flushing Date: Mon, 30 Dec 2024 12:53:09 -0500 Message-ID: <20241230175550.4046587-9-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241230175550.4046587-1-riel@surriel.com> References: <20241230175550.4046587-1-riel@surriel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: riel@surriel.com Content-Type: text/plain; charset="utf-8" In the page reclaim code, we only track the CPU(s) where the TLB needs to be flushed, rather than all the individual mappings that may be getting invalidated. Use broadcast TLB flushing when that is available. Signed-off-by: Rik van Riel --- arch/x86/mm/tlb.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 266d5174fc7b..64f1679c37e1 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -1310,8 +1310,16 @@ EXPORT_SYMBOL_GPL(__flush_tlb_all); void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) { struct flush_tlb_info *info; + int cpu; + + if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) { + guard(preempt)(); + invlpgb_flush_all_nonglobals(); + tlbsync(); + return; + } =20 - int cpu =3D get_cpu(); + cpu =3D get_cpu(); =20 info =3D get_flush_tlb_info(NULL, 0, TLB_FLUSH_ALL, 0, false, TLB_GENERATION_INVALID); --=20 2.47.1 From nobody Sun May 10 06:27:03 2026 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD7271B043C for ; Mon, 30 Dec 2024 18:06:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735581965; cv=none; b=oyYbRiVMUPF2y+1jguPQnplMhJXy4rx759qfCLjbBK/5gMSBS+M9yGbA24GL9yN9QvRW1D/SydAGoEpiGqc2cfBS40oXcR9HzH3WpHJNcTVFShM6yxTPLCcAqAog/XEjJ2R1gu4E6Rkbi1u8hs0qKCprGyTmL57f8aZg860Gbsw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735581965; c=relaxed/simple; bh=Ym2pRY3EsbjRkmG93x5O6rdSgCDJAwIoRigqgkuCGQA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HuamcGFblmNcf8UC9vUYZmG6M/Vtc3HC5uuajtzBFIT85aklKTrTKUMEnZM8qeEJf4ucLrjNkDFgURmwhgSgO6UBUjS+iCqVQyA7f+EZVldyxMmaRs2IiQU5UNp34aVHqHMcv0lCGQcZwFOHtVvDT80J4T7pn0UWHRrKfnu7rf0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=shelob.surriel.com; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tSJze-000000008Lf-3Hji; Mon, 30 Dec 2024 12:55:54 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, nadav.amit@gmail.com, zhengqi.arch@bytedance.com, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 09/12] x86/mm: enable broadcast TLB invalidation for multi-threaded processes Date: Mon, 30 Dec 2024 12:53:10 -0500 Message-ID: <20241230175550.4046587-10-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241230175550.4046587-1-riel@surriel.com> References: <20241230175550.4046587-1-riel@surriel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: riel@surriel.com Content-Type: text/plain; charset="utf-8" Use broadcast TLB invalidation, using the INVPLGB instruction, on AMD EPYC 3 and newer CPUs. In order to not exhaust PCID space, and keep TLB flushes local for single threaded processes, we only hand out broadcast ASIDs to processes active on 3 or more CPUs, and gradually increase the threshold as broadcast ASID space is depleted. Signed-off-by: Rik van Riel --- arch/x86/include/asm/mmu.h | 6 + arch/x86/include/asm/mmu_context.h | 12 ++ arch/x86/include/asm/tlbflush.h | 17 ++ arch/x86/mm/tlb.c | 310 ++++++++++++++++++++++++++++- 4 files changed, 336 insertions(+), 9 deletions(-) diff --git a/arch/x86/include/asm/mmu.h b/arch/x86/include/asm/mmu.h index 3b496cdcb74b..a8e8dfa5a520 100644 --- a/arch/x86/include/asm/mmu.h +++ b/arch/x86/include/asm/mmu.h @@ -48,6 +48,12 @@ typedef struct { unsigned long flags; #endif =20 +#ifdef CONFIG_CPU_SUP_AMD + struct list_head broadcast_asid_list; + u16 broadcast_asid; + bool asid_transition; +#endif + #ifdef CONFIG_ADDRESS_MASKING /* Active LAM mode: X86_CR3_LAM_U48 or X86_CR3_LAM_U57 or 0 (disabled) */ unsigned long lam_cr3_mask; diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_= context.h index 795fdd53bd0a..0dc446c427d2 100644 --- a/arch/x86/include/asm/mmu_context.h +++ b/arch/x86/include/asm/mmu_context.h @@ -139,6 +139,8 @@ static inline void mm_reset_untag_mask(struct mm_struct= *mm) #define enter_lazy_tlb enter_lazy_tlb extern void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk); =20 +extern void destroy_context_free_broadcast_asid(struct mm_struct *mm); + /* * Init a new mm. Used on mm copies, like at fork() * and on mm's that are brand-new, like at execve(). @@ -161,6 +163,13 @@ static inline int init_new_context(struct task_struct = *tsk, mm->context.execute_only_pkey =3D -1; } #endif + +#ifdef CONFIG_CPU_SUP_AMD + INIT_LIST_HEAD(&mm->context.broadcast_asid_list); + mm->context.broadcast_asid =3D 0; + mm->context.asid_transition =3D false; +#endif + mm_reset_untag_mask(mm); init_new_context_ldt(mm); return 0; @@ -170,6 +179,9 @@ static inline int init_new_context(struct task_struct *= tsk, static inline void destroy_context(struct mm_struct *mm) { destroy_context_ldt(mm); +#ifdef CONFIG_CPU_SUP_AMD + destroy_context_free_broadcast_asid(mm); +#endif } =20 extern void switch_mm(struct mm_struct *prev, struct mm_struct *next, diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflus= h.h index 20074f17fbcd..5e9956af98d1 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -65,6 +65,23 @@ static inline void cr4_clear_bits(unsigned long mask) */ #define TLB_NR_DYN_ASIDS 6 =20 +#ifdef CONFIG_CPU_SUP_AMD +#define is_dyn_asid(asid) (asid) < TLB_NR_DYN_ASIDS +#define is_broadcast_asid(asid) (asid) >=3D TLB_NR_DYN_ASIDS +#define in_asid_transition(info) (info->mm && info->mm->context.asid_trans= ition) +#define mm_broadcast_asid(mm) (mm->context.broadcast_asid) +#else +#define is_dyn_asid(asid) true +#define is_broadcast_asid(asid) false +#define in_asid_transition(info) false +#define mm_broadcast_asid(mm) 0 + +inline bool needs_broadcast_asid_reload(struct mm_struct *next, u16 prev_a= sid) +{ + return false; +} +#endif + struct tlb_context { u64 ctx_id; u64 tlb_gen; diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 64f1679c37e1..eb83391385ce 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -74,13 +74,15 @@ * use different names for each of them: * * ASID - [0, TLB_NR_DYN_ASIDS-1] - * the canonical identifier for an mm + * the canonical identifier for an mm, dynamically allocated on ea= ch CPU + * [TLB_NR_DYN_ASIDS, MAX_ASID_AVAILABLE-1] + * the canonical, global identifier for an mm, identical across al= l CPUs * - * kPCID - [1, TLB_NR_DYN_ASIDS] + * kPCID - [1, MAX_ASID_AVAILABLE] * the value we write into the PCID part of CR3; corresponds to the * ASID+1, because PCID 0 is special. * - * uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS] + * uPCID - [2048 + 1, 2048 + MAX_ASID_AVAILABLE] * for KPTI each mm has two address spaces and thus needs two * PCID values, but we can still do with a single ASID denomination * for each mm. Corresponds to kPCID + 2048. @@ -225,6 +227,18 @@ static void choose_new_asid(struct mm_struct *next, u6= 4 next_tlb_gen, return; } =20 + /* + * TLB consistency for this ASID is maintained with INVLPGB; + * TLB flushes happen even while the process isn't running. + */ +#ifdef CONFIG_CPU_SUP_AMD + if (static_cpu_has(X86_FEATURE_INVLPGB) && mm_broadcast_asid(next)) { + *new_asid =3D mm_broadcast_asid(next); + *need_flush =3D false; + return; + } +#endif + if (this_cpu_read(cpu_tlbstate.invalidate_other)) clear_asid_other(); =20 @@ -251,6 +265,245 @@ static void choose_new_asid(struct mm_struct *next, u= 64 next_tlb_gen, *need_flush =3D true; } =20 +#ifdef CONFIG_CPU_SUP_AMD +/* + * Logic for AMD INVLPGB support. + */ +static DEFINE_RAW_SPINLOCK(broadcast_asid_lock); +static u16 last_broadcast_asid =3D TLB_NR_DYN_ASIDS; +static DECLARE_BITMAP(broadcast_asid_used, MAX_ASID_AVAILABLE) =3D { 0 }; +static LIST_HEAD(broadcast_asid_list); +static int broadcast_asid_available =3D MAX_ASID_AVAILABLE - TLB_NR_DYN_AS= IDS - 1; + +static void reset_broadcast_asid_space(void) +{ + mm_context_t *context; + + lockdep_assert_held(&broadcast_asid_lock); + + /* + * Flush once when we wrap around the ASID space, so we won't need + * to flush every time we allocate an ASID for boradcast flushing. + */ + invlpgb_flush_all_nonglobals(); + tlbsync(); + + /* + * Leave the currently used broadcast ASIDs set in the bitmap, since + * those cannot be reused before the next wraparound and flush.. + */ + bitmap_clear(broadcast_asid_used, 0, MAX_ASID_AVAILABLE); + list_for_each_entry(context, &broadcast_asid_list, broadcast_asid_list) + __set_bit(context->broadcast_asid, broadcast_asid_used); + + last_broadcast_asid =3D TLB_NR_DYN_ASIDS; +} + +static u16 get_broadcast_asid(void) +{ + lockdep_assert_held(&broadcast_asid_lock); + + do { + u16 start =3D last_broadcast_asid; + u16 asid =3D find_next_zero_bit(broadcast_asid_used, MAX_ASID_AVAILABLE,= start); + + if (asid >=3D MAX_ASID_AVAILABLE) { + reset_broadcast_asid_space(); + continue; + } + + /* Try claiming this broadcast ASID. */ + if (!test_and_set_bit(asid, broadcast_asid_used)) { + last_broadcast_asid =3D asid; + return asid; + } + } while (1); +} + +/* + * Returns true if the mm is transitioning from a CPU-local ASID to a broa= dcast + * (INVLPGB) ASID, or the other way around. + */ +static bool needs_broadcast_asid_reload(struct mm_struct *next, u16 prev_a= sid) +{ + u16 broadcast_asid =3D mm_broadcast_asid(next); + + if (broadcast_asid && prev_asid !=3D broadcast_asid) + return true; + + if (!broadcast_asid && is_broadcast_asid(prev_asid)) + return true; + + return false; +} + +void destroy_context_free_broadcast_asid(struct mm_struct *mm) +{ + if (!mm->context.broadcast_asid) + return; + + guard(raw_spinlock_irqsave)(&broadcast_asid_lock); + mm->context.broadcast_asid =3D 0; + list_del(&mm->context.broadcast_asid_list); + broadcast_asid_available++; +} + +static bool mm_active_cpus_exceeds(struct mm_struct *mm, int threshold) +{ + int count =3D 0; + int cpu; + + if (cpumask_weight(mm_cpumask(mm)) <=3D threshold) + return false; + + for_each_cpu(cpu, mm_cpumask(mm)) { + /* Skip the CPUs that aren't really running this process. */ + if (per_cpu(cpu_tlbstate.loaded_mm, cpu) !=3D mm) + continue; + + if (per_cpu(cpu_tlbstate_shared.is_lazy, cpu)) + continue; + + if (++count > threshold) + return true; + } + return false; +} + +/* + * Assign a broadcast ASID to the current process, protecting against + * races between multiple threads in the process. + */ +static void use_broadcast_asid(struct mm_struct *mm) +{ + guard(raw_spinlock_irqsave)(&broadcast_asid_lock); + + /* This process is already using broadcast TLB invalidation. */ + if (mm->context.broadcast_asid) + return; + + mm->context.broadcast_asid =3D get_broadcast_asid(); + mm->context.asid_transition =3D true; + list_add(&mm->context.broadcast_asid_list, &broadcast_asid_list); + broadcast_asid_available--; +} + +/* + * Figure out whether to assign a broadcast (global) ASID to a process. + * We vary the threshold by how empty or full broadcast ASID space is. + * 1/4 full: >=3D 4 active threads + * 1/2 full: >=3D 8 active threads + * 3/4 full: >=3D 16 active threads + * 7/8 full: >=3D 32 active threads + * etc + * + * This way we should never exhaust the broadcast ASID space, even on very + * large systems, and the processes with the largest number of active + * threads should be able to use broadcast TLB invalidation. + */ +#define HALFFULL_THRESHOLD 8 +static bool meets_broadcast_asid_threshold(struct mm_struct *mm) +{ + int avail =3D broadcast_asid_available; + int threshold =3D HALFFULL_THRESHOLD; + + if (!avail) + return false; + + if (avail > MAX_ASID_AVAILABLE * 3 / 4) { + threshold =3D HALFFULL_THRESHOLD / 4; + } else if (avail > MAX_ASID_AVAILABLE / 2) { + threshold =3D HALFFULL_THRESHOLD / 2; + } else if (avail < MAX_ASID_AVAILABLE / 3) { + do { + avail *=3D 2; + threshold *=3D 2; + } while ((avail + threshold) < MAX_ASID_AVAILABLE / 2); + } + + return mm_active_cpus_exceeds(mm, threshold); +} + +static void count_tlb_flush(struct mm_struct *mm) +{ + if (!static_cpu_has(X86_FEATURE_INVLPGB)) + return; + + /* Check every once in a while. */ + if ((current->pid & 0x1f) !=3D (jiffies & 0x1f)) + return; + + if (meets_broadcast_asid_threshold(mm)) + use_broadcast_asid(mm); +} + +static void finish_asid_transition(struct flush_tlb_info *info) +{ + struct mm_struct *mm =3D info->mm; + int bc_asid =3D mm_broadcast_asid(mm); + int cpu; + + if (!mm->context.asid_transition) + return; + + for_each_cpu(cpu, mm_cpumask(mm)) { + if (READ_ONCE(per_cpu(cpu_tlbstate.loaded_mm, cpu)) !=3D mm) + continue; + + /* + * If at least one CPU is not using the broadcast ASID yet, + * send a TLB flush IPI. The IPI should cause stragglers + * to transition soon. + */ + if (per_cpu(cpu_tlbstate.loaded_mm_asid, cpu) !=3D bc_asid) { + flush_tlb_multi(mm_cpumask(info->mm), info); + return; + } + } + + /* All the CPUs running this process are using the broadcast ASID. */ + mm->context.asid_transition =3D 0; +} + +static void broadcast_tlb_flush(struct flush_tlb_info *info) +{ + bool pmd =3D info->stride_shift =3D=3D PMD_SHIFT; + unsigned long maxnr =3D invlpgb_count_max; + unsigned long asid =3D info->mm->context.broadcast_asid; + unsigned long addr =3D info->start; + unsigned long nr; + + /* Flushing multiple pages at once is not supported with 1GB pages. */ + if (info->stride_shift > PMD_SHIFT) + maxnr =3D 1; + + if (info->end =3D=3D TLB_FLUSH_ALL) { + invlpgb_flush_single_pcid(kern_pcid(asid)); + /* Do any CPUs supporting INVLPGB need PTI? */ + if (static_cpu_has(X86_FEATURE_PTI)) + invlpgb_flush_single_pcid(user_pcid(asid)); + } else do { + /* + * Calculate how many pages can be flushed at once; if the + * remainder of the range is less than one page, flush one. + */ + nr =3D min(maxnr, (info->end - addr) >> info->stride_shift); + nr =3D max(nr, 1); + + invlpgb_flush_user_nr(kern_pcid(asid), addr, nr, pmd); + /* Do any CPUs supporting INVLPGB need PTI? */ + if (static_cpu_has(X86_FEATURE_PTI)) + invlpgb_flush_user_nr(user_pcid(asid), addr, nr, pmd); + addr +=3D nr << info->stride_shift; + } while (addr < info->end); + + finish_asid_transition(info); + + /* Wait for the INVLPGBs kicked off above to finish. */ + tlbsync(); +} +#endif /* CONFIG_CPU_SUP_AMD */ + /* * Given an ASID, flush the corresponding user ASID. We can delay this * until the next time we switch to it. @@ -556,8 +809,9 @@ void switch_mm_irqs_off(struct mm_struct *unused, struc= t mm_struct *next, */ if (prev =3D=3D next) { /* Not actually switching mm's */ - VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) !=3D - next->context.ctx_id); + if (is_dyn_asid(prev_asid)) + VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) !=3D + next->context.ctx_id); =20 /* * If this races with another thread that enables lam, 'new_lam' @@ -573,6 +827,23 @@ void switch_mm_irqs_off(struct mm_struct *unused, stru= ct mm_struct *next, !cpumask_test_cpu(cpu, mm_cpumask(next)))) cpumask_set_cpu(cpu, mm_cpumask(next)); =20 + /* + * Check if the current mm is transitioning to a new ASID. + */ + if (needs_broadcast_asid_reload(next, prev_asid)) { + next_tlb_gen =3D atomic64_read(&next->context.tlb_gen); + + choose_new_asid(next, next_tlb_gen, &new_asid, &need_flush); + goto reload_tlb; + } + + /* + * Broadcast TLB invalidation keeps this PCID up to date + * all the time. + */ + if (is_broadcast_asid(prev_asid)) + return; + /* * If the CPU is not in lazy TLB mode, we are just switching * from one thread in a process to another thread in the same @@ -626,8 +897,10 @@ void switch_mm_irqs_off(struct mm_struct *unused, stru= ct mm_struct *next, barrier(); } =20 +reload_tlb: new_lam =3D mm_lam_cr3_mask(next); if (need_flush) { + VM_BUG_ON(is_broadcast_asid(new_asid)); this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id); this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen); load_new_mm_cr3(next->pgd, new_asid, new_lam, true); @@ -746,7 +1019,7 @@ static void flush_tlb_func(void *info) const struct flush_tlb_info *f =3D info; struct mm_struct *loaded_mm =3D this_cpu_read(cpu_tlbstate.loaded_mm); u32 loaded_mm_asid =3D this_cpu_read(cpu_tlbstate.loaded_mm_asid); - u64 local_tlb_gen =3D this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].tlb= _gen); + u64 local_tlb_gen; bool local =3D smp_processor_id() =3D=3D f->initiating_cpu; unsigned long nr_invalidate =3D 0; u64 mm_tlb_gen; @@ -769,6 +1042,16 @@ static void flush_tlb_func(void *info) if (unlikely(loaded_mm =3D=3D &init_mm)) return; =20 + /* Reload the ASID if transitioning into or out of a broadcast ASID */ + if (needs_broadcast_asid_reload(loaded_mm, loaded_mm_asid)) { + switch_mm_irqs_off(NULL, loaded_mm, NULL); + loaded_mm_asid =3D this_cpu_read(cpu_tlbstate.loaded_mm_asid); + } + + /* Broadcast ASIDs are always kept up to date with INVLPGB. */ + if (is_broadcast_asid(loaded_mm_asid)) + return; + VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].ctx_id) !=3D loaded_mm->context.ctx_id); =20 @@ -786,6 +1069,8 @@ static void flush_tlb_func(void *info) return; } =20 + local_tlb_gen =3D this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen= ); + if (unlikely(f->new_tlb_gen !=3D TLB_GENERATION_INVALID && f->new_tlb_gen <=3D local_tlb_gen)) { /* @@ -953,7 +1238,7 @@ STATIC_NOPV void native_flush_tlb_multi(const struct c= pumask *cpumask, * up on the new contents of what used to be page tables, while * doing a speculative memory access. */ - if (info->freed_tables) + if (info->freed_tables || in_asid_transition(info)) on_each_cpu_mask(cpumask, flush_tlb_func, (void *)info, true); else on_each_cpu_cond_mask(should_flush_tlb, flush_tlb_func, @@ -1026,14 +1311,18 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsig= ned long start, bool freed_tables) { struct flush_tlb_info *info; + unsigned long threshold =3D tlb_single_page_flush_ceiling; u64 new_tlb_gen; int cpu; =20 + if (static_cpu_has(X86_FEATURE_INVLPGB)) + threshold *=3D invlpgb_count_max; + cpu =3D get_cpu(); =20 /* Should we flush just the requested range? */ if ((end =3D=3D TLB_FLUSH_ALL) || - ((end - start) >> stride_shift) > tlb_single_page_flush_ceiling) { + ((end - start) >> stride_shift) > threshold) { start =3D 0; end =3D TLB_FLUSH_ALL; } @@ -1049,9 +1338,12 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsign= ed long start, * a local TLB flush is needed. Optimize this use-case by calling * flush_tlb_func_local() directly in this case. */ - if (cpumask_any_but(mm_cpumask(mm), cpu) < nr_cpu_ids) { + if (IS_ENABLED(CONFIG_CPU_SUP_AMD) && mm_broadcast_asid(mm)) { + broadcast_tlb_flush(info); + } else if (cpumask_any_but(mm_cpumask(mm), cpu) < nr_cpu_ids) { info->trim_cpumask =3D should_trim_cpumask(mm); flush_tlb_multi(mm_cpumask(mm), info); + count_tlb_flush(mm); } else if (mm =3D=3D this_cpu_read(cpu_tlbstate.loaded_mm)) { lockdep_assert_irqs_enabled(); local_irq_disable(); --=20 2.47.1 From nobody Sun May 10 06:27:03 2026 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B3401B422F for ; Mon, 30 Dec 2024 18:06:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735581988; cv=none; b=RLnnz8zzdmGMziKIvC9a/k1ak22pe7fUoYfMKPa2Z6bLHGyQhVE2GxJckgYqruBMmZ0q/lzBwWIYUsugIRu9buE3AqD2eQZoNNuhgMvZ4G7stp8uf+ibS0UHlFMdDvmsWNQmehmlfbVy4Uk58tEK1uCjzj12v2hxGuyFvR6Wlcs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735581988; c=relaxed/simple; bh=OtAv6GRfSIOgo7hIA7WVqawGSav28XPEnv3ucG67peI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jitPTvCrZ22ykbOfmLXikVZqirKUOxpcHydWj5nuS+Yj2Gr/Nf6fM5l9fwimfuxMCUk4V8Sut4stggXI3BM8MsjVAEw2b2aFKrKwJFq1x3IwN1e8vmX89K/gXErGC8fPp1uBgn7Ipu+HybXuawLLLHbkDep+3RtUQxsYluIxrM4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=shelob.surriel.com; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tSJzf-000000008Lf-0ChP; Mon, 30 Dec 2024 12:55:55 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, nadav.amit@gmail.com, zhengqi.arch@bytedance.com, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 10/12] x86,tlb: do targeted broadcast flushing from tlbbatch code Date: Mon, 30 Dec 2024 12:53:11 -0500 Message-ID: <20241230175550.4046587-11-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241230175550.4046587-1-riel@surriel.com> References: <20241230175550.4046587-1-riel@surriel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: riel@surriel.com Content-Type: text/plain; charset="utf-8" Instead of doing a system-wide TLB flush from arch_tlbbatch_flush, queue up asynchronous, targeted flushes from arch_tlbbatch_add_pending. This also allows us to avoid adding the CPUs of processes using broadcast flushing to the batch->cpumask, and will hopefully further reduce TLB flushing from the reclaim and compaction paths. Signed-off-by: Rik van Riel --- arch/x86/include/asm/tlbbatch.h | 1 + arch/x86/include/asm/tlbflush.h | 12 +++------ arch/x86/mm/tlb.c | 48 ++++++++++++++++++++++++++------- 3 files changed, 42 insertions(+), 19 deletions(-) diff --git a/arch/x86/include/asm/tlbbatch.h b/arch/x86/include/asm/tlbbatc= h.h index 1ad56eb3e8a8..f9a17edf63ad 100644 --- a/arch/x86/include/asm/tlbbatch.h +++ b/arch/x86/include/asm/tlbbatch.h @@ -10,6 +10,7 @@ struct arch_tlbflush_unmap_batch { * the PFNs being flushed.. */ struct cpumask cpumask; + bool used_invlpgb; }; =20 #endif /* _ARCH_X86_TLBBATCH_H */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflus= h.h index 5e9956af98d1..17ec1b169ebd 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -297,21 +297,15 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm) return atomic64_inc_return(&mm->context.tlb_gen); } =20 -static inline void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_ba= tch *batch, - struct mm_struct *mm, - unsigned long uaddr) -{ - inc_mm_tlb_gen(mm); - cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm)); - mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL); -} - static inline void arch_flush_tlb_batched_pending(struct mm_struct *mm) { flush_tlb_mm(mm); } =20 extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch); +extern void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *ba= tch, + struct mm_struct *mm, + unsigned long uaddr); =20 static inline bool pte_flags_need_flush(unsigned long oldflags, unsigned long newflags, diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index eb83391385ce..454a370494d3 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -1602,16 +1602,7 @@ EXPORT_SYMBOL_GPL(__flush_tlb_all); void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) { struct flush_tlb_info *info; - int cpu; - - if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) { - guard(preempt)(); - invlpgb_flush_all_nonglobals(); - tlbsync(); - return; - } - - cpu =3D get_cpu(); + int cpu =3D get_cpu(); =20 info =3D get_flush_tlb_info(NULL, 0, TLB_FLUSH_ALL, 0, false, TLB_GENERATION_INVALID); @@ -1629,12 +1620,49 @@ void arch_tlbbatch_flush(struct arch_tlbflush_unmap= _batch *batch) local_irq_enable(); } =20 + /* + * If we issued (asynchronous) INVLPGB flushes, wait for them here. + * The cpumask above contains only CPUs that were running tasks + * not using broadcast TLB flushing. + */ + if (cpu_feature_enabled(X86_FEATURE_INVLPGB) && batch->used_invlpgb) { + tlbsync(); + migrate_enable(); + batch->used_invlpgb =3D false; + } + cpumask_clear(&batch->cpumask); =20 put_flush_tlb_info(); put_cpu(); } =20 +void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, + struct mm_struct *mm, + unsigned long uaddr) +{ + if (static_cpu_has(X86_FEATURE_INVLPGB) && mm_broadcast_asid(mm)) { + u16 asid =3D mm_broadcast_asid(mm); + /* + * Queue up an asynchronous invalidation. The corresponding + * TLBSYNC is done in arch_tlbbatch_flush(), and must be done + * on the same CPU. + */ + if (!batch->used_invlpgb) { + batch->used_invlpgb =3D true; + migrate_disable(); + } + invlpgb_flush_user_nr(kern_pcid(asid), uaddr, 1, 0); + /* Do any CPUs supporting INVLPGB need PTI? */ + if (static_cpu_has(X86_FEATURE_PTI)) + invlpgb_flush_user_nr(user_pcid(asid), uaddr, 1, 0); + } else { + inc_mm_tlb_gen(mm); + cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm)); + } + mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL); +} + /* * Blindly accessing user memory from NMI context can be dangerous * if we're in the middle of switching the current user task or --=20 2.47.1 From nobody Sun May 10 06:27:03 2026 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C1A41B0437 for ; Mon, 30 Dec 2024 18:06:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735581994; cv=none; b=WjLBGYjj0sumXFgwUNnBOp19QJV1NLEWVxr4UzlLY+GaA3dQUlmc63vQ6XqVaXGvUWGYM3BcEOP066bW0fcC9IvexU5bsZJk2c4nzvFl1F8+T9IT7uZEKcAWERVUKlK5RdvZ3WkQWbhvXGQk9X/qd39/MvTyPd/+68EgpmJ/IyQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735581994; c=relaxed/simple; bh=tOUSI5RGft1SXvut59cbSLRd10l0mLm+tsKZPXmc/+8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=C/BZURjd9L4hqncvdOuuwbDM6oWhAn3dW77CIhNoSfQsCiB+Yh9Kvbty0JZoWOQJ/jhhhYkw6shx7UejDeWUfJTfhAHZZdfh5MQ2YbosnnMkRmPodzG3pedTIrUHUeYxX+k/DsaQDuvJ/dh9wfYqWXM9dWrT0oHpfXM6FfLn7sU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=shelob.surriel.com; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tSJzf-000000008Lf-1Qtd; Mon, 30 Dec 2024 12:55:55 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, nadav.amit@gmail.com, zhengqi.arch@bytedance.com, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 11/12] x86/mm: enable AMD translation cache extensions Date: Mon, 30 Dec 2024 12:53:12 -0500 Message-ID: <20241230175550.4046587-12-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241230175550.4046587-1-riel@surriel.com> References: <20241230175550.4046587-1-riel@surriel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: riel@surriel.com Content-Type: text/plain; charset="utf-8" With AMD TCE (translation cache extensions) only the intermediate mappings that cover the address range zapped by INVLPG / INVLPGB get invalidated, rather than all intermediate mappings getting zapped at every TLB invalidat= ion. This can help reduce the TLB miss rate, by keeping more intermediate mappings in the cache. From the AMD manual: Translation Cache Extension (TCE) Bit. Bit 15, read/write. Setting this bit to 1 changes how the INVLPG, INVLPGB, and INVPCID instructions operate on TLB entries. When this bit is 0, these instructions remove the target PTE from the TLB as well as all upper-level table entries that are cached in the TLB, whether or not they are associated with the target PTE. When this bit is set, these instructions will remove the target PTE and only those upper-level entries that lead to the target PTE in the page table hierarchy, leaving unrelated upper-level entries intact. Signed-off-by: Rik van Riel --- arch/x86/kernel/cpu/amd.c | 8 ++++++++ arch/x86/mm/tlb.c | 10 +++++++--- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 226b8fc64bfc..4dc42705aaca 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1143,6 +1143,14 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) =20 /* Max number of pages INVLPGB can invalidate in one shot */ invlpgb_count_max =3D (edx & 0xffff) + 1; + + /* If supported, enable translation cache extensions (TCE) */ + cpuid(0x80000001, &eax, &ebx, &ecx, &edx); + if (ecx & BIT(17)) { + u64 msr =3D native_read_msr(MSR_EFER);; + msr |=3D BIT(15); + wrmsrl(MSR_EFER, msr); + } } =20 static const struct cpu_dev amd_cpu_dev =3D { diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 454a370494d3..585d0731ca9f 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -477,7 +477,7 @@ static void broadcast_tlb_flush(struct flush_tlb_info *= info) if (info->stride_shift > PMD_SHIFT) maxnr =3D 1; =20 - if (info->end =3D=3D TLB_FLUSH_ALL) { + if (info->end =3D=3D TLB_FLUSH_ALL || info->freed_tables) { invlpgb_flush_single_pcid(kern_pcid(asid)); /* Do any CPUs supporting INVLPGB need PTI? */ if (static_cpu_has(X86_FEATURE_PTI)) @@ -1110,7 +1110,7 @@ static void flush_tlb_func(void *info) * * The only question is whether to do a full or partial flush. * - * We do a partial flush if requested and two extra conditions + * We do a partial flush if requested and three extra conditions * are met: * * 1. f->new_tlb_gen =3D=3D local_tlb_gen + 1. We have an invariant that @@ -1137,10 +1137,14 @@ static void flush_tlb_func(void *info) * date. By doing a full flush instead, we can increase * local_tlb_gen all the way to mm_tlb_gen and we can probably * avoid another flush in the very near future. + * + * 3. No page tables were freed. If page tables were freed, a full + * flush ensures intermediate translations in the TLB get flushed. */ if (f->end !=3D TLB_FLUSH_ALL && f->new_tlb_gen =3D=3D local_tlb_gen + 1 && - f->new_tlb_gen =3D=3D mm_tlb_gen) { + f->new_tlb_gen =3D=3D mm_tlb_gen && + !f->freed_tables) { /* Partial flush */ unsigned long addr =3D f->start; =20 --=20 2.47.1 From nobody Sun May 10 06:27:03 2026 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BCA691B415C for ; Mon, 30 Dec 2024 18:05:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735581954; cv=none; b=fEDzRhxgc67xHUiHrDVi9d6J1Cv28JVc/1W1FU8goIl1bTha7jRyUDf0H71JMaWMFnwtdesUmGpdMK+iQhR6Lt1ByuwRO5OxcK0MR3jxJui5gcxrVIHYPO3zFPDz2ccrBGYHiyRdx8ANS0R6zLX7nMK0XvnYp/ZUPH4b58I+ZT4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735581954; c=relaxed/simple; bh=FT0ac0zrYfeb4u2EYVt6+KU+oAfxwM9JTToymuxvJak=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RSs5J53XJmRvt2lJaxS4SwAPfJd6NMvqKxtMxz8qilWwAmq9LHB90qz8OathogfLj1MulHIZs+a9v8yI345KCbJwsJxTX4UON2sKGkRrLhQM5fcGlg2XxRoYRpQFI66JuSczXGMAcnpotGMlnKE3QGhm9mUCyisBM4DBRgwMsJE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=shelob.surriel.com; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tSJzf-000000008Lf-2gRa; Mon, 30 Dec 2024 12:55:55 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, nadav.amit@gmail.com, zhengqi.arch@bytedance.com, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 12/12] x86/mm: only invalidate final translations with INVLPGB Date: Mon, 30 Dec 2024 12:53:13 -0500 Message-ID: <20241230175550.4046587-13-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241230175550.4046587-1-riel@surriel.com> References: <20241230175550.4046587-1-riel@surriel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: riel@surriel.com Content-Type: text/plain; charset="utf-8" Use the INVLPGB_FINAL_ONLY flag when invalidating mappings with INVPLGB. This way only leaf mappings get removed from the TLB, leaving intermediate translations cached. On the (rare) occasions where we free page tables we do a full flush, ensuring intermediate translations get flushed from the TLB. Signed-off-by: Rik van Riel --- arch/x86/include/asm/invlpgb.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/invlpgb.h b/arch/x86/include/asm/invlpgb.h index 862775897a54..2669ebfffe81 100644 --- a/arch/x86/include/asm/invlpgb.h +++ b/arch/x86/include/asm/invlpgb.h @@ -51,7 +51,7 @@ static inline void invlpgb_flush_user(unsigned long pcid, static inline void invlpgb_flush_user_nr(unsigned long pcid, unsigned long= addr, int nr, bool pmd_stride) { - __invlpgb(0, pcid, addr, nr - 1, pmd_stride, INVLPGB_PCID | INVLPGB_VA); + __invlpgb(0, pcid, addr, nr - 1, pmd_stride, INVLPGB_PCID | INVLPGB_VA | = INVLPGB_FINAL_ONLY); } =20 /* Flush all mappings for a given ASID, not including globals. */ --=20 2.47.1