From nobody Thu Dec 18 09:49:01 2025 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4EE011A00FE for ; Sun, 29 Dec 2024 14:51:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735483866; cv=none; b=ckaZOQXhQfr+KsAadRILre+zgql7r5/QQrihdTPFuvRzu2+oZ5ScISCtd6utXYoHRXrSoGg13uTbw4kj2/Leuw8Kx0yvRrWbk2xEdRumv0BTQlsBx6cVoAXOMuX36ZJrEeAiz+3W0VfPM+GnWW7q3uNRHGcJX2O3m4kEl8ZcThE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735483866; c=relaxed/simple; bh=wAM96yqCW+lsz81e2QPgNILmLnuIJ654UrL1361ydeg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Erf+fi3s26M5d3GK1yaJyHMtOxLxTiYvCgVuMOh4Sb9x1SZowRAD9y7cURq3dhn5gA372q2vWE/SLR92MdhQbAy1kFV5VY6KdZa16L+63r7O4KPdIL4+bVtYJ6Ogc1m5FfK6Hznyk8//gjMfAJjAoJAVOVeXuIHloAncrfmHPv4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=AnviPi7l; arc=none smtp.client-ip=209.85.218.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="AnviPi7l" Received: by mail-ej1-f48.google.com with SMTP id a640c23a62f3a-aa66e4d1d5aso1363805166b.2 for ; Sun, 29 Dec 2024 06:51:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1735483863; x=1736088663; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6wKU7hDbBAEhh5ugFEv8c2E//GwNCMwODyh4qXAxbC4=; b=AnviPi7lqL01/1x45KkXpYscaqjga4hdoUfhMvrDRz5dcKADU7+ZXkwZYAKnL89ffs /esfPcKq4m7fiMXC3Cnw8piXh+28YAdfpKMrYi6ZoTdeA6Vf1yah2z3igJuo6fKGQyVM MhBa6UAM8V9cO0nBisVfd1wOzbjMmPEDntWxE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735483863; x=1736088663; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6wKU7hDbBAEhh5ugFEv8c2E//GwNCMwODyh4qXAxbC4=; b=cHFrIlU348UwOgZ833dxg2VlFnIp0REqgQi6x0iSo+O5pO6Nzy8H5eW2K/H9+/4WO7 Ff6oGKlG87+/1HZucdE5J3x0TBX5VgZnfM8LNgExZL0/YgD8cVE3fx7IDWku2sBUxDkd nlCWBb8gMicGy+ixCtpNazQSIb5sX5j7C3NGPIR/84mwyZZHIyl1oVVufT6+Re8dfHDV Yqjw/zsF7bHhSK0HrVPa/W8VnomCzBBIOZvQlqt7N5Jl9aC7laVcOtm4BFh9+UxbDSag 3peJYnDqSlzUHTvRdkfR2Nscbdn2N/W+PNy9PpUKoJoV9V6TuXI3A4XFwdhP6zuFQlUR G1VQ== X-Gm-Message-State: AOJu0YyuG436kDnzW3+ZhWW9qCXkVqw+CPBh0Jqa0AH1yE84eDVEU0CL Wpu6zNXW5W5msCgOOcp9uu57fJVK8pXfAa+fdbeTQ5fsHFLOFr34ov3Gj/df3p9SgZ7umy/8rNU 5 X-Gm-Gg: ASbGncvIEkxzHVtVehp7+PD6DRbxpG2R0DdmDYXNQ3TrCrXZBIL9TKf+5S7E54UnAHj i4T0V6d97d0GjnmaW/IHtk6f/kZ6wKIwSeDaXM6kpmnl/Q02xFSEJI/3hCSXmYSOTnJTIOSvSu+ CKhUEllZvEpWX3+1O2Sc85yu38E/0c4ZUgJ4ahCHK9aXdVwd+HmPLDa+sNXkiTTKBKfYVhVyvU8 0tWefujX5DqAmbzPD526gvPbE2TspieWosLsXCMVpyWc0kDf5iP9MlIhz0sc1D+QarBwUZ/+YLJ pPWy9Ml0Y/5gXVO07rP+HA== X-Google-Smtp-Source: AGHT+IGuXfjaRQPAunk4u+eEYZZYA62lhB0xm8g69aCXAJE2Mnda7O4OIdrZd531BTzMeroRuU5qFw== X-Received: by 2002:a17:907:2d2c:b0:aa6:8b38:52a3 with SMTP id a640c23a62f3a-aac33787557mr2382898066b.50.1735483861073; Sun, 29 Dec 2024 06:51:01 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0e895080sm1362084466b.47.2024.12.29.06.50.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Dec 2024 06:51:00 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v8 18/18] clk: imx8mn: support spread spectrum clock generation Date: Sun, 29 Dec 2024 15:49:42 +0100 Message-ID: <20241229145027.3984542-19-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241229145027.3984542-1-dario.binacchi@amarulasolutions.com> References: <20241229145027.3984542-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for spread spectrum clock generation for the audio, video, and DRAM PLLs. Signed-off-by: Dario Binacchi Reviewed-by: Peng Fan --- Changes in v8: - Drop the patches added in version 7: - 10/23 dt-bindings: clock: imx8m-clock: add phandle to the anatop - 11/23 arm64: dts: imx8mm: add phandle to anatop within CCM - 12/23 arm64: dts: imx8mn: add phandle to anatop within CCM - 13/23 arm64: dts: imx8mp: add phandle to anatop within CCM - 14/23 arm64: dts: imx8mq: add phandle to anatop within CCM Changes in v7: - Add and manage fsl,anatop property as phandle to the anatop node with the new patches: - 10/23 dt-bindings: clock: imx8m-clock: add phandle to the anatop - 11/23 arm64: dts: imx8mm: add phandle to anatop within CCM - 12/23 arm64: dts: imx8mn: add phandle to anatop within CCM - 13/23 arm64: dts: imx8mp: add phandle to anatop within CCM - 14/23 arm64: dts: imx8mq: add phandle to anatop within CCM Changes in v6: - Merge patches: 10/20 dt-bindings: clock: imx8mm: add binding definitions for anatop 11/20 dt-bindings: clock: imx8mn: add binding definitions for anatop 12/20 dt-bindings: clock: imx8mp: add binding definitions for anatop to 05/20 dt-bindings: clock: imx8m-anatop: define clocks/clock-names now renamed 05/18 dt-bindings: clock: imx8m-anatop: add oscillators and PLLs - Split the patch 15/20 dt-bindings-clock-imx8m-clock-support-spread-spectru.patch into 12/18 dt-bindings: clock: imx8m-clock: add PLLs 16/18 dt-bindings: clock: imx8m-clock: support spread spectrum clocking Changes in v5: - Fix compilation errors. - Separate driver code from dt-bindings Changes in v4: - Add dt-bindings for anatop - Add anatop driver - Drop fsl,ssc-clocks from spread spectrum dt-bindings Changes in v3: - Patches 1/8 has been added in version 3. The dt-bindings have been moved from fsl,imx8m-anatop.yaml to imx8m-clock.yaml. The anatop device (fsl,imx8m-anatop.yaml) is indeed more or less a syscon, so it represents a memory area accessible by ccm (imx8m-clock.yaml) to setup the PLLs. - Patches {3,5}/8 have been added in version 3. - Patches {4,6,8}/8 use ccm device node instead of the anatop one. Changes in v2: - Add "allOf:" and place it after "required:" block, like in the example schema. - Move the properties definition to the top-level. - Drop unit types as requested by the "make dt_binding_check" command. drivers/clk/imx/clk-imx8mn.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index c3a3d063d58e..090b5924fa01 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -306,6 +306,7 @@ static int imx8mn_clocks_probe(struct platform_device *= pdev) struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node, *anp; void __iomem *base; + struct imx_pll14xx_ssc ssc_conf; int ret; =20 base =3D devm_platform_ioremap_resource(pdev, 0); @@ -344,9 +345,21 @@ static int imx8mn_clocks_probe(struct platform_device = *pdev) hws[IMX8MN_SYS_PLL3_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP= _SYS_PLL3_REF_SEL); =20 hws[IMX8MN_AUDIO_PLL1] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO= _PLL1); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll1", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MN_AUDIO_PLL1], &ssc_conf); + hws[IMX8MN_AUDIO_PLL2] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO= _PLL2); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll2", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MN_AUDIO_PLL2], &ssc_conf); + hws[IMX8MN_VIDEO_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VIDEO_= PLL); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "video_pll", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MN_VIDEO_PLL], &ssc_conf); + hws[IMX8MN_DRAM_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRAM_PL= L); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "dram_pll", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MN_DRAM_PLL], &ssc_conf); + hws[IMX8MN_GPU_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_PLL); hws[IMX8MN_M7_ALT_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M7_AL= T_PLL); hws[IMX8MN_ARM_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_PLL); --=20 2.43.0