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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:24 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Krzysztof Kozlowski , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 01/23] dt-bindings: clock: imx8mm: add VIDEO_PLL clocks Date: Fri, 27 Dec 2024 17:56:04 +0100 Message-ID: <20241227165719.3902388-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the name used in the RM is video_pll. So, let's add the IMX8MM_VIDEO_PLL[_*] definitions to be consistent with the RM and avoid misunderstandings. The IMX8MM_VIDEO_PLL1* constants have not been removed to ensure backward compatibility of the patch. No functional changes intended. Signed-off-by: Dario Binacchi Acked-by: Krzysztof Kozlowski --- (no changes since v6) Changes in v6: - Add 'Acked-by' tag of Krzysztof Kozlowski Changes in v5: - New include/dt-bindings/clock/imx8mm-clock.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings= /clock/imx8mm-clock.h index 1f768b2eeb1a..102d8a6cdb55 100644 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -16,7 +16,8 @@ #define IMX8MM_CLK_EXT4 7 #define IMX8MM_AUDIO_PLL1_REF_SEL 8 #define IMX8MM_AUDIO_PLL2_REF_SEL 9 -#define IMX8MM_VIDEO_PLL1_REF_SEL 10 +#define IMX8MM_VIDEO_PLL_REF_SEL 10 +#define IMX8MM_VIDEO_PLL1_REF_SEL IMX8MM_VIDEO_PLL_REF_SEL #define IMX8MM_DRAM_PLL_REF_SEL 11 #define IMX8MM_GPU_PLL_REF_SEL 12 #define IMX8MM_VPU_PLL_REF_SEL 13 @@ -26,7 +27,8 @@ #define IMX8MM_SYS_PLL3_REF_SEL 17 #define IMX8MM_AUDIO_PLL1 18 #define IMX8MM_AUDIO_PLL2 19 -#define IMX8MM_VIDEO_PLL1 20 +#define IMX8MM_VIDEO_PLL 20 +#define IMX8MM_VIDEO_PLL1 IMX8MM_VIDEO_PLL #define IMX8MM_DRAM_PLL 21 #define IMX8MM_GPU_PLL 22 #define IMX8MM_VPU_PLL 23 @@ -36,7 +38,8 @@ #define IMX8MM_SYS_PLL3 27 #define IMX8MM_AUDIO_PLL1_BYPASS 28 #define IMX8MM_AUDIO_PLL2_BYPASS 29 -#define IMX8MM_VIDEO_PLL1_BYPASS 30 +#define IMX8MM_VIDEO_PLL_BYPASS 30 +#define IMX8MM_VIDEO_PLL1_BYPASS IMX8MM_VIDEO_PLL_BYPASS #define IMX8MM_DRAM_PLL_BYPASS 31 #define IMX8MM_GPU_PLL_BYPASS 32 #define IMX8MM_VPU_PLL_BYPASS 33 @@ -46,7 +49,8 @@ #define IMX8MM_SYS_PLL3_BYPASS 37 #define IMX8MM_AUDIO_PLL1_OUT 38 #define IMX8MM_AUDIO_PLL2_OUT 39 -#define IMX8MM_VIDEO_PLL1_OUT 40 +#define IMX8MM_VIDEO_PLL_OUT 40 +#define IMX8MM_VIDEO_PLL1_OUT IMX8MM_VIDEO_PLL_OUT #define IMX8MM_DRAM_PLL_OUT 41 #define IMX8MM_GPU_PLL_OUT 42 #define IMX8MM_VPU_PLL_OUT 43 --=20 2.43.0 From nobody Sun May 10 07:14:10 2026 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A98FE1F867A for ; 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:26 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Peng Fan , Abel Vesa , Fabio Estevam , Michael Turquette , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 02/23] clk: imx8mm: rename video_pll1 to video_pll Date: Fri, 27 Dec 2024 17:56:05 +0100 Message-ID: <20241227165719.3902388-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the name used in the RM is video_pll. So, let's rename "video_pll1" to "video_pll" to be consistent with the RM and avoid misunderstandings. No functional changes intended. Signed-off-by: Dario Binacchi Reviewed-by: Peng Fan --- The patch, which simply replaces video_pll1 with video_pll, highlights many warnings raised by checkpatch.pl. These are not generated by the changes made but are inherited from how the module was originally written. Fixing them would have meant "obscuring" the actual changes introduced. Changes in v7: - Add 'Reviewed-by' tag of Peng Fan Changes in v5: - Split the patch dropping the dt-bindings changes. Changes in v4: - New drivers/clk/imx/clk-imx8mm.c | 102 +++++++++++++++++------------------ 1 file changed, 51 insertions(+), 51 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 342049b847b9..8a1fc7e17ba2 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -28,7 +28,7 @@ static u32 share_count_nand; static const char *pll_ref_sels[] =3D { "osc_24m", "dummy", "dummy", "dumm= y", }; static const char *audio_pll1_bypass_sels[] =3D {"audio_pll1", "audio_pll1= _ref_sel", }; static const char *audio_pll2_bypass_sels[] =3D {"audio_pll2", "audio_pll2= _ref_sel", }; -static const char *video_pll1_bypass_sels[] =3D {"video_pll1", "video_pll1= _ref_sel", }; +static const char *video_pll_bypass_sels[] =3D {"video_pll", "video_pll_re= f_sel", }; static const char *dram_pll_bypass_sels[] =3D {"dram_pll", "dram_pll_ref_s= el", }; static const char *gpu_pll_bypass_sels[] =3D {"gpu_pll", "gpu_pll_ref_sel"= , }; static const char *vpu_pll_bypass_sels[] =3D {"vpu_pll", "vpu_pll_ref_sel"= , }; @@ -42,22 +42,22 @@ static const char *imx8mm_a53_sels[] =3D {"osc_24m", "a= rm_pll_out", "sys_pll2_500m static const char * const imx8mm_a53_core_sels[] =3D {"arm_a53_div", "arm_= pll_out", }; =20 static const char *imx8mm_m4_sels[] =3D {"osc_24m", "sys_pll2_200m", "sys_= pll2_250m", "sys_pll1_266m", - "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_= out", }; + "sys_pll1_800m", "audio_pll1_out", "video_pll_out", "sys_pll3_o= ut", }; =20 static const char *imx8mm_vpu_sels[] =3D {"osc_24m", "arm_pll_out", "sys_p= ll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "vpu_pll_out", }; =20 static const char *imx8mm_gpu3d_sels[] =3D {"osc_24m", "gpu_pll_out", "sys= _pll1_800m", "sys_pll3_out", - "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_o= ut", }; + "sys_pll2_1000m", "audio_pll1_out", "video_pll_out", "audio_pll2_ou= t", }; =20 static const char *imx8mm_gpu2d_sels[] =3D {"osc_24m", "gpu_pll_out", "sys= _pll1_800m", "sys_pll3_out", - "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_o= ut", }; + "sys_pll2_1000m", "audio_pll1_out", "video_pll_out", "audio_pll2_ou= t", }; =20 static const char *imx8mm_main_axi_sels[] =3D {"osc_24m", "sys_pll2_333m",= "sys_pll1_800m", "sys_pll2_250m", - "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "sys_pll1_= 100m",}; + "sys_pll2_1000m", "audio_pll1_out", "video_pll_out", "sys_pll1_1= 00m",}; =20 static const char *imx8mm_enet_axi_sels[] =3D {"osc_24m", "sys_pll1_266m",= "sys_pll1_800m", "sys_pll2_250m", - "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_o= ut", }; + "sys_pll2_200m", "audio_pll1_out", "video_pll_out", "sys_pll3_ou= t", }; =20 static const char *imx8mm_nand_usdhc_sels[] =3D {"osc_24m", "sys_pll1_266m= ", "sys_pll1_800m", "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_= out", }; @@ -72,28 +72,28 @@ static const char *imx8mm_disp_apb_sels[] =3D {"osc_24m= ", "sys_pll2_125m", "sys_pl "sys_pll1_40m", "audio_pll2_out", "clk_ext1", "clk_ext3", }; =20 static const char *imx8mm_disp_rtrm_sels[] =3D {"osc_24m", "sys_pll1_800m"= , "sys_pll2_200m", "sys_pll2_1000m", - "audio_pll1_out", "video_pll1_out", "clk_ext2", "clk_ext3", }; + "audio_pll1_out", "video_pll_out", "clk_ext2", "clk_ext3", }; =20 static const char *imx8mm_usb_bus_sels[] =3D {"osc_24m", "sys_pll2_500m", = "sys_pll1_800m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", }; =20 static const char *imx8mm_gpu_axi_sels[] =3D {"osc_24m", "sys_pll1_800m", = "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", - "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + "audio_pll1_out", "video_pll_out", "audio_pll2_out", }; =20 static const char *imx8mm_gpu_ahb_sels[] =3D {"osc_24m", "sys_pll1_800m", = "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", - "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + "audio_pll1_out", "video_pll_out", "audio_pll2_out", }; =20 static const char *imx8mm_noc_sels[] =3D {"osc_24m", "sys_pll1_800m", "sys= _pll3_out", "sys_pll2_1000m", "sys_pll2_500m", - "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + "audio_pll1_out", "video_pll_out", "audio_pll2_out", }; =20 static const char *imx8mm_noc_apb_sels[] =3D {"osc_24m", "sys_pll1_400m", = "sys_pll3_out", "sys_pll2_333m", "sys_pll2_200m", - "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", }; + "sys_pll1_800m", "audio_pll1_out", "video_pll_out", }; =20 static const char *imx8mm_ahb_sels[] =3D {"osc_24m", "sys_pll1_133m", "sys= _pll1_800m", "sys_pll1_400m", - "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", = }; + "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", }; =20 static const char *imx8mm_audio_ahb_sels[] =3D {"osc_24m", "sys_pll2_500m"= , "sys_pll1_800m", "sys_pll2_1000m", - "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", "video_pll1_= out", }; + "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", "video_pll_o= ut", }; =20 static const char *imx8mm_dram_alt_sels[] =3D {"osc_24m", "sys_pll1_800m",= "sys_pll1_100m", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out", "audio_pll1_out", "sys_pll1_26= 6m", }; @@ -108,10 +108,10 @@ static const char *imx8mm_vpu_g2_sels[] =3D {"osc_24m= ", "vpu_pll_out", "sys_pll1_8 "sys_pll1_100m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out"= , }; =20 static const char *imx8mm_disp_dtrc_sels[] =3D {"osc_24m", "dummy", "sys_p= ll1_800m", "sys_pll2_1000m", - "sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_= out", }; + "sys_pll1_160m", "video_pll_out", "sys_pll3_out", "audio_pll2_o= ut", }; =20 static const char *imx8mm_disp_dc8000_sels[] =3D {"osc_24m", "dummy", "sys= _pll1_800m", "sys_pll2_1000m", - "sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_out",= }; + "sys_pll1_160m", "video_pll_out", "sys_pll3_out", "audio_pll2_out", = }; =20 static const char *imx8mm_pcie1_ctrl_sels[] =3D {"osc_24m", "sys_pll2_250m= ", "sys_pll2_200m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_o= ut", }; @@ -122,47 +122,47 @@ static const char *imx8mm_pcie1_phy_sels[] =3D {"osc_= 24m", "sys_pll2_100m", "sys_p static const char *imx8mm_pcie1_aux_sels[] =3D {"osc_24m", "sys_pll2_200m"= , "sys_pll2_50m", "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200= m", }; =20 -static const char *imx8mm_dc_pixel_sels[] =3D {"osc_24m", "video_pll1_out"= , "audio_pll2_out", "audio_pll1_out", +static const char *imx8mm_dc_pixel_sels[] =3D {"osc_24m", "video_pll_out",= "audio_pll2_out", "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", }; =20 -static const char *imx8mm_lcdif_pixel_sels[] =3D {"osc_24m", "video_pll1_o= ut", "audio_pll2_out", "audio_pll1_out", +static const char *imx8mm_lcdif_pixel_sels[] =3D {"osc_24m", "video_pll_ou= t", "audio_pll2_out", "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", }; =20 -static const char *imx8mm_sai1_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai1_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext1", "clk_ext2", }; =20 -static const char *imx8mm_sai2_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai2_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; =20 -static const char *imx8mm_sai3_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai3_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; =20 -static const char *imx8mm_sai4_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai4_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext1", "clk_ext2", }; =20 -static const char *imx8mm_sai5_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai5_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; =20 -static const char *imx8mm_sai6_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai6_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; =20 -static const char *imx8mm_spdif1_sels[] =3D {"osc_24m", "audio_pll1_out", = "audio_pll2_out", "video_pll1_out", +static const char *imx8mm_spdif1_sels[] =3D {"osc_24m", "audio_pll1_out", = "audio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; =20 -static const char *imx8mm_spdif2_sels[] =3D {"osc_24m", "audio_pll1_out", = "audio_pll2_out", "video_pll1_out", +static const char *imx8mm_spdif2_sels[] =3D {"osc_24m", "audio_pll1_out", = "audio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; =20 static const char *imx8mm_enet_ref_sels[] =3D {"osc_24m", "sys_pll2_125m",= "sys_pll2_50m", "sys_pll2_100m", - "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4",= }; + "sys_pll1_160m", "audio_pll1_out", "video_pll_out", "clk_ext4", = }; =20 static const char *imx8mm_enet_timer_sels[] =3D {"osc_24m", "sys_pll2_100m= ", "audio_pll1_out", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4", "video_pll1_out", }; + "clk_ext3", "clk_ext4", "video_pll_out", }; =20 static const char *imx8mm_enet_phy_sels[] =3D {"osc_24m", "sys_pll2_50m", = "sys_pll2_125m", "sys_pll2_200m", - "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", }; + "sys_pll2_500m", "video_pll_out", "audio_pll2_out", }; =20 static const char *imx8mm_nand_sels[] =3D {"osc_24m", "sys_pll2_500m", "au= dio_pll1_out", "sys_pll1_400m", - "audio_pll2_out", "sys_pll3_out", "sys_pll2_250m", "video_pll1_out",= }; + "audio_pll2_out", "sys_pll3_out", "sys_pll2_250m", "video_pll_out", = }; =20 static const char *imx8mm_qspi_sels[] =3D {"osc_24m", "sys_pll1_400m", "sy= s_pll2_333m", "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", = }; @@ -174,16 +174,16 @@ static const char *imx8mm_usdhc2_sels[] =3D {"osc_24m= ", "sys_pll1_400m", "sys_pll1 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m"= , }; =20 static const char *imx8mm_i2c1_sels[] =3D {"osc_24m", "sys_pll1_160m", "sy= s_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; + "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char *imx8mm_i2c2_sels[] =3D {"osc_24m", "sys_pll1_160m", "sy= s_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; + "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char *imx8mm_i2c3_sels[] =3D {"osc_24m", "sys_pll1_160m", "sy= s_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; + "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char *imx8mm_i2c4_sels[] =3D {"osc_24m", "sys_pll1_160m", "sy= s_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; + "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char *imx8mm_uart1_sels[] =3D {"osc_24m", "sys_pll1_80m", "sy= s_pll2_200m", "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4", "audio_pll2_out", }; @@ -213,19 +213,19 @@ static const char *imx8mm_ecspi2_sels[] =3D {"osc_24m= ", "sys_pll2_200m", "sys_pll1 "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out"= , }; =20 static const char *imx8mm_pwm1_sels[] =3D {"osc_24m", "sys_pll2_100m", "sy= s_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; + "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", }; =20 static const char *imx8mm_pwm2_sels[] =3D {"osc_24m", "sys_pll2_100m", "sy= s_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; + "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", }; =20 static const char *imx8mm_pwm3_sels[] =3D {"osc_24m", "sys_pll2_100m", "sy= s_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; + "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", }; =20 static const char *imx8mm_pwm4_sels[] =3D {"osc_24m", "sys_pll2_100m", "sy= s_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; + "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", }; =20 static const char *imx8mm_gpt1_sels[] =3D {"osc_24m", "sys_pll2_100m", "sy= s_pll1_400m", "sys_pll1_40m", - "video_pll1_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" }; + "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" }; =20 static const char *imx8mm_wdog_sels[] =3D {"osc_24m", "sys_pll1_133m", "sy= s_pll1_160m", "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; @@ -234,31 +234,31 @@ static const char *imx8mm_wrclk_sels[] =3D {"osc_24m"= , "sys_pll1_40m", "vpu_pll_ou "sys_pll1_266m", "sys_pll2_500m", "sys_pll1_100m", }; =20 static const char *imx8mm_dsi_core_sels[] =3D {"osc_24m", "sys_pll1_266m",= "sys_pll2_250m", "sys_pll1_800m", - "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_= out", }; + "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_o= ut", }; =20 static const char *imx8mm_dsi_phy_sels[] =3D {"osc_24m", "sys_pll2_125m", = "sys_pll2_100m", "sys_pll1_800m", - "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out",= }; + "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll_out", = }; =20 static const char *imx8mm_dsi_dbi_sels[] =3D {"osc_24m", "sys_pll1_266m", = "sys_pll2_100m", "sys_pll1_800m", - "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_o= ut", }; + "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_ou= t", }; =20 static const char *imx8mm_usdhc3_sels[] =3D {"osc_24m", "sys_pll1_400m", "= sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m"= , }; =20 static const char *imx8mm_csi1_core_sels[] =3D {"osc_24m", "sys_pll1_266m"= , "sys_pll2_250m", "sys_pll1_800m", - "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1= _out", }; + "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_= out", }; =20 static const char *imx8mm_csi1_phy_sels[] =3D {"osc_24m", "sys_pll2_333m",= "sys_pll2_100m", "sys_pll1_800m", - "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out"= , }; + "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll_out",= }; =20 static const char *imx8mm_csi1_esc_sels[] =3D {"osc_24m", "sys_pll2_100m",= "sys_pll1_80m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", = }; =20 static const char *imx8mm_csi2_core_sels[] =3D {"osc_24m", "sys_pll1_266m"= , "sys_pll2_250m", "sys_pll1_800m", - "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1= _out", }; + "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_= out", }; =20 static const char *imx8mm_csi2_phy_sels[] =3D {"osc_24m", "sys_pll2_333m",= "sys_pll2_100m", "sys_pll1_800m", - "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out"= , }; + "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll_out",= }; =20 static const char *imx8mm_csi2_esc_sels[] =3D {"osc_24m", "sys_pll2_100m",= "sys_pll1_80m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", = }; @@ -286,9 +286,9 @@ static const char *imx8mm_dram_core_sels[] =3D {"dram_p= ll_out", "dram_alt_root", } static const char *imx8mm_clko1_sels[] =3D {"osc_24m", "sys_pll1_800m", "d= ummy", "sys_pll1_200m", "audio_pll2_out", "sys_pll2_500m", "vpu_pll", "sys_pll1_80m", }; static const char *imx8mm_clko2_sels[] =3D {"osc_24m", "sys_pll2_200m", "s= ys_pll1_400m", "sys_pll2_166m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "osc_32k", }; + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "osc_32k", }; =20 -static const char * const clkout_sels[] =3D {"audio_pll1_out", "audio_pll2= _out", "video_pll1_out", +static const char * const clkout_sels[] =3D {"audio_pll1_out", "audio_pll2= _out", "video_pll_out", "dummy", "dummy", "gpu_pll_out", "vpu_pll_out", "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; @@ -327,7 +327,7 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) =20 hws[IMX8MM_AUDIO_PLL1_REF_SEL] =3D imx_clk_hw_mux("audio_pll1_ref_sel", b= ase + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MM_AUDIO_PLL2_REF_SEL] =3D imx_clk_hw_mux("audio_pll2_ref_sel", b= ase + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_VIDEO_PLL1_REF_SEL] =3D imx_clk_hw_mux("video_pll1_ref_sel", b= ase + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_VIDEO_PLL_REF_SEL] =3D imx_clk_hw_mux("video_pll_ref_sel", bas= e + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MM_DRAM_PLL_REF_SEL] =3D imx_clk_hw_mux("dram_pll_ref_sel", base = + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MM_GPU_PLL_REF_SEL] =3D imx_clk_hw_mux("gpu_pll_ref_sel", base + = 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MM_VPU_PLL_REF_SEL] =3D imx_clk_hw_mux("vpu_pll_ref_sel", base + = 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); @@ -336,7 +336,7 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) =20 hws[IMX8MM_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", base, &imx_1443x_pll); hws[IMX8MM_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", base + 0x14, &imx_1443x_pll); - hws[IMX8MM_VIDEO_PLL1] =3D imx_clk_hw_pll14xx("video_pll1", "video_pll1_r= ef_sel", base + 0x28, &imx_1443x_pll); + hws[IMX8MM_VIDEO_PLL] =3D imx_clk_hw_pll14xx("video_pll", "video_pll_ref_= sel", base + 0x28, &imx_1443x_pll); hws[IMX8MM_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", base + 0x50, &imx_1443x_dram_pll); hws[IMX8MM_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = base + 0x64, &imx_1416x_pll); hws[IMX8MM_VPU_PLL] =3D imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", = base + 0x74, &imx_1416x_pll); @@ -348,7 +348,7 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) /* PLL bypass out */ hws[IMX8MM_AUDIO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll1_bypass= ", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels),= CLK_SET_RATE_PARENT); hws[IMX8MM_AUDIO_PLL2_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll2_bypass= ", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass= _sels), CLK_SET_RATE_PARENT); - hws[IMX8MM_VIDEO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("video_pll1_bypass= ", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass= _sels), CLK_SET_RATE_PARENT); + hws[IMX8MM_VIDEO_PLL_BYPASS] =3D imx_clk_hw_mux_flags("video_pll_bypass",= base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sel= s), CLK_SET_RATE_PARENT); hws[IMX8MM_DRAM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("dram_pll_bypass", b= ase + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), = CLK_SET_RATE_PARENT); hws[IMX8MM_GPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("gpu_pll_bypass", bas= e + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_= SET_RATE_PARENT); hws[IMX8MM_VPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("vpu_pll_bypass", bas= e + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_= SET_RATE_PARENT); @@ -358,7 +358,7 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) /* PLL out gate */ hws[IMX8MM_AUDIO_PLL1_OUT] =3D imx_clk_hw_gate("audio_pll1_out", "audio_p= ll1_bypass", base, 13); hws[IMX8MM_AUDIO_PLL2_OUT] =3D imx_clk_hw_gate("audio_pll2_out", "audio_p= ll2_bypass", base + 0x14, 13); - hws[IMX8MM_VIDEO_PLL1_OUT] =3D imx_clk_hw_gate("video_pll1_out", "video_p= ll1_bypass", base + 0x28, 13); + hws[IMX8MM_VIDEO_PLL_OUT] =3D imx_clk_hw_gate("video_pll_out", "video_pll= _bypass", base + 0x28, 13); hws[IMX8MM_DRAM_PLL_OUT] =3D imx_clk_hw_gate("dram_pll_out", "dram_pll_by= pass", base + 0x50, 13); hws[IMX8MM_GPU_PLL_OUT] =3D imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypas= s", base + 0x64, 11); hws[IMX8MM_VPU_PLL_OUT] =3D imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypas= s", base + 0x74, 11); --=20 2.43.0 From nobody Sun May 10 07:14:10 2026 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55D8C1F8686 for ; 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:29 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Krzysztof Kozlowski , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 03/23] dt-bindings: clock: imx8mp: add VIDEO_PLL clocks Date: Fri, 27 Dec 2024 17:56:06 +0100 Message-ID: <20241227165719.3902388-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the name used in the RM is video_pll. So, let's add the IMX8MP_VIDEO_PLL[_*] definitions to be consistent with the RM and avoid misunderstandings. The IMX8MP_VIDEO_PLL1* constants have not been removed to ensure backward compatibility of the patch. No functional changes intended. Signed-off-by: Dario Binacchi Acked-by: Krzysztof Kozlowski --- (no changes since v6) Changes in v6: - Add 'Acked-by' tag of Krzysztof Kozlowski Changes in v5: - New include/dt-bindings/clock/imx8mp-clock.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings= /clock/imx8mp-clock.h index 7da4243984b2..3235d7de3b62 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -16,7 +16,8 @@ #define IMX8MP_CLK_EXT4 7 #define IMX8MP_AUDIO_PLL1_REF_SEL 8 #define IMX8MP_AUDIO_PLL2_REF_SEL 9 -#define IMX8MP_VIDEO_PLL1_REF_SEL 10 +#define IMX8MP_VIDEO_PLL_REF_SEL 10 +#define IMX8MP_VIDEO_PLL1_REF_SEL IMX8MP_VIDEO_PLL_REF_SEL #define IMX8MP_DRAM_PLL_REF_SEL 11 #define IMX8MP_GPU_PLL_REF_SEL 12 #define IMX8MP_VPU_PLL_REF_SEL 13 @@ -26,7 +27,8 @@ #define IMX8MP_SYS_PLL3_REF_SEL 17 #define IMX8MP_AUDIO_PLL1 18 #define IMX8MP_AUDIO_PLL2 19 -#define IMX8MP_VIDEO_PLL1 20 +#define IMX8MP_VIDEO_PLL 20 +#define IMX8MP_VIDEO_PLL1 IMX8MP_VIDEO_PLL #define IMX8MP_DRAM_PLL 21 #define IMX8MP_GPU_PLL 22 #define IMX8MP_VPU_PLL 23 @@ -36,7 +38,8 @@ #define IMX8MP_SYS_PLL3 27 #define IMX8MP_AUDIO_PLL1_BYPASS 28 #define IMX8MP_AUDIO_PLL2_BYPASS 29 -#define IMX8MP_VIDEO_PLL1_BYPASS 30 +#define IMX8MP_VIDEO_PLL_BYPASS 30 +#define IMX8MP_VIDEO_PLL1_BYPASS IMX8MP_VIDEO_PLL_BYPASS #define IMX8MP_DRAM_PLL_BYPASS 31 #define IMX8MP_GPU_PLL_BYPASS 32 #define IMX8MP_VPU_PLL_BYPASS 33 @@ -46,7 +49,8 @@ #define IMX8MP_SYS_PLL3_BYPASS 37 #define IMX8MP_AUDIO_PLL1_OUT 38 #define IMX8MP_AUDIO_PLL2_OUT 39 -#define IMX8MP_VIDEO_PLL1_OUT 40 +#define IMX8MP_VIDEO_PLL_OUT 40 +#define IMX8MP_VIDEO_PLL1_OUT IMX8MP_VIDEO_PLL_OUT #define IMX8MP_DRAM_PLL_OUT 41 #define IMX8MP_GPU_PLL_OUT 42 #define IMX8MP_VPU_PLL_OUT 43 --=20 2.43.0 From nobody Sun May 10 07:14:10 2026 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA0CA1F869B for ; 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:30 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Peng Fan , Abel Vesa , Fabio Estevam , Michael Turquette , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 04/23] clk: imx8mp: rename video_pll1 to video_pll Date: Fri, 27 Dec 2024 17:56:07 +0100 Message-ID: <20241227165719.3902388-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the name used in the RM is video_pll. So, let's rename "video_pll1" to "video_pll" to be consistent with the RM and avoid misunderstandings. No functional changes intended. Signed-off-by: Dario Binacchi Reviewed-by: Peng Fan --- The patch, which simply replaces video_pll1 with video_pll, highlights many warnings raised by checkpatch.pl. These are not generated by the changes made but are inherited from how the module was originally written. Fixing them would have meant "obscuring" the actual changes introduced. Changes in v7: - Add 'Reviewed-by' tag of Peng Fan Changes in v5: - Split the patch dropping the dt-bindings changes. Changes in v4: - New drivers/clk/imx/clk-imx8mp.c | 118 +++++++++++++++++------------------ 1 file changed, 59 insertions(+), 59 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 516dbd170c8a..e96460534e7d 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -23,7 +23,7 @@ static u32 share_count_audio; static const char * const pll_ref_sels[] =3D { "osc_24m", "dummy", "dummy"= , "dummy", }; static const char * const audio_pll1_bypass_sels[] =3D {"audio_pll1", "aud= io_pll1_ref_sel", }; static const char * const audio_pll2_bypass_sels[] =3D {"audio_pll2", "aud= io_pll2_ref_sel", }; -static const char * const video_pll1_bypass_sels[] =3D {"video_pll1", "vid= eo_pll1_ref_sel", }; +static const char * const video_pll_bypass_sels[] =3D {"video_pll", "video= _pll_ref_sel", }; static const char * const dram_pll_bypass_sels[] =3D {"dram_pll", "dram_pl= l_ref_sel", }; static const char * const gpu_pll_bypass_sels[] =3D {"gpu_pll", "gpu_pll_r= ef_sel", }; static const char * const vpu_pll_bypass_sels[] =3D {"vpu_pll", "vpu_pll_r= ef_sel", }; @@ -40,27 +40,27 @@ static const char * const imx8mp_a53_core_sels[] =3D {"= arm_a53_div", "arm_pll_out" =20 static const char * const imx8mp_m7_sels[] =3D {"osc_24m", "sys_pll2_200m"= , "sys_pll2_250m", "vpu_pll_out", "sys_pll1_800m", "audio_pll1_out", - "video_pll1_out", "sys_pll3_out", }; + "video_pll_out", "sys_pll3_out", }; =20 static const char * const imx8mp_ml_sels[] =3D {"osc_24m", "gpu_pll_out", = "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_gpu3d_core_sels[] =3D {"osc_24m", "gpu_pl= l_out", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_gpu3d_shader_sels[] =3D {"osc_24m", "gpu_= pll_out", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_gpu2d_sels[] =3D {"osc_24m", "gpu_pll_out= ", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_audio_axi_sels[] =3D {"osc_24m", "gpu_pll= _out", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_hsio_axi_sels[] =3D {"osc_24m", "sys_pll2= _500m", "sys_pll1_800m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", @@ -72,11 +72,11 @@ static const char * const imx8mp_media_isp_sels[] =3D {= "osc_24m", "sys_pll2_1000m" =20 static const char * const imx8mp_main_axi_sels[] =3D {"osc_24m", "sys_pll2= _333m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "sys_pll1_100m",}; + "video_pll_out", "sys_pll1_100m",}; =20 static const char * const imx8mp_enet_axi_sels[] =3D {"osc_24m", "sys_pll1= _266m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", - "video_pll1_out", "sys_pll3_out", }; + "video_pll_out", "sys_pll3_out", }; =20 static const char * const imx8mp_nand_usdhc_sels[] =3D {"osc_24m", "sys_pl= l1_266m", "sys_pll1_800m", "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", @@ -96,35 +96,35 @@ static const char * const imx8mp_media_apb_sels[] =3D {= "osc_24m", "sys_pll2_125m", =20 static const char * const imx8mp_gpu_axi_sels[] =3D {"osc_24m", "sys_pll1_= 800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_gpu_ahb_sels[] =3D {"osc_24m", "sys_pll1_= 800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_noc_sels[] =3D {"osc_24m", "sys_pll1_800m= ", "sys_pll3_out", "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_noc_io_sels[] =3D {"osc_24m", "sys_pll1_8= 00m", "sys_pll3_out", "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_ml_axi_sels[] =3D {"osc_24m", "sys_pll1_8= 00m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_ml_ahb_sels[] =3D {"osc_24m", "sys_pll1_8= 00m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_ahb_sels[] =3D {"osc_24m", "sys_pll1_133m= ", "sys_pll1_800m", "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", - "audio_pll1_out", "video_pll1_out", }; + "audio_pll1_out", "video_pll_out", }; =20 static const char * const imx8mp_audio_ahb_sels[] =3D {"osc_24m", "sys_pll= 2_500m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out", - "audio_pll1_out", "video_pll1_out", }; + "audio_pll1_out", "video_pll_out", }; =20 static const char * const imx8mp_mipi_dsi_esc_rx_sels[] =3D {"osc_24m", "s= ys_pll2_100m", "sys_pll1_80m", "sys_pll1_800m", "sys_pll2_1000m", @@ -159,56 +159,56 @@ static const char * const imx8mp_pcie_aux_sels[] =3D = {"osc_24m", "sys_pll2_200m", "sys_pll1_160m", "sys_pll1_200m", }; =20 static const char * const imx8mp_i2c5_sels[] =3D {"osc_24m", "sys_pll1_160= m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mp_i2c6_sels[] =3D {"osc_24m", "sys_pll1_160= m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mp_sai1_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext1", "clk_ext2", }; =20 static const char * const imx8mp_sai2_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; =20 static const char * const imx8mp_sai3_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; =20 static const char * const imx8mp_sai5_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; =20 static const char * const imx8mp_sai6_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; =20 static const char * const imx8mp_enet_qos_sels[] =3D {"osc_24m", "sys_pll2= _125m", "sys_pll2_50m", "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", - "video_pll1_out", "clk_ext4", }; + "video_pll_out", "clk_ext4", }; =20 static const char * const imx8mp_enet_qos_timer_sels[] =3D {"osc_24m", "sy= s_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", "clk_ext3", - "clk_ext4", "video_pll1_out", }; + "clk_ext4", "video_pll_out", }; =20 static const char * const imx8mp_enet_ref_sels[] =3D {"osc_24m", "sys_pll2= _125m", "sys_pll2_50m", "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", - "video_pll1_out", "clk_ext4", }; + "video_pll_out", "clk_ext4", }; =20 static const char * const imx8mp_enet_timer_sels[] =3D {"osc_24m", "sys_pl= l2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", "clk_ext3", - "clk_ext4", "video_pll1_out", }; + "clk_ext4", "video_pll_out", }; =20 static const char * const imx8mp_enet_phy_ref_sels[] =3D {"osc_24m", "sys_= pll2_50m", "sys_pll2_125m", "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_nand_sels[] =3D {"osc_24m", "sys_pll2_500= m", "audio_pll1_out", "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out", - "sys_pll2_250m", "video_pll1_out", }; + "sys_pll2_250m", "video_pll_out", }; =20 static const char * const imx8mp_qspi_sels[] =3D {"osc_24m", "sys_pll1_400= m", "sys_pll2_333m", "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", @@ -223,19 +223,19 @@ static const char * const imx8mp_usdhc2_sels[] =3D {"= osc_24m", "sys_pll1_400m", "s "audio_pll2_out", "sys_pll1_100m", }; =20 static const char * const imx8mp_i2c1_sels[] =3D {"osc_24m", "sys_pll1_160= m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mp_i2c2_sels[] =3D {"osc_24m", "sys_pll1_160= m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mp_i2c3_sels[] =3D {"osc_24m", "sys_pll1_160= m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mp_i2c4_sels[] =3D {"osc_24m", "sys_pll1_160= m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mp_uart1_sels[] =3D {"osc_24m", "sys_pll1_80= m", "sys_pll2_200m", @@ -276,42 +276,42 @@ static const char * const imx8mp_ecspi2_sels[] =3D {"= osc_24m", "sys_pll2_200m", "s =20 static const char * const imx8mp_pwm1_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; =20 static const char * const imx8mp_pwm2_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; =20 static const char * const imx8mp_pwm3_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; =20 static const char * const imx8mp_pwm4_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; =20 static const char * const imx8mp_gpt1_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" }; =20 static const char * const imx8mp_gpt2_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext2" }; =20 static const char * const imx8mp_gpt3_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext3" }; =20 static const char * const imx8mp_gpt4_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" }; =20 static const char * const imx8mp_gpt5_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext2" }; =20 static const char * const imx8mp_gpt6_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext3" }; =20 static const char * const imx8mp_wdog_sels[] =3D {"osc_24m", "sys_pll1_133= m", "sys_pll1_160m", @@ -328,19 +328,19 @@ static const char * const imx8mp_ipp_do_clko1_sels[] = =3D {"osc_24m", "sys_pll1_800 =20 static const char * const imx8mp_ipp_do_clko2_sels[] =3D {"osc_24m", "sys_= pll2_200m", "sys_pll1_400m", "sys_pll1_166m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "osc_32k" }; + "video_pll_out", "osc_32k" }; =20 static const char * const imx8mp_hdmi_fdcc_tst_sels[] =3D {"osc_24m", "sys= _pll1_266m", "sys_pll2_250m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", - "audio_pll2_out", "video_pll1_out", }; + "audio_pll2_out", "video_pll_out", }; =20 static const char * const imx8mp_hdmi_24m_sels[] =3D {"osc_24m", "sys_pll1= _160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mp_hdmi_ref_266m_sels[] =3D {"osc_24m", "sys= _pll1_400m", "sys_pll3_out", "sys_pll2_333m", "sys_pll1_266m", "sys_pll2_200m", - "audio_pll1_out", "video_pll1_out", }; + "audio_pll1_out", "video_pll_out", }; =20 static const char * const imx8mp_usdhc3_sels[] =3D {"osc_24m", "sys_pll1_4= 00m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", @@ -349,26 +349,26 @@ static const char * const imx8mp_usdhc3_sels[] =3D {"= osc_24m", "sys_pll1_400m", "s static const char * const imx8mp_media_cam1_pix_sels[] =3D {"osc_24m", "sy= s_pll1_266m", "sys_pll2_250m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", - "video_pll1_out", }; + "video_pll_out", }; =20 static const char * const imx8mp_media_mipi_phy1_ref_sels[] =3D {"osc_24m"= , "sys_pll2_333m", "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", - "video_pll1_out", }; + "video_pll_out", }; =20 -static const char * const imx8mp_media_disp_pix_sels[] =3D {"osc_24m", "vi= deo_pll1_out", "audio_pll2_out", +static const char * const imx8mp_media_disp_pix_sels[] =3D {"osc_24m", "vi= deo_pll_out", "audio_pll2_out", "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", }; =20 static const char * const imx8mp_media_cam2_pix_sels[] =3D {"osc_24m", "sy= s_pll1_266m", "sys_pll2_250m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", - "video_pll1_out", }; + "video_pll_out", }; =20 static const char * const imx8mp_media_ldb_sels[] =3D {"osc_24m", "sys_pll= 2_333m", "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", - "video_pll1_out", }; + "video_pll_out", }; =20 static const char * const imx8mp_memrepair_sels[] =3D {"osc_24m", "sys_pll= 2_100m", "sys_pll1_80m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", @@ -392,12 +392,12 @@ static const char * const imx8mp_vpu_vc8000e_sels[] = =3D {"osc_24m", "vpu_pll_out", "sys_pll3_out", "audio_pll1_out", }; =20 static const char * const imx8mp_sai7_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; =20 static const char * const imx8mp_dram_core_sels[] =3D {"dram_pll_out", "dr= am_alt_root", }; =20 -static const char * const imx8mp_clkout_sels[] =3D {"audio_pll1_out", "aud= io_pll2_out", "video_pll1_out", +static const char * const imx8mp_clkout_sels[] =3D {"audio_pll1_out", "aud= io_pll2_out", "video_pll_out", "dummy", "dummy", "gpu_pll_out", "vpu_pll_out", "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; @@ -440,7 +440,7 @@ static int imx8mp_clocks_probe(struct platform_device *= pdev) =20 hws[IMX8MP_AUDIO_PLL1_REF_SEL] =3D imx_clk_hw_mux("audio_pll1_ref_sel", a= natop_base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MP_AUDIO_PLL2_REF_SEL] =3D imx_clk_hw_mux("audio_pll2_ref_sel", a= natop_base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MP_VIDEO_PLL1_REF_SEL] =3D imx_clk_hw_mux("video_pll1_ref_sel", a= natop_base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MP_VIDEO_PLL_REF_SEL] =3D imx_clk_hw_mux("video_pll_ref_sel", ana= top_base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MP_DRAM_PLL_REF_SEL] =3D imx_clk_hw_mux("dram_pll_ref_sel", anato= p_base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MP_GPU_PLL_REF_SEL] =3D imx_clk_hw_mux("gpu_pll_ref_sel", anatop_= base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MP_VPU_PLL_REF_SEL] =3D imx_clk_hw_mux("vpu_pll_ref_sel", anatop_= base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); @@ -451,7 +451,7 @@ static int imx8mp_clocks_probe(struct platform_device *= pdev) =20 hws[IMX8MP_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", anatop_base, &imx_1443x_pll); hws[IMX8MP_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", anatop_base + 0x14, &imx_1443x_pll); - hws[IMX8MP_VIDEO_PLL1] =3D imx_clk_hw_pll14xx("video_pll1", "video_pll1_r= ef_sel", anatop_base + 0x28, &imx_1443x_pll); + hws[IMX8MP_VIDEO_PLL] =3D imx_clk_hw_pll14xx("video_pll", "video_pll_ref_= sel", anatop_base + 0x28, &imx_1443x_pll); hws[IMX8MP_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", anatop_base + 0x50, &imx_1443x_dram_pll); hws[IMX8MP_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = anatop_base + 0x64, &imx_1416x_pll); hws[IMX8MP_VPU_PLL] =3D imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", = anatop_base + 0x74, &imx_1416x_pll); @@ -462,7 +462,7 @@ static int imx8mp_clocks_probe(struct platform_device *= pdev) =20 hws[IMX8MP_AUDIO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll1_bypass= ", anatop_base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass= _sels), CLK_SET_RATE_PARENT); hws[IMX8MP_AUDIO_PLL2_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll2_bypass= ", anatop_base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2= _bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MP_VIDEO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("video_pll1_bypass= ", anatop_base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1= _bypass_sels), CLK_SET_RATE_PARENT); + hws[IMX8MP_VIDEO_PLL_BYPASS] =3D imx_clk_hw_mux_flags("video_pll_bypass",= anatop_base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_byp= ass_sels), CLK_SET_RATE_PARENT); hws[IMX8MP_DRAM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("dram_pll_bypass", a= natop_base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_= sels), CLK_SET_RATE_PARENT); hws[IMX8MP_GPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("gpu_pll_bypass", ana= top_base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels= ), CLK_SET_RATE_PARENT); hws[IMX8MP_VPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("vpu_pll_bypass", ana= top_base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels= ), CLK_SET_RATE_PARENT); @@ -473,7 +473,7 @@ static int imx8mp_clocks_probe(struct platform_device *= pdev) =20 hws[IMX8MP_AUDIO_PLL1_OUT] =3D imx_clk_hw_gate("audio_pll1_out", "audio_p= ll1_bypass", anatop_base, 13); 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:32 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Krzysztof Kozlowski , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 05/23] dt-bindings: clock: imx8m-anatop: add oscillators and PLLs Date: Fri, 27 Dec 2024 17:56:08 +0100 Message-ID: <20241227165719.3902388-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Though adding clocks and clock-names properties will break the ABI, it is required to accurately describe the hardware. Indeed, the anatop module uses the input oscillators to generate various PLLs. In turn, the Clock Control Module (CCM) receives clocks from the PLLs and oscillators and generates clocks for on-chip peripherals. Furthermore, as agreed in [1], this change represents the first step toward the implementation of the anatop driver. Currently, in fact, there is no dedicated anatop driver, but the CCM driver parses the anatop node and registers the PLLs it produces. [1] https://lore.kernel.org/imx/20241106090549.3684963-1-dario.binacchi@ama= rulasolutions.com/ Signed-off-by: Dario Binacchi Reviewed-by: Krzysztof Kozlowski --- Changes in v7: - Add 'Reviewed-by' tag of Krzysztof Kozlowski Changes in v6: - Improve commit message - Merge it with patch 10, 11, and 12: - 10/20 dt-bindings: clock: imx8mm: add binding definitions for anatop - 11/20 dt-bindings: clock: imx8mn: add binding definitions for anatop - 12/20 dt-bindings: clock: imx8mp: add binding definitions for anatop Changes in v4: - New .../bindings/clock/fsl,imx8m-anatop.yaml | 53 ++++++++++++++- include/dt-bindings/clock/imx8mm-clock.h | 64 +++++++++++++++++ include/dt-bindings/clock/imx8mn-clock.h | 64 +++++++++++++++++ include/dt-bindings/clock/imx8mp-clock.h | 68 +++++++++++++++++++ 4 files changed, 248 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml = b/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml index bbd22e95b319..f439b0a94ce2 100644 --- a/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml +++ b/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml @@ -30,22 +30,73 @@ properties: interrupts: maxItems: 1 =20 + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + maxItems: 3 + '#clock-cells': const: 1 =20 required: - compatible - reg + - clocks + - clock-names - '#clock-cells' =20 +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx8mq-anatop + then: + properties: + clocks: + items: + - description: 32k osc + - description: 25m osc + - description: 27m osc + clock-names: + items: + - const: ckil + - const: osc_25m + - const: osc_27m + else: + properties: + clocks: + items: + - description: 32k osc + - description: 24m osc + + clock-names: + items: + - const: osc_32k + - const: osc_24m + additionalProperties: false =20 examples: - | - anatop: clock-controller@30360000 { + clock-controller@30360000 { compatible =3D "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; reg =3D <0x30360000 0x10000>; #clock-cells =3D <1>; + clocks =3D <&osc_32k>, <&osc_24m>; + clock-names =3D "osc_32k", "osc_24m"; + }; + + - | + clock-controller@30360000 { + compatible =3D "fsl,imx8mq-anatop"; + reg =3D <0x30360000 0x10000>; + #clock-cells =3D <1>; + clocks =3D <&ckil>, <&osc_25m>, <&osc_27m>; + clock-names =3D "ckil", "osc_25m", "osc_27m"; }; =20 ... diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings= /clock/imx8mm-clock.h index 102d8a6cdb55..017c06e48430 100644 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -287,4 +287,68 @@ =20 #define IMX8MM_CLK_END 258 =20 +#define IMX8MM_ANATOP_CLK_DUMMY 0 +#define IMX8MM_ANATOP_CLK_32K 1 +#define IMX8MM_ANATOP_CLK_24M 2 +#define IMX8MM_ANATOP_AUDIO_PLL1_REF_SEL 3 +#define IMX8MM_ANATOP_AUDIO_PLL2_REF_SEL 4 +#define IMX8MM_ANATOP_VIDEO_PLL_REF_SEL 5 +#define IMX8MM_ANATOP_DRAM_PLL_REF_SEL 6 +#define IMX8MM_ANATOP_GPU_PLL_REF_SEL 7 +#define IMX8MM_ANATOP_VPU_PLL_REF_SEL 8 +#define IMX8MM_ANATOP_ARM_PLL_REF_SEL 9 +#define IMX8MM_ANATOP_SYS_PLL3_REF_SEL 10 +#define IMX8MM_ANATOP_AUDIO_PLL1 11 +#define IMX8MM_ANATOP_AUDIO_PLL2 12 +#define IMX8MM_ANATOP_VIDEO_PLL 13 +#define IMX8MM_ANATOP_DRAM_PLL 14 +#define IMX8MM_ANATOP_GPU_PLL 15 +#define IMX8MM_ANATOP_VPU_PLL 16 +#define IMX8MM_ANATOP_ARM_PLL 17 +#define IMX8MM_ANATOP_SYS_PLL1 18 +#define IMX8MM_ANATOP_SYS_PLL2 19 +#define IMX8MM_ANATOP_SYS_PLL3 20 +#define IMX8MM_ANATOP_AUDIO_PLL1_BYPASS 21 +#define IMX8MM_ANATOP_AUDIO_PLL2_BYPASS 22 +#define IMX8MM_ANATOP_VIDEO_PLL_BYPASS 23 +#define IMX8MM_ANATOP_DRAM_PLL_BYPASS 24 +#define IMX8MM_ANATOP_GPU_PLL_BYPASS 25 +#define IMX8MM_ANATOP_VPU_PLL_BYPASS 26 +#define IMX8MM_ANATOP_ARM_PLL_BYPASS 27 +#define IMX8MM_ANATOP_SYS_PLL3_BYPASS 28 +#define IMX8MM_ANATOP_AUDIO_PLL1_OUT 29 +#define IMX8MM_ANATOP_AUDIO_PLL2_OUT 30 +#define IMX8MM_ANATOP_VIDEO_PLL_OUT 31 +#define IMX8MM_ANATOP_DRAM_PLL_OUT 32 +#define IMX8MM_ANATOP_GPU_PLL_OUT 33 +#define IMX8MM_ANATOP_VPU_PLL_OUT 34 +#define IMX8MM_ANATOP_ARM_PLL_OUT 35 +#define IMX8MM_ANATOP_SYS_PLL3_OUT 36 +#define IMX8MM_ANATOP_SYS_PLL1_OUT 37 +#define IMX8MM_ANATOP_SYS_PLL1_40M 38 +#define IMX8MM_ANATOP_SYS_PLL1_80M 39 +#define IMX8MM_ANATOP_SYS_PLL1_100M 40 +#define IMX8MM_ANATOP_SYS_PLL1_133M 41 +#define IMX8MM_ANATOP_SYS_PLL1_160M 42 +#define IMX8MM_ANATOP_SYS_PLL1_200M 43 +#define IMX8MM_ANATOP_SYS_PLL1_266M 44 +#define IMX8MM_ANATOP_SYS_PLL1_400M 45 +#define IMX8MM_ANATOP_SYS_PLL1_800M 46 +#define IMX8MM_ANATOP_SYS_PLL2_OUT 47 +#define IMX8MM_ANATOP_SYS_PLL2_50M 48 +#define IMX8MM_ANATOP_SYS_PLL2_100M 49 +#define IMX8MM_ANATOP_SYS_PLL2_125M 50 +#define IMX8MM_ANATOP_SYS_PLL2_166M 51 +#define IMX8MM_ANATOP_SYS_PLL2_200M 52 +#define IMX8MM_ANATOP_SYS_PLL2_250M 53 +#define IMX8MM_ANATOP_SYS_PLL2_333M 54 +#define IMX8MM_ANATOP_SYS_PLL2_500M 55 +#define IMX8MM_ANATOP_SYS_PLL2_1000M 56 +#define IMX8MM_ANATOP_CLK_CLKOUT1_SEL 57 +#define IMX8MM_ANATOP_CLK_CLKOUT1_DIV 58 +#define IMX8MM_ANATOP_CLK_CLKOUT1 59 +#define IMX8MM_ANATOP_CLK_CLKOUT2_SEL 60 +#define IMX8MM_ANATOP_CLK_CLKOUT2_DIV 61 +#define IMX8MM_ANATOP_CLK_CLKOUT2 62 + #endif diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings= /clock/imx8mn-clock.h index 04809edab33c..b2fa73803d45 100644 --- a/include/dt-bindings/clock/imx8mn-clock.h +++ b/include/dt-bindings/clock/imx8mn-clock.h @@ -267,4 +267,68 @@ =20 #define IMX8MN_CLK_END 235 =20 +#define IMX8MN_ANATOP_CLK_DUMMY 0 +#define IMX8MN_ANATOP_CLK_32K 1 +#define IMX8MN_ANATOP_CLK_24M 2 +#define IMX8MN_ANATOP_AUDIO_PLL1_REF_SEL 3 +#define IMX8MN_ANATOP_AUDIO_PLL2_REF_SEL 4 +#define IMX8MN_ANATOP_VIDEO_PLL_REF_SEL 5 +#define IMX8MN_ANATOP_DRAM_PLL_REF_SEL 6 +#define IMX8MN_ANATOP_GPU_PLL_REF_SEL 7 +#define IMX8MN_ANATOP_M7_ALT_PLL_REF_SEL 8 +#define IMX8MN_ANATOP_ARM_PLL_REF_SEL 9 +#define IMX8MN_ANATOP_SYS_PLL3_REF_SEL 10 +#define IMX8MN_ANATOP_AUDIO_PLL1 11 +#define IMX8MN_ANATOP_AUDIO_PLL2 12 +#define IMX8MN_ANATOP_VIDEO_PLL 13 +#define IMX8MN_ANATOP_DRAM_PLL 14 +#define IMX8MN_ANATOP_GPU_PLL 15 +#define IMX8MN_ANATOP_M7_ALT_PLL 16 +#define IMX8MN_ANATOP_ARM_PLL 17 +#define IMX8MN_ANATOP_SYS_PLL1 18 +#define IMX8MN_ANATOP_SYS_PLL2 19 +#define IMX8MN_ANATOP_SYS_PLL3 20 +#define IMX8MN_ANATOP_AUDIO_PLL1_BYPASS 21 +#define IMX8MN_ANATOP_AUDIO_PLL2_BYPASS 22 +#define IMX8MN_ANATOP_VIDEO_PLL_BYPASS 23 +#define IMX8MN_ANATOP_DRAM_PLL_BYPASS 24 +#define IMX8MN_ANATOP_GPU_PLL_BYPASS 25 +#define IMX8MN_ANATOP_M7_ALT_PLL_BYPASS 26 +#define IMX8MN_ANATOP_ARM_PLL_BYPASS 27 +#define IMX8MN_ANATOP_SYS_PLL3_BYPASS 28 +#define IMX8MN_ANATOP_AUDIO_PLL1_OUT 29 +#define IMX8MN_ANATOP_AUDIO_PLL2_OUT 30 +#define IMX8MN_ANATOP_VIDEO_PLL_OUT 31 +#define IMX8MN_ANATOP_DRAM_PLL_OUT 32 +#define IMX8MN_ANATOP_GPU_PLL_OUT 33 +#define IMX8MN_ANATOP_M7_ALT_PLL_OUT 34 +#define IMX8MN_ANATOP_ARM_PLL_OUT 35 +#define IMX8MN_ANATOP_SYS_PLL3_OUT 36 +#define IMX8MN_ANATOP_SYS_PLL1_OUT 37 +#define IMX8MN_ANATOP_SYS_PLL1_40M 38 +#define IMX8MN_ANATOP_SYS_PLL1_80M 39 +#define IMX8MN_ANATOP_SYS_PLL1_100M 40 +#define IMX8MN_ANATOP_SYS_PLL1_133M 41 +#define IMX8MN_ANATOP_SYS_PLL1_160M 42 +#define IMX8MN_ANATOP_SYS_PLL1_200M 43 +#define IMX8MN_ANATOP_SYS_PLL1_266M 44 +#define IMX8MN_ANATOP_SYS_PLL1_400M 45 +#define IMX8MN_ANATOP_SYS_PLL1_800M 46 +#define IMX8MN_ANATOP_SYS_PLL2_OUT 47 +#define IMX8MN_ANATOP_SYS_PLL2_50M 48 +#define IMX8MN_ANATOP_SYS_PLL2_100M 49 +#define IMX8MN_ANATOP_SYS_PLL2_125M 50 +#define IMX8MN_ANATOP_SYS_PLL2_166M 51 +#define IMX8MN_ANATOP_SYS_PLL2_200M 52 +#define IMX8MN_ANATOP_SYS_PLL2_250M 53 +#define IMX8MN_ANATOP_SYS_PLL2_333M 54 +#define IMX8MN_ANATOP_SYS_PLL2_500M 55 +#define IMX8MN_ANATOP_SYS_PLL2_1000M 56 +#define IMX8MN_ANATOP_CLK_CLKOUT1_SEL 57 +#define IMX8MN_ANATOP_CLK_CLKOUT1_DIV 58 +#define IMX8MN_ANATOP_CLK_CLKOUT1 59 +#define IMX8MN_ANATOP_CLK_CLKOUT2_SEL 60 +#define IMX8MN_ANATOP_CLK_CLKOUT2_DIV 61 +#define IMX8MN_ANATOP_CLK_CLKOUT2 62 + #endif diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings= /clock/imx8mp-clock.h index 3235d7de3b62..8c076225fd9e 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -402,4 +402,72 @@ =20 #define IMX8MP_CLK_AUDIOMIX_END 59 =20 +#define IMX8MP_ANATOP_CLK_DUMMY 0 +#define IMX8MP_ANATOP_CLK_24M 1 +#define IMX8MP_ANATOP_CLK_32K 2 +#define IMX8MP_ANATOP_AUDIO_PLL1_REF_SEL 3 +#define IMX8MP_ANATOP_AUDIO_PLL2_REF_SEL 4 +#define IMX8MP_ANATOP_VIDEO_PLL_REF_SEL 5 +#define IMX8MP_ANATOP_DRAM_PLL_REF_SEL 6 +#define IMX8MP_ANATOP_GPU_PLL_REF_SEL 7 +#define IMX8MP_ANATOP_VPU_PLL_REF_SEL 8 +#define IMX8MP_ANATOP_ARM_PLL_REF_SEL 9 +#define IMX8MP_ANATOP_SYS_PLL1_REF_SEL 10 +#define IMX8MP_ANATOP_SYS_PLL2_REF_SEL 11 +#define IMX8MP_ANATOP_SYS_PLL3_REF_SEL 12 +#define IMX8MP_ANATOP_AUDIO_PLL1 13 +#define IMX8MP_ANATOP_AUDIO_PLL2 14 +#define IMX8MP_ANATOP_VIDEO_PLL 15 +#define IMX8MP_ANATOP_DRAM_PLL 16 +#define IMX8MP_ANATOP_GPU_PLL 17 +#define IMX8MP_ANATOP_VPU_PLL 18 +#define IMX8MP_ANATOP_ARM_PLL 19 +#define IMX8MP_ANATOP_SYS_PLL1 20 +#define IMX8MP_ANATOP_SYS_PLL2 21 +#define IMX8MP_ANATOP_SYS_PLL3 22 +#define IMX8MP_ANATOP_AUDIO_PLL1_BYPASS 23 +#define IMX8MP_ANATOP_AUDIO_PLL2_BYPASS 24 +#define IMX8MP_ANATOP_VIDEO_PLL_BYPASS 25 +#define IMX8MP_ANATOP_DRAM_PLL_BYPASS 26 +#define IMX8MP_ANATOP_GPU_PLL_BYPASS 27 +#define IMX8MP_ANATOP_VPU_PLL_BYPASS 28 +#define IMX8MP_ANATOP_ARM_PLL_BYPASS 29 +#define IMX8MP_ANATOP_SYS_PLL1_BYPASS 30 +#define IMX8MP_ANATOP_SYS_PLL2_BYPASS 31 +#define IMX8MP_ANATOP_SYS_PLL3_BYPASS 32 +#define IMX8MP_ANATOP_AUDIO_PLL1_OUT 33 +#define IMX8MP_ANATOP_AUDIO_PLL2_OUT 34 +#define IMX8MP_ANATOP_VIDEO_PLL_OUT 35 +#define IMX8MP_ANATOP_DRAM_PLL_OUT 36 +#define IMX8MP_ANATOP_GPU_PLL_OUT 37 +#define IMX8MP_ANATOP_VPU_PLL_OUT 38 +#define IMX8MP_ANATOP_ARM_PLL_OUT 39 +#define IMX8MP_ANATOP_SYS_PLL3_OUT 40 +#define IMX8MP_ANATOP_SYS_PLL1_OUT 41 +#define IMX8MP_ANATOP_SYS_PLL1_40M 42 +#define IMX8MP_ANATOP_SYS_PLL1_80M 43 +#define IMX8MP_ANATOP_SYS_PLL1_100M 44 +#define IMX8MP_ANATOP_SYS_PLL1_133M 45 +#define IMX8MP_ANATOP_SYS_PLL1_160M 46 +#define IMX8MP_ANATOP_SYS_PLL1_200M 47 +#define IMX8MP_ANATOP_SYS_PLL1_266M 48 +#define IMX8MP_ANATOP_SYS_PLL1_400M 49 +#define IMX8MP_ANATOP_SYS_PLL1_800M 50 +#define IMX8MP_ANATOP_SYS_PLL2_OUT 51 +#define IMX8MP_ANATOP_SYS_PLL2_50M 52 +#define IMX8MP_ANATOP_SYS_PLL2_100M 53 +#define IMX8MP_ANATOP_SYS_PLL2_125M 54 +#define IMX8MP_ANATOP_SYS_PLL2_166M 55 +#define IMX8MP_ANATOP_SYS_PLL2_200M 56 +#define IMX8MP_ANATOP_SYS_PLL2_250M 57 +#define IMX8MP_ANATOP_SYS_PLL2_333M 58 +#define IMX8MP_ANATOP_SYS_PLL2_500M 59 +#define IMX8MP_ANATOP_SYS_PLL2_1000M 60 +#define IMX8MP_ANATOP_CLK_CLKOUT1_SEL 61 +#define IMX8MP_ANATOP_CLK_CLKOUT1_DIV 62 +#define IMX8MP_ANATOP_CLK_CLKOUT1 63 +#define IMX8MP_ANATOP_CLK_CLKOUT2_SEL 64 +#define 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:33 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 06/23] arm64: dts: imx8mm: add anatop clocks Date: Fri, 27 Dec 2024 17:56:09 +0100 Message-ID: <20241227165719.3902388-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add clocks to anatop node. Add the bindings definitions for the anatop node. The patch is preparatory for future developments. Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - New arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mm.dtsi index 4de3bf22902b..597041a05073 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -600,6 +600,8 @@ anatop: clock-controller@30360000 { compatible =3D "fsl,imx8mm-anatop"; reg =3D <0x30360000 0x10000>; #clock-cells =3D <1>; + clocks =3D <&osc_32k>, <&osc_24m>; + clock-names =3D "osc_32k", "osc_24m"; }; =20 snvs: snvs@30370000 { --=20 2.43.0 From nobody Sun May 10 07:14:10 2026 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C04F1F8AC7 for ; Fri, 27 Dec 2024 16:57:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318659; cv=none; b=gZiKmTqBzTxIsE6XZrIuZp3kIeDUupUj2KwE7gzGxJiIuYfxiwX9GGmjQ4nwkdCU8JE48PCOJiiQ0/U5bDjsA8phLqil8dzdFOJ7kAMS45yA4c2GvFM+H4r33V5o7NQVnXsMmRZNp1zcrf/6RPUoYAcWP89vxjpNk90VSVR+xTE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318659; c=relaxed/simple; bh=MWwhsP/1Gq2jtC+XMH/+PSmlpfJmY2R2gm9uwDR4fZI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IBb2pZwqY6hBBgRFGsmfbKjDQHY/TjFK4J3w6llt4OJSC3volMQpMNnVHEhTjek8ggmwHI6zKubfWqp+YekJm6vPdc+NJarWoEF5oEgkE2bGciMlqzsSWaasZPM/rN+vHiXAPgM1Iz6ih73ft7KnsZhSJULuYO9FrSha7FOq3F0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=lf601sGQ; arc=none smtp.client-ip=209.85.218.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="lf601sGQ" Received: by mail-ej1-f48.google.com with SMTP id a640c23a62f3a-aae81f4fdc4so1058748066b.0 for ; Fri, 27 Dec 2024 08:57:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1735318655; x=1735923455; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Mr8rvSiMKhhr7+g2wBjSbr4ZapMlTY5YRIRH4XPzpek=; b=lf601sGQvfKtDPOpLGbzFH7tsck39Zp35vkK7Ty7Un1bewq+pFgMQjg0NQJZ/LPxbM hO95hKk4noKutqRmOYmjponoBUC6q0GD4HrKoTx496VhpUa1+O/T6t1tYnia433ih4vJ AtS3eGCP7ZNdK7VUscE4cNuZQKObdXxU3rzE8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735318655; x=1735923455; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Mr8rvSiMKhhr7+g2wBjSbr4ZapMlTY5YRIRH4XPzpek=; b=PR62fLRPLFXyYfiDY/zKaOkpi1RVR8Jsqv/7jcOmV9a+uvR/B3my+czj33kEqd4Hx2 01NzsBD13sQyCH4gQ8a15GnDHHaRZVGast27XhdaktX+W+qcC/Q4a0nuD3mZFEYEaNo7 umojCHmY3s+FSLMh1em0+qQApMd7gjHoraE3bO5pLK8+87aP4Tgpq45kDWPUj4gFO168 jERM9L8rwq27GqGCehSALK/wpAhovN3W7sv87Is2TbP1EB0BN8za5h1ChX1pMNeNezG0 WAlU6xW7ymNzF8l2WkZ0as4hlHT5+iSE7OS0apUX8XiP44y/06Mz9zGm+4fbdvePjkIO LZuA== X-Gm-Message-State: AOJu0YyNUX5PXmW0gYC4JZdq46EPkqbIxB3PkkTE7tZdq4rMeHuufvZk Zt1BfMn2Rd5JZ5ugroQOoBfZ1GZ2MdKBFmdkPMlTt14XwXI2hkAaSzZloOVl+S20A6ouOfDEX2f R X-Gm-Gg: ASbGnctwrkh2gLSS2S+3AxdrptuC8ykP47XchWTZ47Bfe0r8KmFuaX8bMBN+Dt6chhT Hcog6ipY0XrfoaxNUgj89IwuereKEqykP1k/EBOooKj7NVX0mpdS1QFbWXYLfmXP7r3/Ye5B6VO Wd+O+Ys1sSSlHirhAaqw7aYXsucRb0li/jBsah6Ajdb4WMEDZyWlMbDqULVujQ6Ywoa0AYDxuYt 65Kh14uUEvAgoEszqVCBytbpk3NAhL1YQeJJiD3DMhvyNwfnimbAqyJKEhkdIElO/Ho4CXgCWZT QfmJS9HK0Q74gpuwZF/lnw== X-Google-Smtp-Source: AGHT+IE0OOORdYEPfw3l5TavUkTwemsNNoEqAVu6kBH4Ag8emI9J3IoeOvq1nphdPOb5Rod0D0CmkQ== X-Received: by 2002:a17:907:d9f:b0:aac:619:7ed8 with SMTP id a640c23a62f3a-aac28748b30mr2647750766b.7.1735318655550; Fri, 27 Dec 2024 08:57:35 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:35 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 07/23] arm64: dts: imx8mn: add anatop clocks Date: Fri, 27 Dec 2024 17:56:10 +0100 Message-ID: <20241227165719.3902388-8-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add clocks to anatop node. Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - New arch/arm64/boot/dts/freescale/imx8mn.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mn.dtsi index a5f9cfb46e5d..49be492b5687 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -606,6 +606,8 @@ anatop: clock-controller@30360000 { compatible =3D "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; reg =3D <0x30360000 0x10000>; #clock-cells =3D <1>; + clocks =3D <&osc_32k>, <&osc_24m>; + clock-names =3D "osc_32k", "osc_24m"; }; =20 snvs: snvs@30370000 { --=20 2.43.0 From nobody Sun May 10 07:14:10 2026 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8F361F8ADF for ; Fri, 27 Dec 2024 16:57:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318660; cv=none; b=oi1bKM0HIw2Uq7Pcl+KGKQacueYgRGgr/yi4IBHQSoW5DsVzI3XAiQPWOV9PpgH6OY+d0AymS1RJICMZQs2bX4gqAnTk1XfrcqJS6r8WEUxMmM+n1W9qguQCrA9kmIb9aIuIpKFTuvrbfDf/e7gRggDuWWwXSUzUdG8GHgWRje0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318660; c=relaxed/simple; bh=EfuJYR878rJ4Cw+YuO97nDjgeWj+F6WJVMj2hzhOd0Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=C6HupRhBH5EpV11JMoxQXs4y7+bHrWMB3G5L/9IiD9xxvWk/79WLhLTm3LglJLjkeZ/LIwHr95u+g3Nty/v8Fu4DVJ/YITcXwGkbayHomeEsyZFXthaPCU+XikMWtqTI1s/Iq42IeoRziboudOt5G8siertD1yvPioQTOYy9pMw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=LsWlJDwd; arc=none smtp.client-ip=209.85.218.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="LsWlJDwd" Received: by mail-ej1-f48.google.com with SMTP id a640c23a62f3a-aa689a37dd4so1083966866b.3 for ; Fri, 27 Dec 2024 08:57:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1735318657; x=1735923457; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JTseU8DWKtdHNNseUc2PJ1vcygpii+LlAX++fbmk+pc=; b=LsWlJDwdauQLdhr7odF0Ra0Qna6L11YP0kYKOG5KuHZ8BBTDTKK+xoi06Vq3vRayfG wEwIbhb/1VVnx/kP04J+RHe7a1IJ4jsgFyszVUX4PHl09NztjTwWMNywBL+w0Ct+Ckzj wib7RNzU06OLywHJ+XNC3TLEAci+OC/dvoTUQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735318657; x=1735923457; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JTseU8DWKtdHNNseUc2PJ1vcygpii+LlAX++fbmk+pc=; b=YyC7MbfpeCvCu+JPO9l3JYk2phJgMwrJmgrIp77v1wza09IVdlBzNqtypZDnWUB1qv CBSHEwusC+Ufp0lCrZWrBnlUaostY+uMuFmvtxHgxkiK/nEQKqy3peau2x++x2IbLZqu WSWeOKtc1NJgC/5ETwPejK3cIrSwNlPCYOFvx+/qCDvXwXXKTfSvXqx4JLxKQyAsNMKU pb0JgfMtUos4MSXUDjCrO4h6UbGbbBmIfz92CEqooOOJ4nEMaLh6I4VlnmreRmAprNPs /zTe+W769u1J445v/y10/dHxNtSo4PfrZ0sLpr5Q6rKDt2MUIiNsZ1QqHAHsYgNOd3O9 gmoA== X-Gm-Message-State: AOJu0YxAxV12Gx9hUzwboReFS1zF2WCO+ila+WU/clu+liQF5w+MYW69 nfq2r/o6+g+wvkTh2iLaxhjCbMA4KGihQFyqItdhmXc9FNWWQIutsjC3fywTrDAhxJMkAlbeTPe V X-Gm-Gg: ASbGncsoplChBV4oeivCHUaNIVlWl2/iHCL/5fnmgzqDP4llhte98oiYC+AvpQfvCmH nJq/ekPW1kxbWtjbRBwZvDWG9vRbN0TJn51nz1BKvw1nhH7nAe1ofylIT/xv8LBerNn/NIhD/ZS aBsn6M9dJA4kP1QRlRq5rX2prSrXRYfG3whd/AJmDvcGGtbGv9Bh/2FTwHWUwPC1qY3I26dRycK MIJJkpzdFGmkZdFKmQ2cjRc/5YoUwfk0GirMG3cRfu9MT3aFAqFfhFwQJMaMCy68ZwIQlfGpaRa 5SewQ+luHqDadwdWCaeogQ== X-Google-Smtp-Source: AGHT+IHqEpKvPrvAcl6AfnqPR2zMpwbkTUBZZsaRlEKFV18gzQEhapMBi6kOkudHyHxl8CuL5KGNTg== X-Received: by 2002:a17:907:7f92:b0:aa6:a87e:f2e1 with SMTP id a640c23a62f3a-aac3378ef88mr2400967166b.56.1735318656917; Fri, 27 Dec 2024 08:57:36 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:36 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 08/23] arm64: dts: imx8mp: add anatop clocks Date: Fri, 27 Dec 2024 17:56:11 +0100 Message-ID: <20241227165719.3902388-9-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add clocks to anatop node. Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - New arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mp.dtsi index e0d3b8cba221..0b928e173f29 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -709,6 +709,8 @@ anatop: clock-controller@30360000 { compatible =3D "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; reg =3D <0x30360000 0x10000>; #clock-cells =3D <1>; + clocks =3D <&osc_32k>, <&osc_24m>; + clock-names =3D "osc_32k", "osc_24m"; }; =20 snvs: snvs@30370000 { --=20 2.43.0 From nobody Sun May 10 07:14:10 2026 Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1BDB01F8EE5 for ; Fri, 27 Dec 2024 16:57:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318661; cv=none; b=FslcGOv4i7Eunh5uot+uEMngY5fIFdEWl9Dm5Jn22LUCb7WN/QjZaeFlzMtedOWcJnuuan7RdQerwg1TNZWYdpeH5i2qE8PZlx2O+NVo9Qv44UDpctqN0n9vgzf2flzNoXoaTywnCFNlprOjx8JKyXSTDB97xW2+D/m4PaB8QkM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318661; c=relaxed/simple; bh=vc25/TFqvg0Ekr2Sm4G/VkkviBdPeMF5e7FdTWNCvAE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KrpEsHNqmEfH8dd7L1x93Bc3vakD5LeWwNwt9lVRmVt6rrHGfQvt+1WXMpYnkLtve0qw2dmVJAMpjbmJYYdXLf3P96WeaW/pHOEUbS9smwRkJuq6MMRLGefwhQeQvbYADJbFNlvD0UiJhsrhoNIe5H1Y2JDKwmfoMuZ2XtYcLhk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=IBd7yWXF; arc=none smtp.client-ip=209.85.208.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="IBd7yWXF" Received: by mail-ed1-f41.google.com with SMTP id 4fb4d7f45d1cf-5d7e3f1fc01so14462473a12.2 for ; Fri, 27 Dec 2024 08:57:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1735318658; x=1735923458; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BHj8xJJDjB/nn7+FV+WNgNcGZHPneQlK/63TZumKERk=; b=IBd7yWXFGuFditt3Uzdre40FRbTBNmOHk4TaDkIaLfKUq93Z1O+woVmoSDxSplFcJS aiG6Ud8qZl57tk4mERTKzhpqnUJk5HbbdJjEUKHQ9GMJWNr6glhCUfZRHpFt/EnqBWI7 mi0cRXlUhDu1NA1qcCXyCHXjLk84o9wyXjnHE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735318658; x=1735923458; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BHj8xJJDjB/nn7+FV+WNgNcGZHPneQlK/63TZumKERk=; b=PirLVlz1TnUV5ijqt2/B3GCYwp+vFKWLf60DGLXg4NDg080N2a+MDAHAznIhRETum1 QHx4mFckFmw9etTa4B0MchHSE4wQfrnsn7UTTY/xEXuk9CYDgy65SsqPyUHwLod8AyX2 NGvNUQC8Kb13i1bCihbJOcKcpm4mCCL0USPmUR4dzqnhqShsMjn+7Z/UjSm4wKJKrvlG DauT+dhOWLxPOmgwpoc8gN+jZwU2RZxn4p3884xA07228d5spc7rzK+hO96OKI6hqoEe PR+avqElR5g8VjZBQWsoxBc7XyMGXE0rsQC9Kg/Uldwwi5tzmgP8sl1gt4gTuni1IO0C RyZw== X-Gm-Message-State: AOJu0YxNn8UAJqcwiKLkzHwAP7ov2k6PZSGIuBXyR55X6dEKP6UBTMk7 M/jvBr7ChQDPUzqLQhnbghf+db8wfVDQkWAeYoceK2vHxlSueilweD1JtxtYsef/2Xhl7K2YUvY A X-Gm-Gg: ASbGnctsjPSEF1zXyVnV38MnUGokrH+UK466vw18M0Qqt7WZjrCKKSyYyh+IeudjJHR fA82m6Q3OMW2Ed9d2ZWuG2i/cluarRaaY6d0tl2NarRQyk19DhQiVAQCscky45HuYfUbwrUVk/e YSzBh0gUIMCYGhPdWi6010uauKFdrYeW0z4tMiC0W8QwxKIclAJGSlaUsSj/BAj9lTRJvrFghfB hLzVsw2ptmQpjZrqDyeN6MKwbDzJpwWKCpgAH0Yv8EJ9NAk+q+D+CLiIsyiXh7Yy5AFUxcSfGil WQ8LY6CeP2W29nTOylf2Rg== X-Google-Smtp-Source: AGHT+IEU39RTa9ECIPzQT71oAG8YXlNy7WaA4azCq4x0ZK+7kYxrqzuYsejzC7Lx7FeHEAwhQoFPPA== X-Received: by 2002:a05:6402:1ed3:b0:5d2:73b0:81ef with SMTP id 4fb4d7f45d1cf-5d81ddfdb67mr28928804a12.22.1735318658268; Fri, 27 Dec 2024 08:57:38 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:37 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 09/23] arm64: dts: imx8mq: add anatop clocks Date: Fri, 27 Dec 2024 17:56:12 +0100 Message-ID: <20241227165719.3902388-10-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add clocks to anatop node. Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - New arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mq.dtsi index d51de8d899b2..1d1424a136f0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -817,6 +817,8 @@ anatop: clock-controller@30360000 { reg =3D <0x30360000 0x10000>; interrupts =3D ; #clock-cells =3D <1>; + clocks =3D <&ckil>, <&osc_25m>, <&osc_27m>; + clock-names =3D "ckil", "osc_25m", "osc_27m"; }; =20 snvs: snvs@30370000 { --=20 2.43.0 From nobody Sun May 10 07:14:10 2026 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93CBD1F8F0D for ; Fri, 27 Dec 2024 16:57:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318663; cv=none; b=Q/zBXUZCDQuth/jtlAMMCUDDG4G2qwlZdtxIsawPJJKLYcU5xrqwwDuFnmuxqPMTPfPfWP7qeHIh4usy30ySSwFvW1zlU740LsV8Bn4ay8ZcXmQNsSwPhy/mF/P52PvALDBwBUOhlPyYK4VbrUDsGqAFp+WmG4hHlp2y3U0EVAc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318663; c=relaxed/simple; bh=naoomUt0k88+wEV17B2ZOe7lNdxVn1y0MUvtBQNmPnY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZlMT4p/2oLqz71mX+0wZ1MxDc6jP4wT4I/Ahc50AzblB4VUhyi2Zn0XGDjuAQC8dIFi8GgSq2z/zAGC3Tlk/V992083jvEYo+oP2TVIW6KrDqfftRZRB4oA7L8Fxm0GPgtiTHQvvc/BhblKXzzvaqClvlv1OBvBpNNlz1BuUsp4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=gtsa9nY4; arc=none smtp.client-ip=209.85.218.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="gtsa9nY4" Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-aaec111762bso914469266b.2 for ; Fri, 27 Dec 2024 08:57:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1735318660; x=1735923460; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EXkTXrVS+/nRJltLKdRuy9fqF8vJTsINCmAjWzhQ/Xw=; b=gtsa9nY4cxAyM7tJKBaT2Ai55BR4MCEDVA1/XAneh4oJInJXYwp6DwO1YTU/puo5Y+ ySwbBSmrr0CBI4DwGskwK9JUR1zg2bBeFi6NhzYSou0e7DI1tM7Omhp9mO+JqU3kSi0c nVEoke9n/lljBckMARBmds5dFNWbND3B9Q0cY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735318660; x=1735923460; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EXkTXrVS+/nRJltLKdRuy9fqF8vJTsINCmAjWzhQ/Xw=; b=J2VgXqEbu6p8UITGUhpN8C8AU3X8v0nrcyqrWc6/a0OzeyaployflCLywqD0mhyebC DNm791mkwtMf6pxmN2WWuUFLd4tJlF4dY/VaOGMUCZpscoG/CRDOz6dIGYbdQBGs4t+u ULprq/1+e4lRCDLDYV/2EMnfWgVdHdT8YfVVWdfzpbHkXkp0mNS/6tFi+NpejaAKaVym mjcp9jT+FFBwDrXpzuY+vwGxwUFHXpRm8YaGmbiCGEoi18uKn+1viR+NDs+vikNo31qV NxHyWF8mzC82HbS6+RdlwP52ytLEDDbdU0p82Mu3xBBFtkR1fF9vOZiir5WCj7CLMig9 jhiQ== X-Gm-Message-State: AOJu0Yw8kJuuUFX1B4SnwPIrQImTMZpj2dpIwPiZ94aJRAClwpL3Lzy8 WZvzydooa5VAiE2v/0PRr3Ume1qjGPKtjZ3eZx0euKH89yze/tWCXxK4YygTfO1f/QppBATQGAF Q X-Gm-Gg: ASbGncs2gU+CgQAo4aRDpoo1S4b+fGKGc1+4cifpHsKtoFbZM7IsNVSpIhT00sE3ykl L/jUdYbyIJQcwATiFpDkMmpWp6jOK5NEOGD/bfTOID2jylM7+RxM+7kD0F5+KFlz40z8kDd18tn CnWGCg8hfszrY9ctH7RyYWp3ATqbQnPpqDyVWYGGITQjw32S9Q49fUuR1cuMIg/MAUPcujIBErd uCwHsAtrDhkhuXU65OdMYdojWWRGIVP9nhYU85r+Z5HsyLxpqAEUylY+tD4eeLZ/NoJb3AS1BxZ hWyvnxHm76toxpXbM+OEfg== X-Google-Smtp-Source: AGHT+IGCaJDO5HxA1JrQ3trYq1mZgAVJbVh/QmApzDwyIdyVJeYbHjoW+NICkcizlG/u5obfXBOTOg== X-Received: by 2002:a17:907:3d86:b0:aa6:9eac:4b7e with SMTP id a640c23a62f3a-aac2d455458mr2795714566b.30.1735318659824; Fri, 27 Dec 2024 08:57:39 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:39 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 10/23] dt-bindings: clock: imx8m-clock: add phandle to the anatop Date: Fri, 27 Dec 2024 17:56:13 +0100 Message-ID: <20241227165719.3902388-11-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adding the phandle to the anatop node will break the ABI but will allow for a better description of the clock generation hardware, making the dependency of CCM on anatop explicit. Indeed, the CCM receives the PLLs generated by anatop as inputs, which, together with the oscillators, are used to generate the clocks for the on-chip peripherals. By doing this, it will also be possible to generalize the CCM driver code, which will no longer require the platform's compatible string to retrieve the anatop device node. Signed-off-by: Dario Binacchi --- Changes in v7: - New .../devicetree/bindings/clock/imx8m-clock.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml b/Doc= umentation/devicetree/bindings/clock/imx8m-clock.yaml index c643d4a81478..b23e639e6389 100644 --- a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml @@ -43,12 +43,20 @@ properties: ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m= -clock.h for the full list of i.MX8M clock IDs. =20 + fsl,anatop: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle to the anatop module that outputs the PLLs, which, + along with the oscillators, are used to generate the clocks for + the on-chip peripherals. + required: - compatible - reg - clocks - clock-names - '#clock-cells' + - fsl,anatop =20 allOf: - if: @@ -109,6 +117,7 @@ examples: <&clk_ext3>, <&clk_ext4>; clock-names =3D "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; + fsl,anatop =3D <&anatop>; }; =20 - | @@ -120,6 +129,7 @@ examples: <&clk_ext2>, <&clk_ext3>, <&clk_ext4>; clock-names =3D "ckil", "osc_25m", "osc_27m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; + fsl,anatop =3D <&anatop>; }; =20 ... --=20 2.43.0 From nobody Sun May 10 07:14:10 2026 Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72B591F9A8B for ; Fri, 27 Dec 2024 16:57:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318666; cv=none; b=QnsEv5iK8E53n+iD753OcFDIYpB2mAq4ytVnWcZ7vnHpWDnANmlJPYwDnHX9YmxPlPNigc0HBbbnT1P7aiprQ6TlczvE0SkQ4fygM1rjjRptzsp8K8rPsnAOylE78qEtne7lgQpsXiMV2gMmyifsd77R1RTnYMApiZpTx7UBjPY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318666; c=relaxed/simple; bh=VanAOZliSmRzy7jeQcKxNf50IVe/tzUMFdewwmrY7jA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NuF6EEAWiMoBPdcCZRvLKYVQXK4a5yWsppCd31N3xf+5gBtgYcOgE/TUhAbi/gyvKzRH24XFBY3Ne5I+1wLz1MCyZWOSwOtmRGIOJaw4NheZHrPbeE6aHyNqijrWy5ov1Uvm1SBCIgB+1XhbsMnupW4XO5Du/ThzJrKH17T52q8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=nVV91uBJ; arc=none smtp.client-ip=209.85.208.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="nVV91uBJ" Received: by mail-ed1-f53.google.com with SMTP id 4fb4d7f45d1cf-5d3d479b1e6so10059805a12.2 for ; Fri, 27 Dec 2024 08:57:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1735318663; x=1735923463; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2+Ol509AXN9QcKlnnsRu6lr9QP7BcBqQWxrtIjE7WLU=; b=nVV91uBJTbLGcDDYpJEFIXpv3FUjRqG+YKq39ACl+q9RAwAWYtlJVXnIDuObsuO4tj giFBevTd2K0Z9V58cR1zP6oSBaBTb+dqDt95XpcXf/PTv7sr0gL6ks6PAcL2264G7FAH ROa5mIxi98blz4zi4qWi2HNnu4kPyr6JXez4o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735318663; x=1735923463; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2+Ol509AXN9QcKlnnsRu6lr9QP7BcBqQWxrtIjE7WLU=; b=LZdu6wMsJtGS84LMbT5Cja6Io4GVxy+shpmMoAH281BnaZpd5jiST1e+oI1ePqblxG EYMgSKn4PPYlMD/0baxdaqQq1bLSjU9cCrAOdLAyUNMQMNOkFE36xSOAdTSLOERpBVRJ zx+8WPlDN0Rg8p03DkmBE5N9vwaVH7FXnCHLSerjg4RQN6bSA2FiBIlOSUBUCxV+Xa0i SeLRaR0QXu86c0v0l+jnqpJiNJC+Rent47yPz4NsBcTZSV+ycUrSvTRGVeQO7Ew6LZiI ETl6Tya2UR4w6/zcmTEHxY5VOZKcEO3Sx+kv1pqndzjqDlsIrORzsH6TyJg/yatymysi D90Q== X-Gm-Message-State: AOJu0YzB276qYpY10uKvjPX0QraHwxFVariP80sC8GKY2ICVYDuFtpcg IbDuCN6786aO6xyW0N8EGA0qd/46hnTM8FzwDMlh5HTHl7tB8Q2kWaPluXioJA8uRLYh0ip9Zv2 x X-Gm-Gg: ASbGncvVq8xD4lk/t1L7BFaouJPN98e9K/Blp4iNikf+5R35Ik2Ed1EhRD61gDLBRpY bU006MCF96/Qpqe8EZcqaOgYv3Lcm8qcd7Zpw2aYkVObShdgzxdxUdiojOkKjZGsLzD0OSmBp7d 9LcRE/2v8HSvuChXUVbKMHPDflJ8PlGY3OFNX70omtXRL9C+jBahtuUS4FLysRkUVUsPLxCicW2 KZX12aY8o1IeNjZIIynSUqLnJ37+k9tqXps8oYJ3x17CQliuKdFIym6xvva+Mze7rDLhM+x0YKf g63xcKufA9aj/EKhIa07aA== X-Google-Smtp-Source: AGHT+IGn15Euo6aKn+YqBtAxfzqKuDORdglC2oyMCv+ocfoAc484ttWncQyapARm20g2sBw1veFNrg== X-Received: by 2002:a05:6402:3206:b0:5d1:2377:5af3 with SMTP id 4fb4d7f45d1cf-5d81dd83b23mr61279573a12.5.1735318662742; Fri, 27 Dec 2024 08:57:42 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:41 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 11/23] arm64: dts: imx8mm: add phandle to anatop within CCM Date: Fri, 27 Dec 2024 17:56:14 +0100 Message-ID: <20241227165719.3902388-12-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the phandle to the anatop node within the CCM node. This makes explicit the dependency of CCM on anatop for generating the clocks for the on-chip peripherals. With this change, it will also be possible to generalize the CCM driver code, as it will no longer need the platform's compatible string to retrieve the anatop device node. Signed-off-by: Dario Binacchi --- Changes in v7: - New arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mm.dtsi index 597041a05073..b1a4cc521bf4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -645,6 +645,7 @@ clk: clock-controller@30380000 { <&clk_ext3>, <&clk_ext4>; clock-names =3D "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; + fsl,anatop =3D <&anatop>; assigned-clocks =3D <&clk IMX8MM_CLK_A53_SRC>, <&clk IMX8MM_CLK_A53_CORE>, <&clk IMX8MM_CLK_NOC>, --=20 2.43.0 From nobody Sun May 10 07:14:10 2026 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12A4A1F9AA1 for ; Fri, 27 Dec 2024 16:57:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318667; cv=none; b=uCjy5cScA5aK0hQI/AfCevKMnyYpNDtGoFixi0GZTeKbSaDxkQecBYlIo2rajOE/Z3s6GD2FMnKDBP8MrDQFLQLe3boj6Skx/IyNEj3Xh2XPZ9JjYY0z1QLQnxHNzN94Hrvs+oEAirhIZVUNkXQqnSZ0qVch78+WRfGYGWhNY0Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318667; c=relaxed/simple; bh=ki/DJ8Sz1UQ1qfcYAiqcjACcGQgLsaYpFgvc92kQuC8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tGWPsmIwB1mGosVgpb1IQ/qsi16wWbmqcR6Ig8HjI7DS5gjbMIOZSmfrsj358G+QA/urF79KdbNMUYM3Rv3RU8dFeRYWB4fNSRX06laadU7Iq9RQHqMnpzf5NsgQt7dvQQmnTypsOi4ONzRDg4D88OKRmmBQNkE/TE6LwfVvHiU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=Afwk0LMu; arc=none smtp.client-ip=209.85.218.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="Afwk0LMu" Received: by mail-ej1-f52.google.com with SMTP id a640c23a62f3a-aa67333f7d2so1092321766b.0 for ; Fri, 27 Dec 2024 08:57:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1735318664; x=1735923464; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=S3H13EAbQnYh5KL130M+yAXwGl0WzQAYvdh+BFvfpuk=; b=Afwk0LMutQaEaLxBJLGnPjHAts9csBNhb9rwo85h0zK50xNOaZUQO7+W5ZB8zD+Sn5 IaZAxTP3G7mv/7hli8LZcgEdHk3zWzAndzq315/xfCAuLWXKGWwXkvKp5NeNRwqydSyE y9MvEg3QIyFgIE+MREgAJddYaUL25KJsTB1tc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735318664; x=1735923464; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=S3H13EAbQnYh5KL130M+yAXwGl0WzQAYvdh+BFvfpuk=; b=Y3zfrQ8TMNb7caIR5PN8whSoYzyVyCJOIT3MBHGeFbDHtKG3r2zdt7ZK4ZPUSqxU64 TyURKsZ2CBr1Z+/onxHV894N/aN2ezErCqdJdDOo47NkKa8QPe+/jBFT+d10uaGorgLK mgz85UqmyW/S8tDU9E2TaVMzIMUYVk8RgfRqM9A42cHjMHtVz/JhYmSY6NbZ2qzhw0ty 77ze1OAU+/H7jCcL5S+/MC2q9Mwup00h7c5zk0q5zDMLV3IX4umKzip0P7a+C5v6IvHC F0JCujUR7hE4ybMhtXtqDkkzqdK927e1gMZmuiVk331UKYuGToD6H0t3q4pB1OaAcTjX VAng== X-Gm-Message-State: AOJu0Yxak/Bi0mOe+mnR5U3VtjqhTau0Zo1ufToV3ew5HRIlZDgrIhik iwxFr5+53HsAAj1CGfwZvmDxhe3qeCLe/PWtaupnRu4C1COz14XnJgLCt60IkumTx+AhUf+2NBl g X-Gm-Gg: ASbGncsuxE3GKqo7XNn13gcQ3b7lzRoBF3i55Z7tTnA7F09Z40+kyoSqHRXhTZmYNyk AHfRn3dQuWudgVx76CPavdZcv6AM2lV7Hp6vMYQ6lMNBSTPgnnxgiMkYoBaF24DRjjowlxKrlI8 P9e+YugK2wSOwHWJh1YUFTwiYmkw4GdgTSHAFZzNbiTy+rCm826lXNOb/vzek4ZDiMWWCniW6e7 3p4ekxTLpQ3DcRRK5B3fs+I5oenzklQopg+6L0DV/cvNojnOHKxXuY91zGZMo19rWQUx1bqSU+/ 8xBLi7aFumyaeJqFt9NyAw== X-Google-Smtp-Source: AGHT+IG0IOUDjXj7M8HLWY3rdlmEmUiO6k9aRVSVPoDq9wO9uWrUVEvcWB+pKuqU8J+AxzpC5sR7Iw== X-Received: by 2002:a17:907:3f12:b0:aa6:7220:f12f with SMTP id a640c23a62f3a-aac2ad8abccmr3008858366b.18.1735318664166; Fri, 27 Dec 2024 08:57:44 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:43 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 12/23] arm64: dts: imx8mn: add phandle to anatop within CCM Date: Fri, 27 Dec 2024 17:56:15 +0100 Message-ID: <20241227165719.3902388-13-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the phandle to the anatop node within the CCM node. This makes explicit the dependency of CCM on anatop for generating the clocks for the on-chip peripherals. With this change, it will also be possible to generalize the CCM driver code, as it will no longer need the platform's compatible string to retrieve the anatop device node. Signed-off-by: Dario Binacchi --- Changes in v7: - New arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mn.dtsi index 49be492b5687..68efa77535cb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -646,6 +646,7 @@ clk: clock-controller@30380000 { <&clk_ext3>, <&clk_ext4>; clock-names =3D "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; + fsl,anatop =3D <&anatop>; assigned-clocks =3D <&clk IMX8MN_CLK_A53_SRC>, <&clk IMX8MN_CLK_A53_CORE>, <&clk IMX8MN_CLK_NOC>, --=20 2.43.0 From nobody Sun May 10 07:14:10 2026 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5060B1F9AB3 for ; Fri, 27 Dec 2024 16:57:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318668; cv=none; b=uv/pasiVIibR4ejaMxe8vjSSD+NDADuBmz0jj4M+wBOzTp7/DqTwHlCcvAsSe9nmSPIJpPoZf7ggzYDwxGS6RqXdZaBq4ed5Wgs07SGrTSHUBJlea1sA76/AZ7+sVbBeuGtIIecco0rIaRKukkYa2F/HJygVP2JT7XqgKEPTX98= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318668; c=relaxed/simple; bh=yj5ENn5hd3kmikL4mIYyyYwweAh8ui9uop7PnQSXapw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=P9O+G5zFgoxfsTWTCaakGaHDllGZ8iy5p9+L2y4b6jU46nFN7y947+Sr9mn4Ya2izTHfCOXajncILEzKTthQc9XWXD2PILk1DCJVrZhuS23PQO9FFWjOhlNCvqSaxl2TJLi3QSCvI5jnYsH6S9UoeWec3+UV7n8h3rnanPipp2o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=RTBxdRLg; arc=none smtp.client-ip=209.85.218.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="RTBxdRLg" Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-aa6c0dbce1fso1034709066b.2 for ; Fri, 27 Dec 2024 08:57:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1735318665; x=1735923465; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=z/Q5xeJIoq5Ujssv/lVVpXyTtV/F6QlZNcPSL4YMIqE=; b=RTBxdRLgCf0RuLy3GvOV3hn4XDhzhIaVIJ8C7slqV59p2Jd+sUP3lJPopdxIbCkmuf gDx8RUGxbc4euVvGiASYnZqr2W1Hzz1FfTUedH0bfGr0LKNwpSmSSDhsuGkmEYd1hJHb Y7k78h9EaOzGdhD00Jl4jMp+6i6728lJvRm6w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735318665; x=1735923465; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z/Q5xeJIoq5Ujssv/lVVpXyTtV/F6QlZNcPSL4YMIqE=; b=bK2p3MX1smFS5m76EGK7oZ73YeiJLTWwWMe0y8Igy9QDOOekoQ9FVIyx8piAwdxVSR fT0t87u4R84rdcWEm+vM5qU/fJmY2LRcNVqyL8oRLcV/dYE2+QNj0wzJBeV83cEwkdAK qAja0tNUKVGzFL8EUY/d39sHpLLjWKA3Cnz+TKywJFUzB1cEakGsOcVDW0WfEAOqzO6Q iM9AZMjayXgnnSxxQWqFjwAOVMn8F12zYw9imZSDs+d8mzgU4zrLbN0pUyA1sS7MUGvM NImmXb+wIP3RZZBkXox7a1pL0NodHWoLC9JxSDJ/g0PCn6NCysilHDlpFfV1JsF0w86k COnQ== X-Gm-Message-State: AOJu0YzUIKeNd+FMb2cbgqjiSdh7RQg91HqyV3mn9SOTIX5f69T+ErQe vaqLqWqTohKGVwZZhbIRuEJoRNIqLE+FHccqsYjd/Zp644Ae0TnUxrteXDYpmFTfPs6OX8idPy1 F X-Gm-Gg: ASbGnct5zXM4j2wb6ig52AlKtwrRYNjAIVECW4mR4pSbgOl0zaKQGOWV2PH43XoPc5p 7w43KYJ0ann+U6y/2U5ITDLk0cEdzOfOrPYYVylend8M3kReYZuiKA/nyUeNGMxAq1WRKMG3M3L 7G9rp06l518s1XdRRo6JZ+y5Bigqg+lHNcjnCdCB1JMuRFHnk/mJ2jaScGhfCa5NmxGlQigq2Hr xJNC/IekoW3Hx0x+vOQueLtVDmaMNNHPOpjNwlp9Ewo7Gej6XHxuuNp6I9Sgrm9oKRp8ztD+hYU IqL+IJLtCoaP8RpyQ+RTGw== X-Google-Smtp-Source: AGHT+IG7WGJrOsb7TyGRh1ACx7FW71ZyfueLA84uEuZp9U5n20JO6c7QeCVbSZ/v+tRXVp6Smkf9tQ== X-Received: by 2002:a05:6402:2802:b0:5d3:cff5:635e with SMTP id 4fb4d7f45d1cf-5d81de065b8mr63355995a12.26.1735318665532; Fri, 27 Dec 2024 08:57:45 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:45 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 13/23] arm64: dts: imx8mp: add phandle to anatop within CCM Date: Fri, 27 Dec 2024 17:56:16 +0100 Message-ID: <20241227165719.3902388-14-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the phandle to the anatop node within the CCM node. This makes explicit the dependency of CCM on anatop for generating the clocks for the on-chip peripherals. With this change, it will also be possible to generalize the CCM driver code, as it will no longer need the platform's compatible string to retrieve the anatop device node. Signed-off-by: Dario Binacchi --- Changes in v7: - New arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mp.dtsi index 0b928e173f29..a1872b5d6e2e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -754,6 +754,7 @@ clk: clock-controller@30380000 { <&clk_ext3>, <&clk_ext4>; clock-names =3D "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; + fsl,anatop =3D <&anatop>; assigned-clocks =3D <&clk IMX8MP_CLK_A53_SRC>, <&clk IMX8MP_CLK_A53_CORE>, <&clk IMX8MP_CLK_NOC>, --=20 2.43.0 From nobody Sun May 10 07:14:10 2026 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B077D1F9EAD for ; Fri, 27 Dec 2024 16:57:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318670; cv=none; b=hu7/kUHTIZ6GsRVWFcCbWQiT2IHnZTUDbRHxmPqcMEhUOv1rKPuXzOV+coGaU/QC+RCsEpIRlYUKa5weZW9Jb4+PLbyyugBum8HyC9ypsVOQrRZirHt/iyFpFU2NMuupzUDSrNWTasBds2MyRZlvpofV9CCbe+mnQyair1SFuCI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318670; c=relaxed/simple; bh=iERCf4PSMgPb1a4YxNQInRCexMKauwehhCNuMMlVeNM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ti3PIXsbbz+riy/GqnYYSZcshDih/E7d9PExqlSsvXyVF1EaGdTSR1f7haTC2vaJMLU1HQAlY1yS37wA4F64wq5vXJEBbylZhfRcBrYYOBMi5KxqUU/pbdKcahCONYRajfkK9hzDxDtso3DDPDxSgd1o11lMHIjtzVgHwzOyRJU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=Nz+8vWX8; arc=none smtp.client-ip=209.85.218.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="Nz+8vWX8" Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-aa66e4d1d5aso1195252766b.2 for ; Fri, 27 Dec 2024 08:57:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1735318667; x=1735923467; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vOKJ3wQvbvnKfy50Gr8I3coc2Gwt+700w35xpJ+3wzM=; b=Nz+8vWX8cie7WMg3HjIFmOMCmVXhbHXAP2yheYDcEyIvDdFUMEft8loT0F5Lga+Jx7 COik2GPUscBwfaKVymyAs1/MwKqMhK6rcI19iUbYaGLm0bxb4VhCbDhoViEZq1FcbVJY Hwrud+ZC/clcXLre9NS1T+jw7BJZOJxfqvKRI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735318667; x=1735923467; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vOKJ3wQvbvnKfy50Gr8I3coc2Gwt+700w35xpJ+3wzM=; b=Mx1YhsXQJPDTaecYzdXUBZ71EWg8MkJs//2pptEzUl/yvsZG3rxh2pv4+chjtSslFx 62lA6B8Xl5WkAKVri4LywiFDOZUUbQT9HrUb9RLvF6mb9ZAQsuKjjhhYvcysnLl/67iS hWFQ7rpgrfzCGEMk6PirTODz+9UvnJQvclWE67C4gdV9EPQ3IxMyuvLbtI6+9bR+FV0W PlvPWYlBkisI5n6DOAQ67lb2s+JVCxTPWHHHcHH5vSi/08OZbaAK1BvTlOmUbes0TWcN taWUKa/5ctFjMMVIoITkloQ3UI4jdLpv9c6beI5XOBeVCW1rl4RN2LpNoyfBo1nF1fii BvSg== X-Gm-Message-State: AOJu0Yzim54sjZtVNLjiDFU7isST4/zdjthDfYvRPqiif4lwGMQKWlNH D/ml2RAE62qZS6TDKIjefygjXTSc7hkt87cfe9UqKh4RUuDxfbBDWI3lCGm+WYDueaXSVvwAm71 4 X-Gm-Gg: ASbGncvlOHQBzT03RdSugXA3B0/EOhyCtGgO4GYeSvJoBD6Qsj0B/0C49dq1+s1GDAN xpAJb3Gc9xA7uN0LWe4UwsulVOsGnHDAknlt955PAe2DJ3Py3LY8LAR1v8fYfTpoWpAQMicJgJQ zaIlHbJwe90aJhp4LNQ3LwqdFrYGWfQ1MgTlBRqI5m8vtzBL1ZoDTVCUH6dfCigSKDbndzr5h5s tZq3L4VxQydRQz/ul6CEHaSDO5MHcJDdG9Suzi5iQ7mil761IWN3vCaR5eAIdhDlM2NShE/2npW elzqTNh+EH6aEE3b8ZVDOQ== X-Google-Smtp-Source: AGHT+IGgrc+HQYxCKLo2SLlUL/mY7iziyIkQErGfzOsjT9xrluZfeOeDPohhXk9ai5VYtyng9jIdHA== X-Received: by 2002:a17:907:961f:b0:aa6:abe2:5cba with SMTP id a640c23a62f3a-aac27026cfemr2873979066b.2.1735318666969; Fri, 27 Dec 2024 08:57:46 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:46 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 14/23] arm64: dts: imx8mq: add phandle to anatop within CCM Date: Fri, 27 Dec 2024 17:56:17 +0100 Message-ID: <20241227165719.3902388-15-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the phandle to the anatop node within the CCM node. This makes explicit the dependency of CCM on anatop for generating the clocks for the on-chip peripherals. With this change, it will also be possible to generalize the CCM driver code, as it will no longer need the platform's compatible string to retrieve the anatop device node. Signed-off-by: Dario Binacchi --- Changes in v7: - New arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mq.dtsi index 1d1424a136f0..6f42e42e13e4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -859,6 +859,7 @@ clk: clock-controller@30380000 { clock-names =3D "ckil", "osc_25m", "osc_27m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; + fsl,anatop =3D <&anatop>; assigned-clocks =3D <&clk IMX8MQ_CLK_A53_SRC>, <&clk IMX8MQ_CLK_A53_CORE>, <&clk IMX8MQ_CLK_NOC>, --=20 2.43.0 From nobody Sun May 10 07:14:10 2026 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24CD11F9EDA for ; Fri, 27 Dec 2024 16:57:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318671; cv=none; b=JyOYoA9uu2tBP4TmAqI4oWXQfApN3t/J0MqvIVxub4OlWBpHpsu2pm7fB5GW31b/e4wdY3keqbvuRDOfCil7dekc9q+9jpYV2Z7XMqXyZYVw7IxbopXtmbPvS/gw9lniGVhqI1D3qPYDb4gsvV0hDLUUwzgyczPVQ0FsgKtuLZY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318671; c=relaxed/simple; bh=eGGs5xBoZ9eIk/QkKyhkODa3AXPAFwKHvMXYA4up2l4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WI+WS7nxIG8T3kJm73+Lb+FKOfbmvl89e5KBtBbjhFHNjOVo59DaYFPvzlN954C+/v6ejiOM0rFEuxDYgd6OA+JfYuHNTBKSQ+cid3SJX2tSmrqiNLZu80lpKDdsPI2rNEcQOyrrTk+jvybxSmHUr8RA3U72L8pxtVZufph2Zw4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=Oc3AoBpg; arc=none smtp.client-ip=209.85.218.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="Oc3AoBpg" Received: by mail-ej1-f51.google.com with SMTP id a640c23a62f3a-aa68b513abcso1420012166b.0 for ; Fri, 27 Dec 2024 08:57:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1735318668; x=1735923468; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2b1DvWsKR3kWK9JNfXRovoEHigCoxQCmQlYrGVfIyUo=; b=Oc3AoBpgeOMEPTyUxa0AFyb5UnHHFuorAJMiM1WzbwyQYadlUrpjp7frBM67J17Koy yEOLtPKQggh0m9UQ+agVUoabDAtAGWzNQG/B236WqcnxS+kEJCyVZk+3QkhlBpaa+AxJ IkVi7hhFPNzcdLV9CS2X8CiHUGHrkUiSTQEXA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735318668; x=1735923468; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2b1DvWsKR3kWK9JNfXRovoEHigCoxQCmQlYrGVfIyUo=; b=ug5hyMswny/e2LEmdkUafEgZsJ7wLP8CcsRDyJd/7rEN/yxLNqic4H1WVazuxSsMhD qrc5C17wPvRi2HoYLwZunNGHKUyxhDgapknEgxtnPmqBlzzLUT6k+pTyZw4/RESEDX8U R+Ajfpcl0d/IcG+VTBgzFJw/e7cVS3QtTvE3HNeAFNI38++sSrGQvfs+4XceR0woaOQj 4wlEQcxPU3ZGDN/utW3Ot4AgjGYAfp3gkdRtHMAW01JbXDxpjDI6JZtD52P+SSVwkIDp atIKYGDpOcIlHuw6hc7C2QTQSz7rJvC+RHbVALR+XCieyMaSH7RRbm2vJki5MunJiDuX cDkg== X-Gm-Message-State: AOJu0YziOMaht2aCFhLlSqm0VezjkgLiu27ky8brStKGglmhw56+pHVR 6UBQPjS+vp1KDIbRjtamJ9m+MbEWL5vtR99GPdbqHvIUxyvCr/X5oZIGoH7A7V8rlWI67y/8s1g z X-Gm-Gg: ASbGnctUbNTfd8U6FBvd64Q3HmBfEzkr5GgTyb6sBha4l5mgVhOTQ9PFj64W9zh0oFf BrkaY2YsKDtS/5cOC0SOqEjxoe1K+bP0a6I45PjaVWV1WGmDvPZq8IxmhEEzxiy3nVHxPO9Wyqf pgfMRHhZu/EleXCgfugKq3dISJ3z9wPShKWYFKvigO09MOGIMcVWj0OgnZtF1hydNnsCfYatNGo eknDX5UC5p/5jNtEl4nnZMr7NSBRupUpiEu59/bJGYyIvlBrNT5aE9diN+s/KDM7vQKZNFoUIR8 ySy34ItHMQAd65GVUyuK0w== X-Google-Smtp-Source: AGHT+IFdtsrBznelwwJuBM0+oIFuAtsVZztgwfPwBkxRjqySUJIDbs8HNHC7GQMygSlEz9WnVs+UvA== X-Received: by 2002:a17:907:704:b0:aac:23db:af61 with SMTP id a640c23a62f3a-aac2874937fmr2719500066b.3.1735318668380; Fri, 27 Dec 2024 08:57:48 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:48 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 15/23] clk: imx: add hw API imx_anatop_get_clk_hw Date: Fri, 27 Dec 2024 17:56:18 +0100 Message-ID: <20241227165719.3902388-16-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Get the hw of a clock registered by the anatop module. This function is preparatory for future developments. Signed-off-by: Dario Binacchi --- Changes in v7: - Add device_node type parameter to imx8m_anatop_get_clk_hw() - Rename imx8m_anatop_get_clk_hw() to imx_anatop_get_clk_hw() - Drop the gaurding macros so the code can be used also by i.MX9 Changes in v5: - Consider CONFIG_CLK_IMX8M{M,N,P,Q}_MODULE to fix compilation errors Changes in v4: - New drivers/clk/imx/clk.c | 15 +++++++++++++++ drivers/clk/imx/clk.h | 2 ++ 2 files changed, 17 insertions(+) diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c index df83bd939492..a906d3cd960b 100644 --- a/drivers/clk/imx/clk.c +++ b/drivers/clk/imx/clk.c @@ -128,6 +128,21 @@ struct clk_hw *imx_get_clk_hw_by_name(struct device_no= de *np, const char *name) } EXPORT_SYMBOL_GPL(imx_get_clk_hw_by_name); =20 +struct clk_hw *imx_anatop_get_clk_hw(struct device_node *np, int id) +{ + struct of_phandle_args args; + struct clk_hw *hw; + + args.np =3D np; + args.args_count =3D 1; + args.args[0] =3D id; + + hw =3D __clk_get_hw(of_clk_get_from_provider(&args)); + pr_debug("%s: got clk: %s\n", __func__, clk_hw_get_name(hw)); + return hw; +} +EXPORT_SYMBOL_GPL(imx_anatop_get_clk_hw); + /* * This fixups the register CCM_CSCMR1 write value. * The write/read/divider values of the aclk_podf field diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index aa5202f284f3..50e407cf48d9 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -487,4 +487,6 @@ struct clk_hw *imx_clk_gpr_mux(const char *name, const = char *compatible, u32 reg, const char **parent_names, u8 num_parents, const u32 *mux_table, u32 mask); =20 +struct clk_hw *imx_anatop_get_clk_hw(struct device_node *np, int id); + #endif --=20 2.43.0 From nobody Sun May 10 07:14:10 2026 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F08231F9ED0 for ; Fri, 27 Dec 2024 16:57:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:49 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 16/23] clk: imx: add support for i.MX8MN anatop clock driver Date: Fri, 27 Dec 2024 17:56:19 +0100 Message-ID: <20241227165719.3902388-17-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support NXP i.MX8M anatop PLL module which generates PLLs to CCM root. By doing so, we also simplify the CCM driver code. The changes are backward compatible. Signed-off-by: Dario Binacchi --- Changes in v7: - Update the code based on the changes made to the imx8m_anatop_get_clk_hw(): - Rename imx8m_anatop_get_clk_hw to imx_anatop_get_clk_hw - Add device_node type parameter - Call of_parse_phandle() to get the anatop's device node. Changes in v6: - Define IMX8MN_ANATOP_CLK_END inside the driver after it has ben removed from include/dt-bindings/clock/imx8mn-clock.h. Changes in v4: - New drivers/clk/imx/Makefile | 2 +- drivers/clk/imx/clk-imx8mn-anatop.c | 283 ++++++++++++++++++++++++++++ drivers/clk/imx/clk-imx8mn.c | 186 ++++++++---------- 3 files changed, 367 insertions(+), 104 deletions(-) create mode 100644 drivers/clk/imx/clk-imx8mn-anatop.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 03f2b2a1ab63..f0f1d01c68f8 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -26,7 +26,7 @@ mxc-clk-objs +=3D clk-gpr-mux.o obj-$(CONFIG_MXC_CLK) +=3D mxc-clk.o =20 obj-$(CONFIG_CLK_IMX8MM) +=3D clk-imx8mm.o -obj-$(CONFIG_CLK_IMX8MN) +=3D clk-imx8mn.o +obj-$(CONFIG_CLK_IMX8MN) +=3D clk-imx8mn-anatop.o clk-imx8mn.o obj-$(CONFIG_CLK_IMX8MP) +=3D clk-imx8mp.o clk-imx8mp-audiomix.o obj-$(CONFIG_CLK_IMX8MQ) +=3D clk-imx8mq.o =20 diff --git a/drivers/clk/imx/clk-imx8mn-anatop.c b/drivers/clk/imx/clk-imx8= mn-anatop.c new file mode 100644 index 000000000000..43101b0a758e --- /dev/null +++ b/drivers/clk/imx/clk-imx8mn-anatop.c @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * clk-imx8mn-anatop.c - NXP i.MX8MN anatop clock driver + * + * Copyright (c) 2022 Dario Binacchi + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#define IMX8MN_ANATOP_CLK_END IMX8MN_ANATOP_CLK_CLKOUT2 + +static const char * const pll_ref_sels[] =3D { "osc_24m", "dummy", "dummy"= , "dummy", }; +static const char * const audio_pll1_bypass_sels[] =3D {"audio_pll1", "aud= io_pll1_ref_sel", }; +static const char * const audio_pll2_bypass_sels[] =3D {"audio_pll2", "aud= io_pll2_ref_sel", }; +static const char * const video_pll_bypass_sels[] =3D {"video_pll", "video= _pll_ref_sel", }; +static const char * const dram_pll_bypass_sels[] =3D {"dram_pll", "dram_pl= l_ref_sel", }; +static const char * const gpu_pll_bypass_sels[] =3D {"gpu_pll", "gpu_pll_r= ef_sel", }; +static const char * const m7_alt_pll_bypass_sels[] =3D {"m7_alt_pll", "m7_= alt_pll_ref_sel", }; +static const char * const arm_pll_bypass_sels[] =3D {"arm_pll", "arm_pll_r= ef_sel", }; +static const char * const sys_pll3_bypass_sels[] =3D {"sys_pll3", "sys_pll= 3_ref_sel", }; +static const char * const clkout_sels[] =3D {"audio_pll1_out", "audio_pll2= _out", "video_pll_out", + "dummy", "dummy", "gpu_pll_out", "dummy", + "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", + "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; + +static struct clk_hw_onecell_data *clk_hw_data; +static struct clk_hw **hws; + +static int imx8mn_anatop_clocks_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + void __iomem *base; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) { + dev_err(dev, "failed to get base address\n"); + return PTR_ERR(base); + } + + clk_hw_data =3D devm_kzalloc(dev, struct_size(clk_hw_data, hws, + IMX8MN_ANATOP_CLK_END), + GFP_KERNEL); + if (WARN_ON(!clk_hw_data)) + return -ENOMEM; + + clk_hw_data->num =3D IMX8MN_ANATOP_CLK_END; + hws =3D clk_hw_data->hws; + + hws[IMX8MN_ANATOP_CLK_DUMMY] =3D imx_clk_hw_fixed("dummy", 0); + hws[IMX8MN_ANATOP_CLK_32K] =3D imx_get_clk_hw_by_name(np, "osc_32k"); + hws[IMX8MN_ANATOP_CLK_24M] =3D imx_get_clk_hw_by_name(np, "osc_24m"); + + hws[IMX8MN_ANATOP_AUDIO_PLL1_REF_SEL] =3D + imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_AUDIO_PLL2_REF_SEL] =3D + imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_VIDEO_PLL_REF_SEL] =3D + imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_DRAM_PLL_REF_SEL] =3D + imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_GPU_PLL_REF_SEL] =3D + imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_M7_ALT_PLL_REF_SEL] =3D + imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_ARM_PLL_REF_SEL] =3D + imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_SYS_PLL3_REF_SEL] =3D + imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + + hws[IMX8MN_ANATOP_AUDIO_PLL1] =3D + imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", + base, &imx_1443x_pll); + hws[IMX8MN_ANATOP_AUDIO_PLL2] =3D + imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", + base + 0x14, &imx_1443x_pll); + hws[IMX8MN_ANATOP_VIDEO_PLL] =3D + imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", + base + 0x28, &imx_1443x_pll); + hws[IMX8MN_ANATOP_DRAM_PLL] =3D + imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, + &imx_1443x_dram_pll); + hws[IMX8MN_ANATOP_GPU_PLL] =3D + imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, + &imx_1416x_pll); + hws[IMX8MN_ANATOP_M7_ALT_PLL] =3D + imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_ref_sel", + base + 0x74, &imx_1416x_pll); + hws[IMX8MN_ANATOP_ARM_PLL] =3D + imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, + &imx_1416x_pll); + hws[IMX8MN_ANATOP_SYS_PLL1] =3D imx_clk_hw_fixed("sys_pll1", 800000000); + hws[IMX8MN_ANATOP_SYS_PLL2] =3D imx_clk_hw_fixed("sys_pll2", 1000000000); + hws[IMX8MN_ANATOP_SYS_PLL3] =3D + imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, + &imx_1416x_pll); + + /* PLL bypass out */ + hws[IMX8MN_ANATOP_AUDIO_PLL1_BYPASS] =3D + imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, + audio_pll1_bypass_sels, + ARRAY_SIZE(audio_pll1_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_AUDIO_PLL2_BYPASS] =3D + imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, + audio_pll2_bypass_sels, + ARRAY_SIZE(audio_pll2_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_VIDEO_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1, + video_pll_bypass_sels, + ARRAY_SIZE(video_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_DRAM_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, + dram_pll_bypass_sels, + ARRAY_SIZE(dram_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_GPU_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, + gpu_pll_bypass_sels, + ARRAY_SIZE(gpu_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_M7_ALT_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("m7_alt_pll_bypass", base + 0x74, 28, 1, + m7_alt_pll_bypass_sels, + ARRAY_SIZE(m7_alt_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_ARM_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, + arm_pll_bypass_sels, + ARRAY_SIZE(arm_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_SYS_PLL3_BYPASS] =3D + imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, + sys_pll3_bypass_sels, + ARRAY_SIZE(sys_pll3_bypass_sels), + CLK_SET_RATE_PARENT); + + /* PLL out gate */ + hws[IMX8MN_ANATOP_AUDIO_PLL1_OUT] =3D + imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", + base, 13); + hws[IMX8MN_ANATOP_AUDIO_PLL2_OUT] =3D + imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", + base + 0x14, 13); + hws[IMX8MN_ANATOP_VIDEO_PLL_OUT] =3D + imx_clk_hw_gate("video_pll_out", "video_pll_bypass", + base + 0x28, 13); + hws[IMX8MN_ANATOP_DRAM_PLL_OUT] =3D + imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", + base + 0x50, 13); + hws[IMX8MN_ANATOP_GPU_PLL_OUT] =3D + imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", + base + 0x64, 11); + hws[IMX8MN_ANATOP_M7_ALT_PLL_OUT] =3D + imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_pll_bypass", + base + 0x74, 11); + hws[IMX8MN_ANATOP_ARM_PLL_OUT] =3D + imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", + base + 0x84, 11); + hws[IMX8MN_ANATOP_SYS_PLL3_OUT] =3D + imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", + base + 0x114, 11); + + /* SYS PLL1 fixed output */ + hws[IMX8MN_ANATOP_SYS_PLL1_OUT] =3D + imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11); + hws[IMX8MN_ANATOP_SYS_PLL1_40M] =3D + imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); + hws[IMX8MN_ANATOP_SYS_PLL1_80M] =3D + imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); + hws[IMX8MN_ANATOP_SYS_PLL1_100M] =3D + imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); + hws[IMX8MN_ANATOP_SYS_PLL1_133M] =3D + imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); + hws[IMX8MN_ANATOP_SYS_PLL1_160M] =3D + imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); + hws[IMX8MN_ANATOP_SYS_PLL1_200M] =3D + imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); + hws[IMX8MN_ANATOP_SYS_PLL1_266M] =3D + imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); + hws[IMX8MN_ANATOP_SYS_PLL1_400M] =3D + imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); + hws[IMX8MN_ANATOP_SYS_PLL1_800M] =3D + imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); + + /* SYS PLL2 fixed output */ + hws[IMX8MN_ANATOP_SYS_PLL2_OUT] =3D + imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11); + hws[IMX8MN_ANATOP_SYS_PLL2_50M] =3D + imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); + hws[IMX8MN_ANATOP_SYS_PLL2_100M] =3D + imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); + hws[IMX8MN_ANATOP_SYS_PLL2_125M] =3D + imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); + hws[IMX8MN_ANATOP_SYS_PLL2_166M] =3D + imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); + hws[IMX8MN_ANATOP_SYS_PLL2_200M] =3D + imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); + hws[IMX8MN_ANATOP_SYS_PLL2_250M] =3D + imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); + hws[IMX8MN_ANATOP_SYS_PLL2_333M] =3D + imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); + hws[IMX8MN_ANATOP_SYS_PLL2_500M] =3D + imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); + hws[IMX8MN_ANATOP_SYS_PLL2_1000M] =3D + imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); + + hws[IMX8MN_ANATOP_CLK_CLKOUT1_SEL] =3D + imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, + clkout_sels, ARRAY_SIZE(clkout_sels)); + hws[IMX8MN_ANATOP_CLK_CLKOUT1_DIV] =3D + imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, + 0, 4); + hws[IMX8MN_ANATOP_CLK_CLKOUT1] =3D + imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8); + hws[IMX8MN_ANATOP_CLK_CLKOUT2_SEL] =3D + imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4, + clkout_sels, ARRAY_SIZE(clkout_sels)); + hws[IMX8MN_ANATOP_CLK_CLKOUT2_DIV] =3D + imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, + 16, 4); + hws[IMX8MN_ANATOP_CLK_CLKOUT2] =3D + imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24); + + imx_check_clk_hws(hws, IMX8MN_ANATOP_CLK_END); + + ret =3D of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); + if (ret < 0) { + imx_unregister_hw_clocks(hws, IMX8MN_ANATOP_CLK_END); + return dev_err_probe(dev, ret, + "failed to register anatop clock provider\n"); + } + + dev_info(dev, "NXP i.MX8MN anatop clock driver probed\n"); + return 0; +} + +static const struct of_device_id imx8mn_anatop_clk_of_match[] =3D { + { .compatible =3D "fsl,imx8mn-anatop" }, + { /* Sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, imx8mn_anatop_clk_of_match); + +static struct platform_driver imx8mn_anatop_clk_driver =3D { + .probe =3D imx8mn_anatop_clocks_probe, + .driver =3D { + .name =3D "imx8mn-anatop", + /* + * Disable bind attributes: clocks are not removed and + * reloading the driver will crash or break devices. + */ + .suppress_bind_attrs =3D true, + .of_match_table =3D imx8mn_anatop_clk_of_match, + }, +}; + +module_platform_driver(imx8mn_anatop_clk_driver); + +MODULE_AUTHOR("Dario Binacchi "); +MODULE_DESCRIPTION("NXP i.MX8MN anatop clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index ab77e148e70c..984331372139 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -24,16 +24,6 @@ static u32 share_count_disp; static u32 share_count_pdm; static u32 share_count_nand; =20 -static const char * const pll_ref_sels[] =3D { "osc_24m", "dummy", "dummy"= , "dummy", }; -static const char * const audio_pll1_bypass_sels[] =3D {"audio_pll1", "aud= io_pll1_ref_sel", }; -static const char * const audio_pll2_bypass_sels[] =3D {"audio_pll2", "aud= io_pll2_ref_sel", }; -static const char * const video_pll_bypass_sels[] =3D {"video_pll", "video= _pll_ref_sel", }; -static const char * const dram_pll_bypass_sels[] =3D {"dram_pll", "dram_pl= l_ref_sel", }; -static const char * const gpu_pll_bypass_sels[] =3D {"gpu_pll", "gpu_pll_r= ef_sel", }; -static const char * const m7_alt_pll_bypass_sels[] =3D {"m7_alt_pll", "m7_= alt_pll_ref_sel", }; -static const char * const arm_pll_bypass_sels[] =3D {"arm_pll", "arm_pll_r= ef_sel", }; -static const char * const sys_pll3_bypass_sels[] =3D {"sys_pll3", "sys_pll= 3_ref_sel", }; - static const char * const imx8mn_a53_sels[] =3D {"osc_24m", "arm_pll_out",= "sys_pll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; @@ -308,21 +298,20 @@ static const char * const imx8mn_clko2_sels[] =3D {"o= sc_24m", "sys_pll2_200m", "sy "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", "osc_32k", }; =20 -static const char * const clkout_sels[] =3D {"audio_pll1_out", "audio_pll2= _out", "video_pll_out", - "dummy", "dummy", "gpu_pll_out", "dummy", - "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", - "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; - static struct clk_hw_onecell_data *clk_hw_data; static struct clk_hw **hws; =20 static int imx8mn_clocks_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; - struct device_node *np =3D dev->of_node; + struct device_node *np =3D dev->of_node, *anp; void __iomem *base; int ret; =20 + base =3D devm_platform_ioremap_resource(pdev, 0); + if (WARN_ON(IS_ERR(base))) + return PTR_ERR(base); + clk_hw_data =3D devm_kzalloc(dev, struct_size(clk_hw_data, hws, IMX8MN_CLK_END), GFP_KERNEL); if (WARN_ON(!clk_hw_data)) @@ -331,99 +320,93 @@ static int imx8mn_clocks_probe(struct platform_device= *pdev) clk_hw_data->num =3D IMX8MN_CLK_END; hws =3D clk_hw_data->hws; =20 - hws[IMX8MN_CLK_DUMMY] =3D imx_clk_hw_fixed("dummy", 0); - hws[IMX8MN_CLK_24M] =3D imx_get_clk_hw_by_name(np, "osc_24m"); - hws[IMX8MN_CLK_32K] =3D imx_get_clk_hw_by_name(np, "osc_32k"); + anp =3D of_parse_phandle(np, "fsl,anatop", 0); + if (!anp) { + anp =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop"); + if (!anp) + return dev_err_probe(dev, -ENODEV, "missing anatop\n"); + } + + of_node_put(anp); + + hws[IMX8MN_CLK_DUMMY] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_DU= MMY); + hws[IMX8MN_CLK_24M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_24M); + hws[IMX8MN_CLK_32K] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_32K); hws[IMX8MN_CLK_EXT1] =3D imx_get_clk_hw_by_name(np, "clk_ext1"); hws[IMX8MN_CLK_EXT2] =3D imx_get_clk_hw_by_name(np, "clk_ext2"); hws[IMX8MN_CLK_EXT3] =3D imx_get_clk_hw_by_name(np, "clk_ext3"); hws[IMX8MN_CLK_EXT4] =3D imx_get_clk_hw_by_name(np, "clk_ext4"); =20 - np =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop"); - base =3D devm_of_iomap(dev, np, 0, NULL); - of_node_put(np); - if (WARN_ON(IS_ERR(base))) { - ret =3D PTR_ERR(base); - goto unregister_hws; - } - - hws[IMX8MN_AUDIO_PLL1_REF_SEL] =3D imx_clk_hw_mux("audio_pll1_ref_sel", b= ase + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_AUDIO_PLL2_REF_SEL] =3D imx_clk_hw_mux("audio_pll2_ref_sel", b= ase + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_VIDEO_PLL_REF_SEL] =3D imx_clk_hw_mux("video_pll_ref_sel", bas= e + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_DRAM_PLL_REF_SEL] =3D imx_clk_hw_mux("dram_pll_ref_sel", base = + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_GPU_PLL_REF_SEL] =3D imx_clk_hw_mux("gpu_pll_ref_sel", base + = 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_M7_ALT_PLL_REF_SEL] =3D imx_clk_hw_mux("m7_alt_pll_ref_sel", b= ase + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_ARM_PLL_REF_SEL] =3D imx_clk_hw_mux("arm_pll_ref_sel", base + = 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_SYS_PLL3_REF_SEL] =3D imx_clk_hw_mux("sys_pll3_ref_sel", base = + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - - hws[IMX8MN_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", base, &imx_1443x_pll); - hws[IMX8MN_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", base + 0x14, &imx_1443x_pll); - hws[IMX8MN_VIDEO_PLL] =3D imx_clk_hw_pll14xx("video_pll", "video_pll_ref_= sel", base + 0x28, &imx_1443x_pll); - hws[IMX8MN_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", base + 0x50, &imx_1443x_dram_pll); - hws[IMX8MN_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = base + 0x64, &imx_1416x_pll); - hws[IMX8MN_M7_ALT_PLL] =3D imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_r= ef_sel", base + 0x74, &imx_1416x_pll); - hws[IMX8MN_ARM_PLL] =3D imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", = base + 0x84, &imx_1416x_pll); - hws[IMX8MN_SYS_PLL1] =3D imx_clk_hw_fixed("sys_pll1", 800000000); - hws[IMX8MN_SYS_PLL2] =3D imx_clk_hw_fixed("sys_pll2", 1000000000); - hws[IMX8MN_SYS_PLL3] =3D imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel= ", base + 0x114, &imx_1416x_pll); + hws[IMX8MN_AUDIO_PLL1_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANAT= OP_AUDIO_PLL1_REF_SEL); + hws[IMX8MN_AUDIO_PLL2_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANAT= OP_AUDIO_PLL2_REF_SEL); + hws[IMX8MN_VIDEO_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATO= P_VIDEO_PLL_REF_SEL); + hws[IMX8MN_DRAM_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP= _DRAM_PLL_REF_SEL); + hws[IMX8MN_GPU_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_= GPU_PLL_REF_SEL); + hws[IMX8MN_M7_ALT_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANAT= OP_M7_ALT_PLL_REF_SEL); + hws[IMX8MN_ARM_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_= ARM_PLL_REF_SEL); + hws[IMX8MN_SYS_PLL3_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP= _SYS_PLL3_REF_SEL); + + hws[IMX8MN_AUDIO_PLL1] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO= _PLL1); + hws[IMX8MN_AUDIO_PLL2] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO= _PLL2); + hws[IMX8MN_VIDEO_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VIDEO_= PLL); + hws[IMX8MN_DRAM_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRAM_PL= L); + hws[IMX8MN_GPU_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_PLL); + hws[IMX8MN_M7_ALT_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M7_AL= T_PLL); + hws[IMX8MN_ARM_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_PLL); + hws[IMX8MN_SYS_PLL1] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL= 1); + hws[IMX8MN_SYS_PLL2] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL= 2); + hws[IMX8MN_SYS_PLL3] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL= 3); =20 /* PLL bypass out */ - hws[IMX8MN_AUDIO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll1_bypass= ", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels),= CLK_SET_RATE_PARENT); - hws[IMX8MN_AUDIO_PLL2_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll2_bypass= ", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass= _sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_VIDEO_PLL_BYPASS] =3D imx_clk_hw_mux_flags("video_pll_bypass",= base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sel= s), CLK_SET_RATE_PARENT); - hws[IMX8MN_DRAM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("dram_pll_bypass", b= ase + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), = CLK_SET_RATE_PARENT); - hws[IMX8MN_GPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("gpu_pll_bypass", bas= e + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_= SET_RATE_PARENT); - hws[IMX8MN_M7_ALT_PLL_BYPASS] =3D imx_clk_hw_mux_flags("m7_alt_pll_bypass= ", base + 0x74, 28, 1, m7_alt_pll_bypass_sels, ARRAY_SIZE(m7_alt_pll_bypass= _sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_ARM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("arm_pll_bypass", bas= e + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_= SET_RATE_PARENT); - hws[IMX8MN_SYS_PLL3_BYPASS] =3D imx_clk_hw_mux_flags("sys_pll3_bypass", b= ase + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels),= CLK_SET_RATE_PARENT); + hws[IMX8MN_AUDIO_PLL1_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATO= P_AUDIO_PLL1_BYPASS); + hws[IMX8MN_AUDIO_PLL2_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATO= P_AUDIO_PLL2_BYPASS); + hws[IMX8MN_VIDEO_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP= _VIDEO_PLL_BYPASS); + hws[IMX8MN_DRAM_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_= DRAM_PLL_BYPASS); + hws[IMX8MN_GPU_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_G= PU_PLL_BYPASS); + hws[IMX8MN_M7_ALT_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATO= P_M7_ALT_PLL_BYPASS); + hws[IMX8MN_ARM_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_A= RM_PLL_BYPASS); + hws[IMX8MN_SYS_PLL3_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_= SYS_PLL3_BYPASS); =20 /* PLL out gate */ - hws[IMX8MN_AUDIO_PLL1_OUT] =3D imx_clk_hw_gate("audio_pll1_out", "audio_p= ll1_bypass", base, 13); - hws[IMX8MN_AUDIO_PLL2_OUT] =3D imx_clk_hw_gate("audio_pll2_out", "audio_p= ll2_bypass", base + 0x14, 13); - hws[IMX8MN_VIDEO_PLL_OUT] =3D imx_clk_hw_gate("video_pll_out", "video_pll= _bypass", base + 0x28, 13); - hws[IMX8MN_DRAM_PLL_OUT] =3D imx_clk_hw_gate("dram_pll_out", "dram_pll_by= pass", base + 0x50, 13); - hws[IMX8MN_GPU_PLL_OUT] =3D imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypas= s", base + 0x64, 11); - hws[IMX8MN_M7_ALT_PLL_OUT] =3D imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_= pll_bypass", base + 0x74, 11); - hws[IMX8MN_ARM_PLL_OUT] =3D imx_clk_hw_gate("arm_pll_out", "arm_pll_bypas= s", base + 0x84, 11); - hws[IMX8MN_SYS_PLL3_OUT] =3D imx_clk_hw_gate("sys_pll3_out", "sys_pll3_by= pass", base + 0x114, 11); + hws[IMX8MN_AUDIO_PLL1_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_A= UDIO_PLL1_OUT); + hws[IMX8MN_AUDIO_PLL2_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_A= UDIO_PLL2_OUT); + hws[IMX8MN_VIDEO_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VI= DEO_PLL_OUT); + hws[IMX8MN_DRAM_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRA= M_PLL_OUT); + hws[IMX8MN_GPU_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_= PLL_OUT); + hws[IMX8MN_M7_ALT_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M= 7_ALT_PLL_OUT); + hws[IMX8MN_ARM_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_= PLL_OUT); + hws[IMX8MN_SYS_PLL3_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS= _PLL3_OUT); =20 /* SYS PLL1 fixed output */ - hws[IMX8MN_SYS_PLL1_OUT] =3D imx_clk_hw_gate("sys_pll1_out", "sys_pll1", = base + 0x94, 11); - hws[IMX8MN_SYS_PLL1_40M] =3D imx_clk_hw_fixed_factor("sys_pll1_40m", "sys= _pll1_out", 1, 20); - hws[IMX8MN_SYS_PLL1_80M] =3D imx_clk_hw_fixed_factor("sys_pll1_80m", "sys= _pll1_out", 1, 10); - hws[IMX8MN_SYS_PLL1_100M] =3D imx_clk_hw_fixed_factor("sys_pll1_100m", "s= ys_pll1_out", 1, 8); - hws[IMX8MN_SYS_PLL1_133M] =3D imx_clk_hw_fixed_factor("sys_pll1_133m", "s= ys_pll1_out", 1, 6); - hws[IMX8MN_SYS_PLL1_160M] =3D imx_clk_hw_fixed_factor("sys_pll1_160m", "s= ys_pll1_out", 1, 5); - hws[IMX8MN_SYS_PLL1_200M] =3D imx_clk_hw_fixed_factor("sys_pll1_200m", "s= ys_pll1_out", 1, 4); - hws[IMX8MN_SYS_PLL1_266M] =3D imx_clk_hw_fixed_factor("sys_pll1_266m", "s= ys_pll1_out", 1, 3); - hws[IMX8MN_SYS_PLL1_400M] =3D imx_clk_hw_fixed_factor("sys_pll1_400m", "s= ys_pll1_out", 1, 2); - hws[IMX8MN_SYS_PLL1_800M] =3D imx_clk_hw_fixed_factor("sys_pll1_800m", "s= ys_pll1_out", 1, 1); + hws[IMX8MN_SYS_PLL1_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS= _PLL1_OUT); + hws[IMX8MN_SYS_PLL1_40M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS= _PLL1_40M); + hws[IMX8MN_SYS_PLL1_80M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS= _PLL1_80M); + hws[IMX8MN_SYS_PLL1_100M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL1_100M); + hws[IMX8MN_SYS_PLL1_133M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL1_133M); + hws[IMX8MN_SYS_PLL1_160M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL1_160M); + hws[IMX8MN_SYS_PLL1_200M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL1_200M); + hws[IMX8MN_SYS_PLL1_266M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL1_266M); + hws[IMX8MN_SYS_PLL1_400M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL1_400M); + hws[IMX8MN_SYS_PLL1_800M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL1_800M); =20 /* SYS PLL2 fixed output */ - hws[IMX8MN_SYS_PLL2_OUT] =3D imx_clk_hw_gate("sys_pll2_out", "sys_pll2", = base + 0x104, 11); - hws[IMX8MN_SYS_PLL2_50M] =3D imx_clk_hw_fixed_factor("sys_pll2_50m", "sys= _pll2_out", 1, 20); - hws[IMX8MN_SYS_PLL2_100M] =3D imx_clk_hw_fixed_factor("sys_pll2_100m", "s= ys_pll2_out", 1, 10); - hws[IMX8MN_SYS_PLL2_125M] =3D imx_clk_hw_fixed_factor("sys_pll2_125m", "s= ys_pll2_out", 1, 8); - hws[IMX8MN_SYS_PLL2_166M] =3D imx_clk_hw_fixed_factor("sys_pll2_166m", "s= ys_pll2_out", 1, 6); - hws[IMX8MN_SYS_PLL2_200M] =3D imx_clk_hw_fixed_factor("sys_pll2_200m", "s= ys_pll2_out", 1, 5); - hws[IMX8MN_SYS_PLL2_250M] =3D imx_clk_hw_fixed_factor("sys_pll2_250m", "s= ys_pll2_out", 1, 4); - hws[IMX8MN_SYS_PLL2_333M] =3D imx_clk_hw_fixed_factor("sys_pll2_333m", "s= ys_pll2_out", 1, 3); - hws[IMX8MN_SYS_PLL2_500M] =3D imx_clk_hw_fixed_factor("sys_pll2_500m", "s= ys_pll2_out", 1, 2); - hws[IMX8MN_SYS_PLL2_1000M] =3D imx_clk_hw_fixed_factor("sys_pll2_1000m", = "sys_pll2_out", 1, 1); - - hws[IMX8MN_CLK_CLKOUT1_SEL] =3D imx_clk_hw_mux2("clkout1_sel", base + 0x1= 28, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); - hws[IMX8MN_CLK_CLKOUT1_DIV] =3D imx_clk_hw_divider("clkout1_div", "clkout= 1_sel", base + 0x128, 0, 4); - hws[IMX8MN_CLK_CLKOUT1] =3D imx_clk_hw_gate("clkout1", "clkout1_div", bas= e + 0x128, 8); - hws[IMX8MN_CLK_CLKOUT2_SEL] =3D imx_clk_hw_mux2("clkout2_sel", base + 0x1= 28, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); - hws[IMX8MN_CLK_CLKOUT2_DIV] =3D imx_clk_hw_divider("clkout2_div", "clkout= 2_sel", base + 0x128, 16, 4); - hws[IMX8MN_CLK_CLKOUT2] =3D imx_clk_hw_gate("clkout2", "clkout2_div", bas= e + 0x128, 24); - - np =3D dev->of_node; - base =3D devm_platform_ioremap_resource(pdev, 0); - if (WARN_ON(IS_ERR(base))) { - ret =3D PTR_ERR(base); - goto unregister_hws; - } + hws[IMX8MN_SYS_PLL2_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS= _PLL2_OUT); + hws[IMX8MN_SYS_PLL2_50M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS= _PLL2_50M); + hws[IMX8MN_SYS_PLL2_100M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL2_100M); + hws[IMX8MN_SYS_PLL2_125M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL2_125M); + hws[IMX8MN_SYS_PLL2_166M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL2_166M); + hws[IMX8MN_SYS_PLL2_200M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL2_200M); + hws[IMX8MN_SYS_PLL2_250M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL2_250M); + hws[IMX8MN_SYS_PLL2_333M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL2_333M); + hws[IMX8MN_SYS_PLL2_500M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL2_500M); + hws[IMX8MN_SYS_PLL2_1000M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_S= YS_PLL2_1000M); + + hws[IMX8MN_CLK_CLKOUT1_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_= CLK_CLKOUT1_SEL); + hws[IMX8MN_CLK_CLKOUT1_DIV] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_= CLK_CLKOUT1_DIV); + hws[IMX8MN_CLK_CLKOUT1] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_= CLKOUT1); + hws[IMX8MN_CLK_CLKOUT2_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_= CLK_CLKOUT2_SEL); + hws[IMX8MN_CLK_CLKOUT2_DIV] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_= CLK_CLKOUT2_DIV); + hws[IMX8MN_CLK_CLKOUT2] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_= CLKOUT2); =20 /* CORE */ hws[IMX8MN_CLK_A53_DIV] =3D imx8m_clk_hw_composite_core("arm_a53_div", im= x8mn_a53_sels, base + 0x8000); @@ -599,18 +582,15 @@ static int imx8mn_clocks_probe(struct platform_device= *pdev) =20 ret =3D of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); if (ret < 0) { - dev_err(dev, "failed to register hws for i.MX8MN\n"); - goto unregister_hws; + imx_unregister_hw_clocks(hws, IMX8MN_CLK_END); + return dev_err_probe(dev, ret, + "failed to register hws for i.MX8MN\n"); } =20 imx_register_uart_clocks(); =20 + dev_info(dev, "NXP i.MX8MN ccm clock driver probed\n"); return 0; - -unregister_hws: - imx_unregister_hw_clocks(hws, IMX8MN_CLK_END); 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:51 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Krzysztof Kozlowski , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 17/23] dt-bindings: clock: imx8m-clock: add PLLs Date: Fri, 27 Dec 2024 17:56:20 +0100 Message-ID: <20241227165719.3902388-18-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Though adding the PLLs to clocks and clock-names properties will break the ABI, it is required to accurately describe the hardware. Indeed, the Clock Control Module (CCM) receives clocks from the PLLs and oscillators and generates clocks for on-chip peripherals. Signed-off-by: Dario Binacchi Reviewed-by: Krzysztof Kozlowski --- Changes in v7: - Add 'Reviewed-by' tag of Krzysztof Kozlowski Changes in v6: - New .../bindings/clock/imx8m-clock.yaml | 27 ++++++++++++++----- 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml b/Doc= umentation/devicetree/bindings/clock/imx8m-clock.yaml index b23e639e6389..eb2e6e702de9 100644 --- a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml @@ -29,12 +29,12 @@ properties: maxItems: 2 =20 clocks: - minItems: 6 - maxItems: 7 + minItems: 7 + maxItems: 10 =20 clock-names: - minItems: 6 - maxItems: 7 + minItems: 7 + maxItems: 10 =20 '#clock-cells': const: 1 @@ -94,6 +94,10 @@ allOf: - description: ext2 clock input - description: ext3 clock input - description: ext4 clock input + - description: audio1 PLL input + - description: audio2 PLL input + - description: dram PLL input + - description: video PLL input =20 clock-names: items: @@ -103,20 +107,31 @@ allOf: - const: clk_ext2 - const: clk_ext3 - const: clk_ext4 + - const: audio_pll1 + - const: audio_pll2 + - const: dram_pll + - const: video_pll =20 additionalProperties: false =20 examples: # Clock Control Module node: - | + #include + clock-controller@30380000 { compatible =3D "fsl,imx8mm-ccm"; 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:52 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 18/23] arm64: dts: imx8mm: add PLLs to clock controller module (CCM) Date: Fri, 27 Dec 2024 17:56:21 +0100 Message-ID: <20241227165719.3902388-19-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the PLLs generated by anatop to the clock list of the Clock Controller Module (CCM) node. Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - New arch/arm64/boot/dts/freescale/imx8mm.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mm.dtsi index b1a4cc521bf4..c3287978c42b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -642,9 +642,14 @@ clk: clock-controller@30380000 { ; #clock-cells =3D <1>; clocks =3D <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; + <&clk_ext3>, <&clk_ext4>, + <&anatop IMX8MM_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MM_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MM_ANATOP_DRAM_PLL>, + <&anatop IMX8MM_ANATOP_VIDEO_PLL>; clock-names =3D "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; + "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2", + "dram_pll", "video_pll"; fsl,anatop =3D <&anatop>; assigned-clocks =3D <&clk IMX8MM_CLK_A53_SRC>, <&clk IMX8MM_CLK_A53_CORE>, --=20 2.43.0 From nobody Sun May 10 07:14:10 2026 Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59FFB1FA15D for ; Fri, 27 Dec 2024 16:57:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318678; cv=none; b=dHqvp8lQI5+TwdPFRZx1Iq5uyFLX0gVFXPfXhXWJGk+PaWGlPlwzYy9KgFt18Tr49HN6S6GHxZs+6ExUVNJ0UOX2UOWI8/er9pwacvHsYgXwR0tTVlxuE/U4a3L8wGOQL1k3Pi+qEUABNDPzuYNfjiBwJLsl/8TkGMEYP7WJNFA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318678; c=relaxed/simple; bh=WPI2dIsyUP0LxzdhYGphrf43j1SUNHG0CnoAlIBpkLQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qjUCeh8kUDtBqUPiGsSWAiuM4TrjAXd3oUHOUZbDmE/SIAMz4n71MDp4C4fVn8iLZLhBJa0cspMuc5VsRK/x0SN77eGtbsC5B0yb39oc+dDLYmRNy5jcfMUVsijHeG+im1RA6otZa+V2fFmiUQwOtDzVqDiga8huEXwzOuHA3LY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=h/I3p7AA; arc=none smtp.client-ip=209.85.218.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="h/I3p7AA" Received: by mail-ej1-f41.google.com with SMTP id a640c23a62f3a-aa684b6d9c7so1281098566b.2 for ; Fri, 27 Dec 2024 08:57:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1735318674; x=1735923474; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Rq1VSi4sJPfcoFKtG/h420vGHkyV2FuPufBKEuYsW+8=; b=h/I3p7AAvERpOK7GXqcWjFqcstgLpmNOa/OXt3OZofKlvMloKEgBrXkvaHYprBkc4B dwTet/cIBW1hn01UJxVUumlZvCKXqFfDZMlDd82H6NcOCSKFJ9kCb66r10qDT8sIHFOC /Qn+k2RMi9grRT4smPaUWnCuoJsuM7qMhN98k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735318674; x=1735923474; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Rq1VSi4sJPfcoFKtG/h420vGHkyV2FuPufBKEuYsW+8=; b=sdGELt1bJyBE4Fl4McZOBuvnRkmPk8oTuGfAcXLMUHuD+2IIHr6haHCPIIShtOed7j pOVjvDmuoMfDatbKWJIyttmlyAM+/XeJUCXekHy9QMX5Fy4Ac8ALNJzPin0w/2oBngdl UAas+RmScTbaUqemTWZew1F6QdZQO7F/dzUfrvrQObEt9PLd/dEhEFVnMRSe6HuKd2+I tKNx11JDunzRh/GgddLcimf8DzJ9+0jcwcRcgd5Z/A8EZxVmrS35O4shI74kIjXqUJZr laeU/PWVmMEfG5cOvp59kkncbW8hx+tkvmQ4d1zC/2VANNnwBL1SU4zbPBoYlzJrru3j AfUw== X-Gm-Message-State: AOJu0Yx5m8CELixy9ixVBfP+BNGzr/ZI4DkR5yzjkEkum2IdFbaObZMo r5rCcQJZbWrDCdZqgm+M2KI0R7mPUcPdNieI+2YCxLs7BwAwIyl5m2Te0lp3++uKLt+eHJ8bmIM a X-Gm-Gg: ASbGncujW+T9qVUH/iBcy73NZgnujGwc0fY5gdZ4cp9JejAAAOLM845Xqnb0ruxFECr 0+qKbH+cKtBrOOEBfjRt813GBqNUSeamqQVNsFTGJux0IwjYNSk0f5V12vSoDpTqxZYzQTSwym/ DVWJd5BxJjO9+tO+2MCLhno7FHRfmzrEd31hiUiKpoHqGmTjPGPrOtEiuC7YKJrgqBxvj1hDo4r LCOeaF1tqypbtZdgE/0bbMUaxlSueuqfw1o/Is5k7iLLDxlRuYPRQkJNsMsEltfnEylrB/JaCsj MvYV8w8fXoOsI6nTUaxxvQ== X-Google-Smtp-Source: AGHT+IE7j4dDMSJzj4YF9TTof8Zod66BxHTVWnQ8MmtOChqL0trQDynsgYUTS5unrBlBn2AwqqLf3w== X-Received: by 2002:a17:907:940c:b0:aa6:82ea:69d6 with SMTP id a640c23a62f3a-aac2ad9e63dmr3011790766b.18.1735318674459; Fri, 27 Dec 2024 08:57:54 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:54 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 19/23] arm64: dts: imx8mn: add PLLs to clock controller module (CCM) Date: Fri, 27 Dec 2024 17:56:22 +0100 Message-ID: <20241227165719.3902388-20-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the PLLs generated by anatop to the clock list of the Clock Controller Module (CCM) node. Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - New arch/arm64/boot/dts/freescale/imx8mn.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mn.dtsi index 68efa77535cb..ef25c4a655ed 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -643,9 +643,14 @@ clk: clock-controller@30380000 { ; #clock-cells =3D <1>; clocks =3D <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; + <&clk_ext3>, <&clk_ext4>, + <&anatop IMX8MN_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MN_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MN_ANATOP_DRAM_PLL>, + <&anatop IMX8MN_ANATOP_VIDEO_PLL>; clock-names =3D "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; + "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2", + "dram_pll", "video_pll"; fsl,anatop =3D <&anatop>; assigned-clocks =3D <&clk IMX8MN_CLK_A53_SRC>, <&clk IMX8MN_CLK_A53_CORE>, --=20 2.43.0 From nobody Sun May 10 07:14:10 2026 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C621E1FA176 for ; Fri, 27 Dec 2024 16:57:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318679; cv=none; b=Uli48FaLMTSQHlql41peBUURmp73PwDp1skcRoIwV3jgs2Fwe2sYJrC69TzTgZV1EzKXYkxjGnS1iUZtuQqxh1NavljgHl6B/mVWxen9eTyOWJ1rI73Sa52fMU6GeW1NtOmpTBN/UnZpKJn5NkwQe+ExX6QcZE+It9gDlRo/zw4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318679; c=relaxed/simple; bh=GQfdS0kr5E8nwdLPiF4Pmvz7xsX6Pr29PRtsziZLSbs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uP0twaz5kV2/+kDk0DoqnrA68dD2+PSMwAPyZsaHecz2J+dnmKxuCWmcwcZGXRMnhqNIx/t2GCqiRphA8b19AmHipGqLEO2MT+hRH937OBiOub/jqg2hod9GrS0XXCm2YriGCNRrtRDlsqvacnO/YP+W/j5Q1ShDeWHCNx0gzVY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=YQ9C+lWP; arc=none smtp.client-ip=209.85.218.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="YQ9C+lWP" Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-aabfb33aff8so1295475166b.0 for ; Fri, 27 Dec 2024 08:57:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1735318676; x=1735923476; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y8SU2g1cyJY/YhurmsY4xoxi+5SPo4QoddhIipRwE9k=; b=YQ9C+lWPU0eM/JA5CP75DlRd8jOSUFq3D5uhyWHTuU2uf/ZJ+4H7KFe/tcjIMLW9iY 0+W4YK7paZBtPLTGic9lNgbuJL+82GaXt3AruMYrmbXf2Au9auTXeNdoMyhxIS84RZhQ /UquF316VqNwysK3/mChO2xhGrImMaAqX4mXA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735318676; x=1735923476; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y8SU2g1cyJY/YhurmsY4xoxi+5SPo4QoddhIipRwE9k=; b=A5TMi+BjmTuPjpiudnWkLg63/a6gpvSacXyBcVH4S1JnvX5g1jc396T+26JDPyXfDr Uor2NfvgXjD5sQ49X25zMaZjInQh8yJoUD2K1JSTjarR3QqwTYJAAxszuLpLSCH2m2PD C+Uo6uez+D9ts6jcZ9NJ+azbh2gk0NXj2dTf+RYU/NW2RP/otxJA2+0bZBEr2/Sbc25y jIUSdNQNVYufVM8/h4apctdLULQ6Rm5RNhLRnnsadup9UoAxs7HRNslq0Q2mM5rPvjhq ZXDCyhHf96NsCo/ZYQe7y+DS8XVinAtwZqjl9Giq6d/fiI/f0Me0reyRYoOq/HonFkuX KLFQ== X-Gm-Message-State: AOJu0YyVOqA3OB+e8AWR9fnY/1kE48wAwI9K6ZyjnGOy3SMmOGbRJPBM 9k/u4muaGUfCx6ZrnVwBlFAJCDsCTp+0riS3+y4aZ+OeEPFCSfziUkPv+RX5QTDjjnwYkbAc0cN z X-Gm-Gg: ASbGncsSLDthTmVSlyrCRJ2I74tSNQrzmrKHPVfU5hJQAvbBq4VcoqAI7kfO8t/70ts m5XJ05rcwblrVmI0t9fpsM+lDgkvgInkG8Prrgf4qalEe2X3ant50oouwDjtrdCmUk49fGqwSCi 5HqI6RteE9+MQY/MgyGYzLT03Ouf2EaUphl9OIHSSeoq4mFTr0ztiTscBkRjjEBrWeCUEofbBo6 /5Xj02X/G6xp/RfNh0u9KWo2w96dBIGxIXgJ6RktwSwrh5qCqsUTbzA4sGP57RXOuWONWPxorn2 gHyyIiDlXxKWM2N2pOQFoQ== X-Google-Smtp-Source: AGHT+IH0lWPZ7CSr63+Pe3YNPdP7iCVlRpFAQ9r8ey6JfEjfuzqQLJzkM3y+9Wa7RLtt+3lup5Nlpg== X-Received: by 2002:a17:907:969e:b0:aa6:938a:3c40 with SMTP id a640c23a62f3a-aac08228246mr2206907566b.24.1735318675830; Fri, 27 Dec 2024 08:57:55 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:55 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 20/23] arm64: dts: imx8mp: add PLLs to clock controller module (CCM) Date: Fri, 27 Dec 2024 17:56:23 +0100 Message-ID: <20241227165719.3902388-21-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the PLLs generated by anatop to the clock list of the Clock Controller Module (CCM) node. Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - New arch/arm64/boot/dts/freescale/imx8mp.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mp.dtsi index a1872b5d6e2e..ccf990a63372 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -751,9 +751,14 @@ clk: clock-controller@30380000 { ; #clock-cells =3D <1>; clocks =3D <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; + <&clk_ext3>, <&clk_ext4>, + <&anatop IMX8MP_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MP_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MP_ANATOP_DRAM_PLL>, + <&anatop IMX8MP_ANATOP_VIDEO_PLL>; clock-names =3D "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; + "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2", + "dram_pll", "video_pll"; fsl,anatop =3D <&anatop>; assigned-clocks =3D <&clk IMX8MP_CLK_A53_SRC>, <&clk IMX8MP_CLK_A53_CORE>, --=20 2.43.0 From nobody Sun May 10 07:14:10 2026 Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 341921FA27F for ; Fri, 27 Dec 2024 16:57:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318681; cv=none; b=Lr+TlIURZg9A80hmSx2MxczOcdPTPO4B/6JmXDVvl1+jkDw35zMplUnpIzQ2F405HvhJCSkRlB2XD4jrdwvuEglI4p2vdw147KxdmhzRielt/cuKq7tMfa49RZOQFOij4PAPl0enkbIkC/s4bHNAyjWgoNi9oZNMM4XCO6LOKu0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735318681; c=relaxed/simple; bh=bPw6sBKo42nWd35aKTqsGLLoGTjQzArJVhFrICMWSWU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VAf18EmZTodFoH2jl+d5DTl1i8H9XJ48i0TkK/yb+sNNtRLq8UQeJfWuHnPKxCABTaVkxvCwIVA0AlNVlb1I3JbtI/Fv/unFuBimi9IMTKvoysvrnOzIbrN4RRh3T965bKTdbP8HkDvzwy+IkYDFo638OmeZNLMCsv8b1+27QQg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=GU/zjL0L; arc=none smtp.client-ip=209.85.208.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="GU/zjL0L" Received: by mail-ed1-f41.google.com with SMTP id 4fb4d7f45d1cf-5d3f57582a2so15014302a12.1 for ; Fri, 27 Dec 2024 08:57:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1735318677; x=1735923477; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZqUbS4QFbQjY9acz5KfEUvUnduu2cjIu1TltoLZFYZg=; b=GU/zjL0LvuP5aIzubNe/y+WEZeClLzFlfNQPAwIRuuqsBH4szEE0zanQqoPLSW24SF WSeXCfY0Oba2DHTK0D761iNAKDndzWFof7dE5/wFzc7gtZ85ixDtl9PcZKoj3SE27ej+ Ody5Ew8ImtwP1wQ1HQQSkZIomKU1dhPT+iF44= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735318677; x=1735923477; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZqUbS4QFbQjY9acz5KfEUvUnduu2cjIu1TltoLZFYZg=; b=XVVT+Vpgh3AmF95YTwNDhNxMDL1KoelBslCE0lx+JAD02XyLKnnFokHQXtDv7H/m0I wtk/eu2ehLEGF5mO3/5syI6AVWPv2d+arS8dXARz4lt7MJUGAXlcxECOwVZA8koO7Hj/ RK0rNc/V7OEslEHYUGHpc4myZogrncQRFsUIkyCYYIXMk+3oWX/r55GwWCO7XJS1lF32 svQPzNFNCzl68WOpr7nMWSNYcLfCfSZPqfp2cdeNagQO10FqMlRBObBVFrK5pf25yaVf UIVvm7cVpSpl+8v2jtRakh68IypBrNQ1jRthAhpse7pGTF7T2YDYpJtYlZbKeCzOJsej 1dPw== X-Gm-Message-State: AOJu0YzO0tCxOCcXewiUmVg1ibdQKsff4+Tb5IhI3olsxxW0VVnp9t+a kPYmy3g8PhZd6Y1oMWwuF4l0icEvZhXq10dSt34xs2mc2yOo0VFgnijJNcdyRxOS6fJM9YcH8j+ P X-Gm-Gg: ASbGncsoXnwaa6sHIkWRhJ5qAF/4zDvjETrj9yuFsqnnKQaueg2jVsA93KT50+O/J0v rCSUDmQ4mHJMc4UcD7jd26K3erH2+Nw4wUsa+2/7G30U8gDb8oU84qWqKIGlxS2jcAM/jVszYFd SfcxaX2h6H1Egln3aFvLtRe4AUx7QxtiMSBydc7/qlaKyAl4KQvxP/+GkONMyPpEhuEpw7xxlWs ItMnoPmDN3Z4cvjhL3enY+YUZYsT5i1Y+wWhvHJgTJWykzoyl0SXQ6Q08ob2j9GNUp5XB0hTpCu CtPQuCs9JE0zIS/J4KH/IA== X-Google-Smtp-Source: AGHT+IHElfZi3i1uNBnK2xJqGFXo7qQDmANxsj6O+9wLFu70VpPDFGks7oNgpbJku7AT+TTCB0jLHA== X-Received: by 2002:a05:6402:2346:b0:5d8:17da:dcf0 with SMTP id 4fb4d7f45d1cf-5d81e523027mr20469463a12.4.1735318677486; Fri, 27 Dec 2024 08:57:57 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:57 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Krzysztof Kozlowski , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 21/23] dt-bindings: clock: imx8m-clock: support spread spectrum clocking Date: Fri, 27 Dec 2024 17:56:24 +0100 Message-ID: <20241227165719.3902388-22-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The addition of DT bindings for enabling and tuning spread spectrum clocking generation can be applied specifically to the PLLs. The "" value for the fsl,ssc-method property is specifically intended to specify a "no SSC" case, as in the example, when you don't want to configure spread spectrum for one of the PLLs, thus avoiding the use of a method that would only make sense if SSC were being set. Signed-off-by: Dario Binacchi Reviewed-by: Krzysztof Kozlowski --- Changes in v7: - List the PLLs to strictly define the setup order for each of the added properties - Drop maxItems from "fsl,ssc-modfreq-hz" and "fsl,ssc-modrate-percent" properties - Add 'Reviewed-by' tag of Krzysztof Kozlowski Changes in v6: - Improve the commit message - change minItems from 7 to 1 for all the ssc properties added - change maxItems from 10 to 4 for alle the ssc properties added - update the DTS example Changes in v4: - Drop "fsl,ssc-clocks" property. The other added properties now refer to the clock list. - Updated minItems and maxItems of - clocks - clock-names - fsl,ssc-modfreq-hz - fsl,ssc-modrate-percent - fsl,ssc-modmethod - Updated the dts examples Changes in v3: - Added in v3 - The dt-bindings have been moved from fsl,imx8m-anatop.yaml to imx8m-clock.yaml. The anatop device (fsl,imx8m-anatop.yaml) is indeed more or less a syscon, so it represents a memory area accessible by ccm (imx8m-clock.yaml) to setup the PLLs. Changes in v2: - Add "allOf:" and place it after "required:" block, like in the example schema. - Move the properties definition to the top-level. - Drop unit types as requested by the "make dt_binding_check" command. .../bindings/clock/imx8m-clock.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml b/Doc= umentation/devicetree/bindings/clock/imx8m-clock.yaml index eb2e6e702de9..76040ee9cd5c 100644 --- a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml @@ -50,6 +50,46 @@ properties: along with the oscillators, are used to generate the clocks for the on-chip peripherals. =20 + fsl,ssc-modfreq-hz: + description: + The values of modulation frequency (Hz unit) for each clock + supporting spread spectrum. + minItems: 1 + items: + - description: audio_pll1 + - description: audio_pll2 + - description: dram_pll + - description: video_pll + + fsl,ssc-modrate-percent: + description: + The percentage values of modulation rate for each clock + supporting spread spectrum. + minItems: 1 + items: + - description: audio_pll1 + - description: audio_pll2 + - description: dram_pll + - description: video_pll + + fsl,ssc-modmethod: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + description: | + The modulation techniques for each clock supporting spread + spectrum in this order:: + - audio_pll1 + - audio_pll2 + - dram_pll + - video_pll + minItems: 1 + maxItems: 4 + items: + enum: + - "" + - down-spread + - up-spread + - center-spread + required: - compatible - reg @@ -84,6 +124,10 @@ allOf: - const: clk_ext2 - const: clk_ext3 - const: clk_ext4 + fsl,ssc-modfreq-hz: false + fsl,ssc-modrate-percent: false + fsl,ssc-modmethod: false + else: properties: clocks: @@ -133,6 +177,9 @@ examples: "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2", "dram_pll", "video_pll"; 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:57:58 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Peng Fan , Abel Vesa , Fabio Estevam , Michael Turquette , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 22/23] clk: imx: pll14xx: support spread spectrum clock generation Date: Fri, 27 Dec 2024 17:56:25 +0100 Message-ID: <20241227165719.3902388-23-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for spread spectrum clock (SSC) generation to the pll14xxx driver. Signed-off-by: Dario Binacchi Reviewed-by: Peng Fan --- Changes in v7: - Add 'Reviewed-by' tag of Peng Fan Changes in v6: - Update the code based on the changes made to the DT bindings drivers/clk/imx/clk-pll14xx.c | 134 ++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk.h | 16 ++++ 2 files changed, 150 insertions(+) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index d63564dbb12c..c20f1ade9dff 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -20,6 +20,8 @@ #define GNRL_CTL 0x0 #define DIV_CTL0 0x4 #define DIV_CTL1 0x8 +#define SSCG_CTRL 0xc + #define LOCK_STATUS BIT(31) #define LOCK_SEL_MASK BIT(29) #define CLKE_MASK BIT(11) @@ -31,6 +33,10 @@ #define KDIV_MASK GENMASK(15, 0) #define KDIV_MIN SHRT_MIN #define KDIV_MAX SHRT_MAX +#define SSCG_ENABLE BIT(31) +#define MFREQ_CTL_MASK GENMASK(19, 12) +#define MRAT_CTL_MASK GENMASK(9, 4) +#define SEL_PF_MASK GENMASK(1, 0) =20 #define LOCK_TIMEOUT_US 10000 =20 @@ -40,6 +46,8 @@ struct clk_pll14xx { enum imx_pll14xx_type type; const struct imx_pll14xx_rate_table *rate_table; int rate_count; + bool ssc_enable; + struct imx_pll14xx_ssc ssc_conf; }; =20 #define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw) @@ -347,6 +355,27 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, un= signed long drate, return 0; } =20 +static void clk_pll1443x_enable_ssc(struct clk_hw *hw, unsigned long paren= t_rate, + unsigned int pdiv, unsigned int mdiv) +{ + struct clk_pll14xx *pll =3D to_clk_pll14xx(hw); + struct imx_pll14xx_ssc *conf =3D &pll->ssc_conf; + u32 sscg_ctrl, mfr, mrr; + + sscg_ctrl =3D readl_relaxed(pll->base + SSCG_CTRL); + sscg_ctrl &=3D + ~(SSCG_ENABLE | MFREQ_CTL_MASK | MRAT_CTL_MASK | SEL_PF_MASK); + + mfr =3D parent_rate / (conf->mod_freq * pdiv * (1 << 5)); + mrr =3D (conf->mod_rate * mdiv * (1 << 6)) / (100 * mfr); + + sscg_ctrl |=3D SSCG_ENABLE | FIELD_PREP(MFREQ_CTL_MASK, mfr) | + FIELD_PREP(MRAT_CTL_MASK, mrr) | + FIELD_PREP(SEL_PF_MASK, conf->mod_type); + + writel_relaxed(sscg_ctrl, pll->base + SSCG_CTRL); +} + static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { @@ -368,6 +397,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, uns= igned long drate, writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1); =20 + if (pll->ssc_enable) + clk_pll1443x_enable_ssc(hw, prate, rate.pdiv, rate.mdiv); + return 0; } =20 @@ -408,6 +440,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, uns= igned long drate, gnrl_ctl &=3D ~BYPASS_MASK; writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); =20 + if (pll->ssc_enable) + clk_pll1443x_enable_ssc(hw, prate, rate.pdiv, rate.mdiv); + return 0; } =20 @@ -542,3 +577,102 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *= dev, const char *name, return hw; } EXPORT_SYMBOL_GPL(imx_dev_clk_hw_pll14xx); + +void imx_clk_pll14xx_enable_ssc(struct clk_hw *hw, struct imx_pll14xx_ssc = *conf) +{ + struct clk_pll14xx *pll =3D to_clk_pll14xx(hw); + + pll->ssc_enable =3D true; + memcpy(&pll->ssc_conf, conf, sizeof(pll->ssc_conf)); +} +EXPORT_SYMBOL_GPL(imx_clk_pll14xx_enable_ssc); + +static int clk_pll14xx_ssc_mod_type(const char *name, + enum imx_pll14xx_ssc_mod_type *mod_type) +{ + int i; + struct { + const char *name; + enum imx_pll14xx_ssc_mod_type id; + } mod_types[] =3D { + { .name =3D "down-spread", .id =3D IMX_PLL14XX_SSC_DOWN_SPREAD }, + { .name =3D "up-spread", .id =3D IMX_PLL14XX_SSC_UP_SPREAD }, + { .name =3D "center-spread", .id =3D IMX_PLL14XX_SSC_CENTER_SPREAD } + }; + + for (i =3D 0; i < ARRAY_SIZE(mod_types); i++) { + if (!strcmp(name, mod_types[i].name)) { + *mod_type =3D mod_types[i].id; + return 0; + } + } + + return -EINVAL; +} + +static int clk_pll14xx_ssc_index(const char *pll_name) +{ + static const char *const pll_names[] =3D { + "audio_pll1", + "audio_pll2", + "dram_pll", + "video_pll" + }; + int i; + + for (i =3D 0; i < ARRAY_SIZE(pll_names); i++) { + if (!strcmp(pll_names[i], pll_name)) + return i; + } + + return -ENODEV; +} + +int imx_clk_pll14xx_ssc_parse_dt(struct device_node *np, const char *pll_n= ame, + struct imx_pll14xx_ssc *conf) +{ + int index, ret; + const char *s; + + if (!conf) + return -EINVAL; + + index =3D clk_pll14xx_ssc_index(pll_name); + if (index < 0) + return index; + + ret =3D of_property_read_u32_index(np, "fsl,ssc-modfreq-hz", index, + &conf->mod_freq); + if (ret) + return ret; + + ret =3D of_property_read_u32_index(np, "fsl,ssc-modrate-percent", index, + &conf->mod_rate); + if (ret) { + pr_err("missing fsl,ssc-modrate-percent property for %pOFn\n", + np); + return ret; + } + + ret =3D of_property_read_string_index(np, "fsl,ssc-modmethod", index, &s); + if (ret) { + pr_err("failed to get fsl,ssc-modmethod property for %pOFn\n", + np); + return ret; + } + + if (strlen(s) =3D=3D 0) + return -ENODEV; + + ret =3D clk_pll14xx_ssc_mod_type(s, &conf->mod_type); + if (ret) { + pr_err("wrong fsl,ssc-modmethod property for %pOFn\n", np); + return ret; + } + + pr_debug("%s: SSC %s settings: mod_freq: %d, mod_rate: %d: mod_method: %s= [%d]\n", + __func__, pll_name, conf->mod_freq, conf->mod_rate, s, conf->mod_type); + + return 0; +} +EXPORT_SYMBOL_GPL(imx_clk_pll14xx_ssc_parse_dt); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 50e407cf48d9..38e4a4cf253d 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -69,6 +69,18 @@ struct imx_pll14xx_clk { int flags; }; =20 +enum imx_pll14xx_ssc_mod_type { + IMX_PLL14XX_SSC_DOWN_SPREAD, + IMX_PLL14XX_SSC_UP_SPREAD, + IMX_PLL14XX_SSC_CENTER_SPREAD, +}; + +struct imx_pll14xx_ssc { + unsigned int mod_freq; + unsigned int mod_rate; + enum imx_pll14xx_ssc_mod_type mod_type; +}; + extern struct imx_pll14xx_clk imx_1416x_pll; extern struct imx_pll14xx_clk imx_1443x_pll; extern struct imx_pll14xx_clk imx_1443x_dram_pll; @@ -489,4 +501,8 @@ struct clk_hw *imx_clk_gpr_mux(const char *name, const = char *compatible, =20 struct clk_hw *imx_anatop_get_clk_hw(struct device_node *np, int id); =20 +void imx_clk_pll14xx_enable_ssc(struct clk_hw *hw, struct imx_pll14xx_ssc = *conf); +int imx_clk_pll14xx_ssc_parse_dt(struct device_node *np, const char *pll_n= ame, + struct imx_pll14xx_ssc *conf); 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([2.196.43.175]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f0159f1sm1130097266b.154.2024.12.27.08.57.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 08:58:00 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v7 23/23] clk: imx8mn: support spread spectrum clock generation Date: Fri, 27 Dec 2024 17:56:26 +0100 Message-ID: <20241227165719.3902388-24-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> References: <20241227165719.3902388-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for spread spectrum clock generation for the audio, video, and DRAM PLLs. Signed-off-by: Dario Binacchi --- Changes in v7: - Add and manage fsl,anatop property as phandle to the anatop node with the new patches: - 10/23 dt-bindings: clock: imx8m-clock: add phandle to the anatop - 11/23 arm64: dts: imx8mm: add phandle to anatop within CCM - 12/23 arm64: dts: imx8mn: add phandle to anatop within CCM - 13/23 arm64: dts: imx8mp: add phandle to anatop within CCM - 14/23 arm64: dts: imx8mq: add phandle to anatop within CCM Changes in v6: - Merge patches: 10/20 dt-bindings: clock: imx8mm: add binding definitions for anatop 11/20 dt-bindings: clock: imx8mn: add binding definitions for anatop 12/20 dt-bindings: clock: imx8mp: add binding definitions for anatop to 05/20 dt-bindings: clock: imx8m-anatop: define clocks/clock-names now renamed 05/18 dt-bindings: clock: imx8m-anatop: add oscillators and PLLs - Split the patch 15/20 dt-bindings-clock-imx8m-clock-support-spread-spectru.patch into 12/18 dt-bindings: clock: imx8m-clock: add PLLs 16/18 dt-bindings: clock: imx8m-clock: support spread spectrum clocking Changes in v5: - Fix compilation errors. - Separate driver code from dt-bindings Changes in v4: - Add dt-bindings for anatop - Add anatop driver - Drop fsl,ssc-clocks from spread spectrum dt-bindings Changes in v3: - Patches 1/8 has been added in version 3. The dt-bindings have been moved from fsl,imx8m-anatop.yaml to imx8m-clock.yaml. The anatop device (fsl,imx8m-anatop.yaml) is indeed more or less a syscon, so it represents a memory area accessible by ccm (imx8m-clock.yaml) to setup the PLLs. - Patches {3,5}/8 have been added in version 3. - Patches {4,6,8}/8 use ccm device node instead of the anatop one. Changes in v2: - Add "allOf:" and place it after "required:" block, like in the example schema. - Move the properties definition to the top-level. - Drop unit types as requested by the "make dt_binding_check" command. drivers/clk/imx/clk-imx8mn.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 984331372139..9a04e8138b7d 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -306,6 +306,7 @@ static int imx8mn_clocks_probe(struct platform_device *= pdev) struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node, *anp; void __iomem *base; + struct imx_pll14xx_ssc ssc_conf; int ret; =20 base =3D devm_platform_ioremap_resource(pdev, 0); @@ -347,9 +348,21 @@ static int imx8mn_clocks_probe(struct platform_device = *pdev) hws[IMX8MN_SYS_PLL3_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP= _SYS_PLL3_REF_SEL); =20 hws[IMX8MN_AUDIO_PLL1] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO= _PLL1); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll1", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MN_AUDIO_PLL1], &ssc_conf); + hws[IMX8MN_AUDIO_PLL2] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO= _PLL2); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll2", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MN_AUDIO_PLL2], &ssc_conf); + hws[IMX8MN_VIDEO_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VIDEO_= PLL); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "video_pll", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MN_VIDEO_PLL], &ssc_conf); + hws[IMX8MN_DRAM_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRAM_PL= L); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "dram_pll", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MN_DRAM_PLL], &ssc_conf); + hws[IMX8MN_GPU_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_PLL); hws[IMX8MN_M7_ALT_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M7_AL= T_PLL); hws[IMX8MN_ARM_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_PLL); --=20 2.43.0