From nobody Sun May 10 07:13:42 2026 Received: from mail-ed1-f45.google.com (mail-ed1-f45.google.com [209.85.208.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4CC53F9C5 for ; Fri, 27 Dec 2024 13:58:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735307920; cv=none; b=rX5AkDS1jpkV96RiSYzo9iC+Kb4zicAKvX6ZMLOocK5NpiNC+ehSCCGQnCQTsuMBjgk09QG4X0KfnzotTV2zggD01sc1lUY/QHLtU4D49Mfg3NPJjOQ3oXmgVS1tUEBXUtIlI/uRQvIN57r0loMo5RkkutIZiCfguFrQKST0GsA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735307920; c=relaxed/simple; bh=HAwnmobE9pbrLwCHRIIIdxDXdiG9rn+IBjiziYqpLF8=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Content-Type; b=P3PSshjuOD+SiZNYFjsQNcsbTNgIkEXs7bHz5+s0jgFsUiG9xjPG+VKQ+mzMEhid0Ik+Zt9qCUrTFg4Y9W6rdSr7VFRYQELL6DywaYBhmK0Mz7Qe1V0D8/+qXYGEJTLf1u9tayvosn0PREOjM/j5jIJxz8xxztXdPWEkmVickBw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=gSefDZZm; arc=none smtp.client-ip=209.85.208.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gSefDZZm" Received: by mail-ed1-f45.google.com with SMTP id 4fb4d7f45d1cf-5d3e8f64d5dso12560969a12.3 for ; Fri, 27 Dec 2024 05:58:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1735307917; x=1735912717; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=6iJyjzdma57dmyZ0t0UsW/0aGPhJ5fqmkpCDjzJ3qEI=; b=gSefDZZmpe1dVcjZwDuWm9K+9s+HUM/wV88Wya6FxKtTdo81Yn7Eu4yhjzDNlo4UNF ngFxlRUY9imP3H7VvwRtsyOKwODNgQHpo3vq9JJXBQRmnAzoNKfppjuBUCPfHyPLLjS3 vaxq5MN3GpRjNrb1WsnNvv93Hz5zCJEbThRmnQY+XDZCGHHfYHDa2Vq2DSKW3/+7kwjo tIuabqVLjHaHMwzE+QlP/8nLrgVXRJh5QtsEdZq0QBJt70Y8efo6VIxUkXE234N18QVR V/apCzQ1RFDsqAEZKOUgtAs7JXGEk9Qb2x7Y8DdrGOZvWKIJdvPr4JDVop09Pw95A0R4 Zr2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735307917; x=1735912717; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=6iJyjzdma57dmyZ0t0UsW/0aGPhJ5fqmkpCDjzJ3qEI=; b=TG/c/U3ATNGojYgfsRCrk4agZcTgLsffzme+cr+5H2fzwLscKSPH2QYr3ZGcQssIdy JZlsAtqTjpxYMleIPZly0yBr+9MsjLyKI6gMI5uRYJIbwW9ods0bKTcTjkj2oU2aXah8 cHFLvrDGRINKo3PvUSQIWECMz5L0Y+UtCAemPlB5utrVlNZNGpJ1fmRofQDgEJtbRpa2 yv/OoCQcjfx6Bi8KB1TSd4R/GZWqZ9KLFR64TdXCa5K5fc4RxnMZCwHDT55iqzgRQXvy ltDG5fB8aOovxabLkM/j3Ej0uhF6fAEnC3LWbrxh+ZpQQZh5m8FBuyJzCp+S2riuhYV4 xO9Q== X-Forwarded-Encrypted: i=1; AJvYcCX8v+LuCojCG55jVeXsjvwnaI+M/gWvYAGVwDIgZjYtHI8qGBNxLYMa8eD2mHyilbWMTO1/H+GCgzPQpcQ=@vger.kernel.org X-Gm-Message-State: AOJu0Yyz4BGGGXtA+GQ04JFhG4XvvM0T5yxdYIyTGbE452cCEbUWP4RF 5WX1pchU/sUKqKtbkDSySskM+S/thHPTcwpR94P06cCZ4+aUtjUe X-Gm-Gg: ASbGnct89t4DYYsVSr/A1ZunQGtDn+FJ8QsPPcEPbul0LZsss6/Tz+/UJ0dJWFI0VgU BT5AQJbX4mnJw4HSaOE5vhWV+g47CCsWgnMoZfBAlc4QxsvCXRyy8KAtXBLRuhic71XQcaOJwDj Pj7dauHZmH9Eo0u74DSe4SiZ5IbKODljToBCT93yZH+K5WA30yW55KI60cEtOEdulPhR5vBzRfD fcFpH+yXYbIUfh+fyCFfAhJ3SSI3Nj2bQA2tfyOSc6Dp4Kkt/0ILKo3dLwbT1twquFLNOmHYRA9 KglVK2RbmfVxWg== X-Google-Smtp-Source: AGHT+IEatqe6KwbwSsJX6AjxgXCAzeEk4xBS0tMM+82FN5ilbAK+1my21AU2Ddz2mwFwcuY4QrlJ6g== X-Received: by 2002:a05:6402:3225:b0:5cf:3dc3:7a3f with SMTP id 4fb4d7f45d1cf-5d81ddd6563mr24401972a12.5.1735307916881; Fri, 27 Dec 2024 05:58:36 -0800 (PST) Received: from localhost.localdomain ([109.245.32.58]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5d80679eea6sm10795204a12.49.2024.12.27.05.58.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Dec 2024 05:58:36 -0800 (PST) From: Aleksandar Rikalo To: linux-riscv@lists.infradead.org Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrew Jones , =?UTF-8?q?Christoph=20M=C3=BCllner?= , Aleksandar Rikalo , linux-kernel@vger.kernel.org, Djordje Todorovic Subject: [PATCH v2] riscv: Fix the PAUSE Opcode for MIPS P8700. Date: Fri, 27 Dec 2024 14:58:32 +0100 Message-Id: <20241227135832.188256-1-arikalo@gmail.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Djordje Todorovic The riscv MIPS P8700 uses a different opcode for PAUSE. It is a =E2=80=98hint=E2=80=99 encoding of the SLLI instruction, with rd=3D= 0, rs1=3D0 and imm=3D5. It will behave as a NOP instruction if no additional behavior beyond that of SLLI is implemented. Add ERRATA_MIPS and ERRATA_MIPS_P8700_PAUSE_OPCODE configs. Handle errata for MIPS CPUs. Signed-off-by: Djordje Todorovic Signed-off-by: Aleksandar Rikalo Signed-off-by: Raj Vishwanathan4 --- arch/riscv/Kconfig.errata | 22 +++++++++++++++++ arch/riscv/errata/Makefile | 1 + arch/riscv/errata/mips/Makefile | 5 ++++ arch/riscv/errata/mips/errata.c | 33 ++++++++++++++++++++++++++ arch/riscv/include/asm/alternative.h | 3 +++ arch/riscv/include/asm/vendorid_list.h | 1 + arch/riscv/kernel/alternative.c | 5 ++++ 7 files changed, 70 insertions(+) create mode 100644 arch/riscv/errata/mips/Makefile create mode 100644 arch/riscv/errata/mips/errata.c diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index 2acc7d876e1f..99c75fece8b9 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -21,6 +21,28 @@ config ERRATA_ANDES_CMO =20 If you don't know what to do here, say "Y". =20 +config ERRATA_MIPS + bool "MIPS errata" + depends on RISCV_ALTERNATIVE + help + All MIPS errata Kconfig depend on this Kconfig. Disabling + this Kconfig will disable all MIPS errata. Please say "Y" + here if your platform uses MIPS CPU cores. + + Otherwise, please say "N" here to avoid unnecessary overhead. + +config ERRATA_MIPS_P8700_PAUSE_OPCODE + bool "Fix the PAUSE Opcode for MIPS P8700" + depends on ERRATA_MIPS && 64BIT + help + The RISCV MIPS P8700 uses a different opcode for PAUSE. + It is a 'hint' encoding of the SLLI instruction, + with rd=3D0, rs1=3D0 and imm=3D5. It will behave as a NOP + instruction if no additional behavior beyond that of + SLLI is implemented. + + If you are not using the P8700 processor, say N. + config ERRATA_SIFIVE bool "SiFive errata" depends on RISCV_ALTERNATIVE diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile index f0da9d7b39c3..156cafb338c1 100644 --- a/arch/riscv/errata/Makefile +++ b/arch/riscv/errata/Makefile @@ -9,5 +9,6 @@ endif endif =20 obj-$(CONFIG_ERRATA_ANDES) +=3D andes/ +obj-$(CONFIG_ERRATA_MIPS) +=3D mips/ obj-$(CONFIG_ERRATA_SIFIVE) +=3D sifive/ obj-$(CONFIG_ERRATA_THEAD) +=3D thead/ diff --git a/arch/riscv/errata/mips/Makefile b/arch/riscv/errata/mips/Makef= ile new file mode 100644 index 000000000000..6278c389b801 --- /dev/null +++ b/arch/riscv/errata/mips/Makefile @@ -0,0 +1,5 @@ +ifdef CONFIG_RISCV_ALTERNATIVE_EARLY +CFLAGS_errata.o :=3D -mcmodel=3Dmedany +endif + +obj-y +=3D errata.o diff --git a/arch/riscv/errata/mips/errata.c b/arch/riscv/errata/mips/errat= a.c new file mode 100644 index 000000000000..7affc590ded5 --- /dev/null +++ b/arch/riscv/errata/mips/errata.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024 MIPS. + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +void __init_or_module mips_errata_patch_func(struct alt_entry *begin, + struct alt_entry *end, + unsigned long archid, + unsigned long impid, + unsigned int stage) +{ + if (!IS_ENABLED(CONFIG_ERRATA_MIPS)) + return; + + if (!IS_ENABLED(CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE)) + return; + + asm volatile(ALTERNATIVE(".4byte 0x1000000f", ".4byte 0x00501013", + MIPS_VENDOR_ID, 0, /* patch_id */ + CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE)); +} diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/= alternative.h index 3c2b59b25017..bc3ada8190a9 100644 --- a/arch/riscv/include/asm/alternative.h +++ b/arch/riscv/include/asm/alternative.h @@ -48,6 +48,9 @@ struct alt_entry { void andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *en= d, unsigned long archid, unsigned long impid, unsigned int stage); +void mips_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, + unsigned long archid, unsigned long impid, + unsigned int stage); void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *e= nd, unsigned long archid, unsigned long impid, unsigned int stage); diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/as= m/vendorid_list.h index 2f2bb0c84f9a..55d979a7a7c2 100644 --- a/arch/riscv/include/asm/vendorid_list.h +++ b/arch/riscv/include/asm/vendorid_list.h @@ -8,5 +8,6 @@ #define ANDES_VENDOR_ID 0x31e #define SIFIVE_VENDOR_ID 0x489 #define THEAD_VENDOR_ID 0x5b7 +#define MIPS_VENDOR_ID 0x127 =20 #endif diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternativ= e.c index 7eb3cb1215c6..7642704c7f18 100644 --- a/arch/riscv/kernel/alternative.c +++ b/arch/riscv/kernel/alternative.c @@ -47,6 +47,11 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufactu= rer_info_t *cpu_mfr_info cpu_mfr_info->patch_func =3D andes_errata_patch_func; break; #endif +#ifdef CONFIG_ERRATA_MIPS + case MIPS_VENDOR_ID: + cpu_mfr_info->patch_func =3D mips_errata_patch_func; + break; +#endif #ifdef CONFIG_ERRATA_SIFIVE case SIFIVE_VENDOR_ID: cpu_mfr_info->patch_func =3D sifive_errata_patch_func; --=20 2.25.1