From nobody Tue Feb 10 18:36:40 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 980351EA80 for ; Fri, 27 Dec 2024 01:10:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735261835; cv=none; b=Pqr+hoQUc0zw+mGhMyR56WOTHYO6D3aFQm4JvbIEY4zrIRW2lRQtp8PmY1G6CtMfW9ilH3X1oLWKqcaRf8NB+jXrABDJ47wVkAYoYD6w0/J4Sr8PSSO+ZaeYBFeeh46veFOnPNApHfgqnX7PKK8nRGU+vGtGZN/mDkI/ENngljM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735261835; c=relaxed/simple; bh=ZQvAGn/2NlyTLE3ty4U7yyFatMFiuoweHmxM3NYxd9s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=i1YaNpFpE/NUAj/CQ45C2W+DGqTAiYjeZWQOVoTlP1Pkz53jkE0EvibhjQMve+8uIpGLvA94qNp0sbRyf5Bs7Fn+j8fkUgOGtVAdrMFjpQ/uIda8IgfNwz4CL8S9XMSLwT7pxgnEdapjnATGNB+DlxS8lz/36Gn8KbQU9cQ2VX0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PeZ1kEAp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PeZ1kEAp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E7F09C4CEDC; Fri, 27 Dec 2024 01:10:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1735261834; bh=ZQvAGn/2NlyTLE3ty4U7yyFatMFiuoweHmxM3NYxd9s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PeZ1kEAp68nyIi/RJ5ZdLkSOeUrgMc/fSVBuT0mLtmilREx+IP91edm7/kKg2N1JH iMVn9kpXvF4fjd/rV49CCfOHwi8bCQ3dU997P4ruWiAg78TmkbOprD3tev8LSCKbk3 RbGmIxM5CvgwhAww2+ntH/FodbVcCpMSWW7vEpXgN2P5PEaxQFT2IApJKntndQRJiM Isgvs+5unaC+O7RMUTlxBLTdoeOiJtUcuNBtFYu6SpdC3H/XzzP/FW3HEJK+XzGHwq UZAbuoS8ZmafCtz4HmO41xtz3732f0HOkTJXdMhq4tEIb1gjgFCa3okQYHMq/2EjF7 Of8pTprIEsLng== From: guoren@kernel.org To: paul.walmsley@sifive.com, palmer@dabbelt.com, guoren@kernel.org, bjorn@rivosinc.com, conor@kernel.org, leobras@redhat.com, peterz@infradead.org, parri.andrea@gmail.com, will@kernel.org, longman@redhat.com, boqun.feng@gmail.com, arnd@arndb.de, alexghiti@rivosinc.com, ajones@ventanamicro.com, rkrcmar@ventanamicro.com, atishp@rivosinc.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Guo Ren Subject: [RFC PATCH V2 1/4] RISC-V: paravirt: Add pvqspinlock KVM backend Date: Thu, 26 Dec 2024 20:10:08 -0500 Message-Id: <20241227011011.2331381-2-guoren@kernel.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20241227011011.2331381-1-guoren@kernel.org> References: <20241227011011.2331381-1-guoren@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Guo Ren Add the files functions needed to support the SBI PVLOCK (paravirt qspinlock kick_cpu) extension. Implement kvm_sbi_ext_pvlock_kick_- cpu(), and we only need to call the kvm_vcpu_kick() and bring target_vcpu from the halt state. Reviewed-by: Leonardo Bras Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/include/asm/kvm_vcpu_sbi.h | 1 + arch/riscv/include/asm/sbi.h | 5 +++ arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/Makefile | 1 + arch/riscv/kvm/vcpu_sbi.c | 4 ++ arch/riscv/kvm/vcpu_sbi_pvlock.c | 57 +++++++++++++++++++++++++++ 6 files changed, 69 insertions(+) create mode 100644 arch/riscv/kvm/vcpu_sbi_pvlock.c diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index b96705258cf9..bc37131938ad 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -88,6 +88,7 @@ extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_d= bcn; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_sta; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor; +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_pvlock; =20 #ifdef CONFIG_RISCV_PMU_SBI extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_pmu; diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 6c82318065cf..03e719f076ad 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -35,6 +35,7 @@ enum sbi_ext_id { SBI_EXT_DBCN =3D 0x4442434E, SBI_EXT_STA =3D 0x535441, SBI_EXT_NACL =3D 0x4E41434C, + SBI_EXT_PVLOCK =3D 0x50564C4B, =20 /* Experimentals extensions must lie within this range */ SBI_EXT_EXPERIMENTAL_START =3D 0x08000000, @@ -401,6 +402,10 @@ enum sbi_ext_nacl_feature { #define SBI_NACL_SHMEM_SRET_X(__i) ((__riscv_xlen / 8) * (__i)) #define SBI_NACL_SHMEM_SRET_X_LAST 31 =20 +enum sbi_ext_pvlock_fid { + SBI_EXT_PVLOCK_KICK_CPU =3D 0, +}; + /* SBI spec version fields */ #define SBI_SPEC_VERSION_DEFAULT 0x1 #define SBI_SPEC_VERSION_MAJOR_SHIFT 24 diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index 3482c9a73d1b..4590570a8fc3 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -198,6 +198,7 @@ enum KVM_RISCV_SBI_EXT_ID { KVM_RISCV_SBI_EXT_VENDOR, KVM_RISCV_SBI_EXT_DBCN, KVM_RISCV_SBI_EXT_STA, + KVM_RISCV_SBI_EXT_PVLOCK, KVM_RISCV_SBI_EXT_MAX, }; =20 diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index 0fb1840c3e0a..4e1a82a7eeab 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -32,6 +32,7 @@ kvm-y +=3D vcpu_sbi_replace.o kvm-y +=3D vcpu_sbi_sta.o kvm-$(CONFIG_RISCV_SBI_V01) +=3D vcpu_sbi_v01.o kvm-y +=3D vcpu_switch.o +kvm-y +=3D vcpu_sbi_pvlock.o kvm-y +=3D vcpu_timer.o kvm-y +=3D vcpu_vector.o kvm-y +=3D vm.o diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index 6e704ed86a83..c770bef51a2f 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -82,6 +82,10 @@ static const struct kvm_riscv_sbi_extension_entry sbi_ex= t[] =3D { .ext_idx =3D KVM_RISCV_SBI_EXT_VENDOR, .ext_ptr =3D &vcpu_sbi_ext_vendor, }, + { + .ext_idx =3D KVM_RISCV_SBI_EXT_PVLOCK, + .ext_ptr =3D &vcpu_sbi_ext_pvlock, + }, }; =20 static const struct kvm_riscv_sbi_extension_entry * diff --git a/arch/riscv/kvm/vcpu_sbi_pvlock.c b/arch/riscv/kvm/vcpu_sbi_pvl= ock.c new file mode 100644 index 000000000000..55d889ddc2cd --- /dev/null +++ b/arch/riscv/kvm/vcpu_sbi_pvlock.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c), 2024 Alibaba Cloud + * + * Authors: + * Guo Ren + */ + +#include +#include +#include +#include +#include + +static int kvm_sbi_ext_pvlock_kick_cpu(struct kvm_vcpu *vcpu) +{ + struct kvm_cpu_context *cp =3D &vcpu->arch.guest_context; + struct kvm *kvm =3D vcpu->kvm; + struct kvm_vcpu *target; + + target =3D kvm_get_vcpu_by_id(kvm, cp->a0); + if (!target) + return SBI_ERR_INVALID_PARAM; + + kvm_vcpu_kick(target); + + if (READ_ONCE(target->ready)) + kvm_vcpu_yield_to(target); + + return SBI_SUCCESS; +} + +static int kvm_sbi_ext_pvlock_handler(struct kvm_vcpu *vcpu, struct kvm_ru= n *run, + struct kvm_vcpu_sbi_return *retdata) +{ + int ret =3D 0; + struct kvm_cpu_context *cp =3D &vcpu->arch.guest_context; + unsigned long funcid =3D cp->a6; + + switch (funcid) { + case SBI_EXT_PVLOCK_KICK_CPU: + ret =3D kvm_sbi_ext_pvlock_kick_cpu(vcpu); + break; + default: + ret =3D SBI_ERR_NOT_SUPPORTED; + } + + retdata->err_val =3D ret; + + return 0; +} + +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_pvlock =3D { + .extid_start =3D SBI_EXT_PVLOCK, + .extid_end =3D SBI_EXT_PVLOCK, + .handler =3D kvm_sbi_ext_pvlock_handler, +}; --=20 2.40.1