From nobody Mon Feb 9 01:52:26 2026 Received: from mail-m15593.qiye.163.com (mail-m15593.qiye.163.com [101.71.155.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 440C71B4146; Tue, 24 Dec 2024 09:49:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=101.71.155.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735033777; cv=none; b=k7fXoDhCFsa7wNaM9cC6At+a320QaVmKn+S1Fvk8c/SNJqUpsON1Ez65kccKR1S+JMGPru2FPMkjaO2qMoc09RphgRH0MKq18nibozvA0RzO7FjA3vPnM8v71Q760VxD3v4GaoYuedd8CD9evr6Y6+eVki1jK/Wc2sDLYPqPZoQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735033777; c=relaxed/simple; bh=WHhCpWlNKddpg5CKXgmY4DN7unF6qYEFA9+0vTcWAk0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=C/+/vvHQ3dClu/2i1euMkSrNRgG7s/Dv3I2WFgFSkPvI2AO+1G6stemPysiM/4WP3Hcp4tlmmTD8RhgIHhaJuWPGGO8w8wrXLfIlRGFkuKGNfCjPvJBq6UQNc+s/q1EQydzuWxHFAAQ8+ZvcPummlFkBl/8OizjBO5YnTdXAZAQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=kDlja3iW; arc=none smtp.client-ip=101.71.155.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="kDlja3iW" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 6aad4ee1; Tue, 24 Dec 2024 17:49:25 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , Simon Xue , Conor Dooley , Rob Herring , Bjorn Helgaas , linux-pci@vger.kernel.org, =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , devicetree@vger.kernel.org, Lorenzo Pieralisi , Shawn Lin , Manivannan Sadhasivam , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 01/17] dt-bindings: PCI: dwc: rockchip: Add rk3562 support Date: Tue, 24 Dec 2024 17:49:04 +0800 Message-Id: <20241224094920.3821861-2-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241224094920.3821861-1-kever.yang@rock-chips.com> References: <20241224094920.3821861-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQkxIHlYfGB8dGRhISk0dGUxWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCSE NVSktLVUpCS0tZBg++ X-HM-Tid: 0a93f8123cba03afkunm6aad4ee1 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Nxw6UTo5PDITFEoRFktLLCs* Gh4aCRxVSlVKTEhOS0hITE1NTk1OVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFDSUI3Bg++ DKIM-Signature: a=rsa-sha256; b=kDlja3iWYWdMq6LcgpOabX78pR0W+tigHsyEX80pTuf6bteEGFycAYoOTI/eLgSAqDFzcJ/gnoznmAYCzFk9sgpUmA+IEUFyBYzhcF3NPjozXheOLookix+uzryyg7fFfrFR6YbEZ9kix/86bxy+KyEfVpAYMMv7gPvrMHNDxxw=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=v0BA7iqw1thPHV06/lmELXjL7ByEp1rbkTCxKwOXO2A=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" rk3562 is using the same controller as rk3568. Signed-off-by: Kever Yang Reviewed-by: Heiko Stuebner --- Changes in v2: None Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/= Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 9a464731fa4a..dce6d68865c7 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -26,6 +26,7 @@ properties: - const: rockchip,rk3568-pcie - items: - enum: + - rockchip,rk3562-pcie - rockchip,rk3576-pcie - rockchip,rk3588-pcie - const: rockchip,rk3568-pcie --=20 2.25.1 From nobody Mon Feb 9 01:52:26 2026 Received: from mail-m127158.xmail.ntesmail.com (mail-m127158.xmail.ntesmail.com [115.236.127.158]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F3EB1BEF82; Tue, 24 Dec 2024 09:49:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.236.127.158 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735033778; cv=none; b=CbHjNFkDHwQIyUhi5cWJZj1EX9rSfizrIOKUTIKY0GhRDB9MunRhEf0AG1kNVLlKhLwbKd/bWVdyxCRXm0dT1kYLU8Wr4ycddLgH0L/3Uh6wgYVv7b7ZKuU0LWAXIoWz7mF7K0P2I3ZBBgeE6MZVnLwagt73ldqKL5oYKw91RB8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735033778; c=relaxed/simple; bh=nwOrRzYKRAawu2Q/5xarfry/s0Wnu6iKpKIqeTi+AzY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Y53mwQKLH0uePcI4b+osBIfvW/4CuK/QkF0a9siup7UdlkGo2vE6+DcNLf+8dEqO1n3nUMcqLd9Sv86Q27zSeVAEOw81b+qgI89yIWNiX5PPTESO0p9p6yf3wMDI0GbA0nyxZERuDUBve/cXIbFiQ/A4bC/eH2rcGz4KrIXL1vY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=UW7X+Yjq; arc=none smtp.client-ip=115.236.127.158 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="UW7X+Yjq" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 6aad4ee8; Tue, 24 Dec 2024 17:49:26 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , devicetree@vger.kernel.org, Conor Dooley , Rob Herring , Jisheng Zhang , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Ulf Hansson Subject: [PATCH v2 02/17] dt-bindings: mmc: Add support for rk3562 eMMC Date: Tue, 24 Dec 2024 17:49:05 +0800 Message-Id: <20241224094920.3821861-3-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241224094920.3821861-1-kever.yang@rock-chips.com> References: <20241224094920.3821861-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQ0kYTFZKSEkYGUhIGkNNT0pWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a93f812434003afkunm6aad4ee8 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Nxg6Ayo*STIOTUozS1EqLDUz EBEKFCJVSlVKTEhOS0hITE1MQktMVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFKSUxINwY+ DKIM-Signature: a=rsa-sha256; b=UW7X+YjqDvlBxMNOu0sjqZY8HpN2ytS3XGlGuLaq57xynPQJOnsuJoZA3VpTSP8y2QQe8Vcj0FXLDp8zYndIQ0L+jFeCIGjKy6G4rHMI3KRlW380htcLRuCvp3KH7iSZtc0fAl0LfNzAC8bo20Eyocv1KhB6cZYs8NN4Q0nrUs4=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=8Vy2jX1P5CcfS+k88EOexLOM32haPI+pYQW5JzkIYwM=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" rk3562 is using the same controller as rk3588. Signed-off-by: Kever Yang --- Changes in v2: None .../devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml = b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml index c3d5e0230af1..33f4288ff879 100644 --- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml @@ -14,16 +14,19 @@ properties: compatible: oneOf: - items: - - const: rockchip,rk3576-dwcmshc + - const: rockchip,rk3568-dwcmshc - const: rockchip,rk3588-dwcmshc - enum: - - rockchip,rk3568-dwcmshc - - rockchip,rk3588-dwcmshc - snps,dwcmshc-sdhci - sophgo,cv1800b-dwcmshc - sophgo,sg2002-dwcmshc - sophgo,sg2042-dwcmshc - thead,th1520-dwcmshc + - items: + - enum: + - rockchip,rk3562-dwcmshc + - rockchip,rk3576-dwcmshc + - const: rockchip,rk3588-dwcmshc =20 reg: maxItems: 1 --=20 2.25.1 From nobody Mon Feb 9 01:52:26 2026 Received: from mail-m127173.xmail.ntesmail.com (mail-m127173.xmail.ntesmail.com [115.236.127.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FA0F1917F0; Tue, 24 Dec 2024 09:49:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.236.127.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735033774; cv=none; b=Mo/N+ppZ3pm7X4n5/NGXwJIGcxrFh+vPdfUpz5GqsMdShNUU00jSdxw9wcHg5l61WAQ315u8jDKfiUkTRd8TrpVDr5slCfFl76nYOb1h4ZSZN1og370dZc4rCQ8AO3DVUMd7qgrijLMBuwIQweOmiupDMfKQm3Qq98Jxr9WGWEY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735033774; c=relaxed/simple; bh=wt6pcLM6vYVhlnsbSkC+CukL2UdqKSRndcgFfg1xVmA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=U8ybn7RDeGLrqbK6gYl8YkEXi3DzKUBpGkRK4ea7u0PyqrnRJhrITRn2jmRIXkuvM9rSNXe3iGZXZ3Xirq3UDPPz6SbxeqqL6JSYactKp/ndvb12tpu7UFqAj8tWxRgFzstBDq/K0lSQz975Cxy7c5DNlAixhC7a2HwByZh3L0w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=RLV+8yjf; arc=none smtp.client-ip=115.236.127.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="RLV+8yjf" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 6aad4eef; Tue, 24 Dec 2024 17:49:28 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , devicetree@vger.kernel.org, Conor Dooley , Rob Herring , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, Ulf Hansson Subject: [PATCH v2 03/17] dt-bindings: mmc: rockchip-dw-mshc: Add rk3562 compatible string Date: Tue, 24 Dec 2024 17:49:06 +0800 Message-Id: <20241224094920.3821861-4-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241224094920.3821861-1-kever.yang@rock-chips.com> References: <20241224094920.3821861-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGktOSlZPGB5OGEMeTktIQxpWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSEtNT0 1VSktLVUpCWQY+ X-HM-Tid: 0a93f812488403afkunm6aad4eef X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6PzI6TQw4QzIcNkosFlYCLDIv DFYaFDhVSlVKTEhOS0hITE1CSkJMVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFDQ0I3Bg++ DKIM-Signature: a=rsa-sha256; b=RLV+8yjfPEqclnGQKP48Duwe2uNc5Hxwjo1n5ZycnicSBvaYJRm9G0xkcQN4sHPsO5Q3W3L5kRsUM7A3HbY49oluqxpdeUSYBd8uoXYbd6AKEQXtZKt6E5etHUlEKvAjyud1bq3x+zMw2Rshqih8d+IU+OIWudMiC2hLVIetnUw=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=VoKJ6FOgCFP1HuVMBu37S6FxFo809cHz971Ja0kvKBU=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add RK3588 compatible string for SD interface. Signed-off-by: Kever Yang --- Changes in v2: None Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml b/= Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml index 06df1269f247..772f592291bf 100644 --- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml @@ -38,6 +38,7 @@ properties: - rockchip,rk3328-dw-mshc - rockchip,rk3368-dw-mshc - rockchip,rk3399-dw-mshc + - rockchip,rk3562-dw-mshc - rockchip,rk3568-dw-mshc - rockchip,rk3588-dw-mshc - rockchip,rv1108-dw-mshc --=20 2.25.1 From nobody Mon Feb 9 01:52:26 2026 Received: from mail-m127100.qiye.163.com (mail-m127100.qiye.163.com [115.236.127.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E5F61B218E; Tue, 24 Dec 2024 09:49:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.236.127.100 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735033775; cv=none; b=nYYHqbqnpWQLPf+Mpd4/eQfX93OP4WQvmZYQFW0fjWTz8moof3GCFdwajev6Nfp8y82nfobfNcWmrZI6soBsm94nrqAgnEIn297B2bjIsdASAygbwr72Pzi1g72LykTxo7uGhhoUAnzVBjWA2jCnBL+mguUIiM1b9FJCtkQja2U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735033775; c=relaxed/simple; bh=WZcTx6gA0r45LEdA6rQJC5BGENRKsVGLhIq1MmnZii8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TOuF64lldCsmtatuPL6i5g3TQrBqRBTqir+fGTV2NDJH9xip+vvKkVjcowql1Q9KBLKs919DXaFeoTOlVv+EqZXAIQYbkL8XrjO0J2WzKVKf796gud+GN3s09R1l2HzwbPzXHhTX8tooFUPwR5cvgZ9gUQe0HkhyGPvhn7cYwXw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=Tjix2ixa; arc=none smtp.client-ip=115.236.127.100 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="Tjix2ixa" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 6aad4ef6; Tue, 24 Dec 2024 17:49:29 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , devicetree@vger.kernel.org, Conor Dooley , Finley Xiao , Rob Herring , Detlev Casanova , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Elaine Zhang , linux-arm-kernel@lists.infradead.org, Ulf Hansson Subject: [PATCH v2 04/17] dt-bindings: power: rockchip: Add bindings for rk3562 Date: Tue, 24 Dec 2024 17:49:07 +0800 Message-Id: <20241224094920.3821861-5-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241224094920.3821861-1-kever.yang@rock-chips.com> References: <20241224094920.3821861-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQklJTVZKGkNKHU8aSB5CSE1WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCSE NVSktLVUpCS0tZBg++ X-HM-Tid: 0a93f8124d8e03afkunm6aad4ef6 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Pgw6FQw6IzIOIkpWLFExLDwZ TjQaCS5VSlVKTEhOS0hITExLTU1NVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFCT0s3Bg++ DKIM-Signature: a=rsa-sha256; b=Tjix2ixaScAPFTECUNb9KcHWczqWyKfBPWs6d0bTxJnBq+N36/L1PlMTm8uamAwU0vAOClamBW3BXjka4Pu+Lq4nMS4dMgl8Ba4zp+ShKnF9gCY/pWkXlZ9UNags+oiv5Nbjupp2yk0BbbxlSNbao+STi7m/tBX/pxpBmQ4fcdY=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=9UI8ZWSnef9pE/uO9n5qBniu7nZ0lTpAreivjCmgTYc=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add the compatible string for rk3562 SoC. Signed-off-by: Kever Yang Reviewed-by: Heiko Stuebner --- Changes in v2: None .../devicetree/bindings/power/rockchip,power-controller.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/rockchip,power-control= ler.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controlle= r.yaml index 650dc0aae6f5..79b948518f0c 100644 --- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml @@ -40,6 +40,7 @@ properties: - rockchip,rk3366-power-controller - rockchip,rk3368-power-controller - rockchip,rk3399-power-controller + - rockchip,rk3562-power-controller - rockchip,rk3568-power-controller - rockchip,rk3576-power-controller - rockchip,rk3588-power-controller --=20 2.25.1 From nobody Mon Feb 9 01:52:26 2026 Received: from mail-m11879.qiye.163.com (mail-m11879.qiye.163.com [115.236.118.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C940F1DDA2D; Tue, 24 Dec 2024 09:49:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.236.118.79 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735033782; cv=none; b=lg7E1yHR3sEfAwBbvakIcuCqrmKq4DPj8aj1IehNNSM2UJoRIb25tTwkrZu+ujKgsBvXXj4RFGQDHuIELxAmiHpEnBoxe2J/xOexKdJeGJnVeUtK+G6J2suG4DEieCZzNCu2+VpEh91FFNsWC+R1OEGj9io98FLGPgxx9kGHaaQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735033782; c=relaxed/simple; bh=fo4O3DUbdR1GLX4YrHy6RH/QYtH7FZoVdSoQT0b+94s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=MvaV0FptxcdxvkVMgOLzzvxhkVFmXthTAArxbacHH+J3JjbvUfMnVvp0vcZ8hjXCuR7f36AAGQwIwrPjnwQ1BGJfoCAmt35JZ2o0EUbBRGzrKfPLuSMMPCa7hk51wRNGGEOx7mAHLS0NXjivb4/1bOZyOvi9eAMwj2g9sNSpaI8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=IwzHhIi8; arc=none smtp.client-ip=115.236.118.79 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="IwzHhIi8" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 6aad4f01; Tue, 24 Dec 2024 17:49:30 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , devicetree@vger.kernel.org, Conor Dooley , Rob Herring , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andi Shyti Subject: [PATCH v2 05/17] dt-bindings: i2c: i2c-rk3x: Add rk3562 compatible Date: Tue, 24 Dec 2024 17:49:08 +0800 Message-Id: <20241224094920.3821861-6-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241224094920.3821861-1-kever.yang@rock-chips.com> References: <20241224094920.3821861-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGUtOTFYYQ01ITBkdHk9OGRlWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a93f812534c03afkunm6aad4f01 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6K1E6LBw4SDIWEEowPFEfLClR ME4KCUxVSlVKTEhOS0hITExJSkpOVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFDSU03Bg++ DKIM-Signature: a=rsa-sha256; b=IwzHhIi81TA9HnKZ+z7VyIPgp/5sMLOZaP6B7rfbkbSej+P2D/Yt/iOj3hTrqwyFX/KMLp2ViGZkJz1jTAWaxA42Q8jLF1EiW2aUsn8FWuogVfXkUWGVW0Zcg87u4y963UFeRdMCOi1RNapygG/x9E96rN8SKnOzKDEswz085uQ=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=Fa7XEoZ+RPcBuWk9L6Qw7dSHYC3bDV3g23RfgBMjFWQ=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" rk3562 i2c compatible to the existing rk3399 binding. Signed-off-by: Kever Yang Reviewed-by: Heiko Stuebner --- Changes in v2: None Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml b/Document= ation/devicetree/bindings/i2c/i2c-rk3x.yaml index a9dae5b52f28..8101afa6f146 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml @@ -37,6 +37,7 @@ properties: - rockchip,px30-i2c - rockchip,rk3308-i2c - rockchip,rk3328-i2c + - rockchip,rk3562-i2c - rockchip,rk3568-i2c - rockchip,rk3576-i2c - rockchip,rk3588-i2c --=20 2.25.1 From nobody Mon Feb 9 01:52:26 2026 Received: from mail-m121146.qiye.163.com (mail-m121146.qiye.163.com [115.236.121.146]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDF601CDFBE; Tue, 24 Dec 2024 09:49:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.236.121.146 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735033784; cv=none; b=Ou5fenMmQpsmXgXEp3XdEQnjeHwE1EFfoBTCAYn61bv75BXKYpeh7b8mukljAKYpwqPZosLBVJ9l1TrkmduYNidpg8rG0e64RpYXhcsfHuB9XvGeJZdWSMFaOiJX5FD/ZXfQHjmjnE5/8Hi9C88E6Vcmx2OT0O/DoTeTjBuHCOU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735033784; c=relaxed/simple; bh=yX1efV3vxWaB+V9q+ARgCgX2dEqq7xoActrT8Fj3DOo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fstW0vLKz+FsiKEl7aezPLl77SW8S8S8pNCPyYDr/TMptRk+mWYmIfmbnCmiMzEnw0lFCKlG+gijMgi8cNxBY2gj7KD/3XPIAItxpr4nyGFHQGiy/TOXkWtsKBTecHD8mTaA3KMWeFgOPKKVI+kFF2s0z5WLU1sIAU6WoENcbnc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=T7LND+Xf; arc=none smtp.client-ip=115.236.121.146 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="T7LND+Xf" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 6aad4f0b; Tue, 24 Dec 2024 17:49:32 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , devicetree@vger.kernel.org, Conor Dooley , Maxime Ripard , Rob Herring , Thomas Zimmermann , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , Krzysztof Kozlowski , Maarten Lankhorst , Simona Vetter Subject: [PATCH v2 06/17] dt-bindings: gpu: Add rockchip,rk3562-mali compatible Date: Tue, 24 Dec 2024 17:49:09 +0800 Message-Id: <20241224094920.3821861-7-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241224094920.3821861-1-kever.yang@rock-chips.com> References: <20241224094920.3821861-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGkhCS1YaGRgeHUxPHk0YTklWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a93f81258f503afkunm6aad4f0b X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6PVE6ATo4SjILHEojS0oILCFR EFYwCjdVSlVKTEhOS0hITExITU5IVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFKS05NNwY+ DKIM-Signature: a=rsa-sha256; b=T7LND+XfDLkMaBiBZdsXWlMZ20wC0hDD2YrIeXQLdN2oTHRdXeEfAqIqS7XRckXVUKbjvhX/ExBAVZNrzvu4oBR5u0IEsbf88I+onTvMahEKB+q28VzzCjIHlthBYUHNmCw3NmzUgDf0iZ84SS8R2PQkZXjiB7vdDpC9tRzbTFM=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=9e0fkON3OqPWW/xMJm4rwqQ0FxbNptJZ1Px6QOShTng=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" rk3562 has 1 ARM Mali-G52 GPU,. Signed-off-by: Kever Yang --- Changes in v2: None Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/= Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 735c7f06c24e..b0d4806614aa 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -25,6 +25,7 @@ properties: - renesas,r9a07g044-mali - renesas,r9a07g054-mali - rockchip,px30-mali + - rockchip,rk3562-mali - rockchip,rk3568-mali - rockchip,rk3576-mali - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is f= ully discoverable @@ -60,7 +61,7 @@ properties: =20 clocks: minItems: 1 - maxItems: 3 + maxItems: 4 =20 clock-names: true =20 --=20 2.25.1 From nobody Mon Feb 9 01:52:26 2026 Received: from mail-m1973170.qiye.163.com (mail-m1973170.qiye.163.com [220.197.31.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3ED5517C220; Tue, 24 Dec 2024 09:54:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735034088; cv=none; b=n3fafa/OI67+B81mkWd31W34+IMZteeNTDpwZDL9CSGalF71VWEjLgjWKS9LxZE7c+es4m0vsvUOrb0kiwfhUo8xWmMW4a8GksRHum4vyaZWXlxuaeHUkmxX7ipN7GTKQr690tLSHUEM8H7t4dba3hFgNBsQxswGKOpP36AzhOw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735034088; c=relaxed/simple; bh=QC8QKO926aubblv/IQQskodaCWChRpxnYNf+iiZ2nS0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=A8kYc0RGgrImvd8XxEAV37iXExhbto7wNwhTNeEG6S/ESqRbGWkdyTMAnFtR5ThcYCBt/IG8NByKLHlbbmib2riYEqwNRbgzYNQOxJgdYkY96wYMmNMHsCa5oUA4ALmqAMKPPBCgVwUhcYhJYeOH16YziUAgdiJC0eTWnr0+Gjg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=kIsQGord; arc=none smtp.client-ip=220.197.31.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="kIsQGord" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 6aad4f15; Tue, 24 Dec 2024 17:49:33 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , Jamie Iles , Guenter Roeck , linux-watchdog@vger.kernel.org, Rob Herring , Wim Van Sebroeck , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , devicetree@vger.kernel.org, Conor Dooley Subject: [PATCH v2 07/17] dt-bindings: watchdog: Add rk3562 compatible Date: Tue, 24 Dec 2024 17:49:10 +0800 Message-Id: <20241224094920.3821861-8-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241224094920.3821861-1-kever.yang@rock-chips.com> References: <20241224094920.3821861-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGkNKHlZOSx1LHxpDQh4dSU1WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSEpOTE 5VSktLVUpCS0tZBg++ X-HM-Tid: 0a93f8125ef503afkunm6aad4f15 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6MRQ6UQw4CDIXPko3PFELLBkM TTdPCRJVSlVKTEhOS0hITExOS01DVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFDTks3Bg++ DKIM-Signature: a=rsa-sha256; b=kIsQGord8lsAPJmwszbIVhJI3b+HHzCIMLWAf6rQyq5DWGDccoC0RNicvEadQy8GW9w+qIhrB3ksI/idOd777KwoiVRBxb2wN2N7piZj48fEqpN1fnjTsXApCGlkc4Qbvlb1DA5JH0xzzW2OkxQmaO4Y5PNvM2s9NsSBlKPAIAg=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=w65nHanWmBSK+gAUJK97FwbkvqytD7kBrCEuPTUVJpI=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add rockchip,rk3562-wdt for rk3562. Signed-off-by: Kever Yang Reviewed-by: Heiko Stuebner --- Changes in v2: None Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml b/= Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml index 1efefd741c06..ef088e0f6917 100644 --- a/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml @@ -28,6 +28,7 @@ properties: - rockchip,rk3328-wdt - rockchip,rk3368-wdt - rockchip,rk3399-wdt + - rockchip,rk3562-wdt - rockchip,rk3568-wdt - rockchip,rk3576-wdt - rockchip,rk3588-wdt --=20 2.25.1 From nobody Mon Feb 9 01:52:26 2026 Received: from mail-m3277.qiye.163.com (mail-m3277.qiye.163.com [220.197.32.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA56017C220; Tue, 24 Dec 2024 09:54:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735034094; cv=none; b=QIEb83L4tVBtMeIf1DbkNQZ2/w7gFSPnGtKnUoUcbVEPIs1/4fip6DfKqLPDAGnS85LDmFczMd3JPcC5El+n2z7PU+ABiT2OoEa2EgTJXyBZxUA4JYZQl4XPmWJ591OL7OSwPm90PjdcDfhBPTfaYdboyd2jampDeimDkiqisoM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735034094; c=relaxed/simple; bh=NegVq0gVVmJ4TG/f+ZAU4nDfTp6uIPSBqRmjVKo0FmE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=VY1msJdrNlsa0zHR9EDCAAwSUuQPKnMN4u4nElDmXn0yE1bu0FJd2A9pg2I8ApyCON4YGyHMS9fjw1AFQL5CNOM6MlQ2XvLQ6ErQhPjutl9/KWYMn1R3VdYm+hKF3BL/zeGpPNNsjhoyNN2TKzjTIC6GMBX6y9djDRpKKEU6Gbc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=aIC4AIcW; arc=none smtp.client-ip=220.197.32.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="aIC4AIcW" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 6aad4f1b; Tue, 24 Dec 2024 17:49:35 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , devicetree@vger.kernel.org, Conor Dooley , Rob Herring , Mark Brown , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 08/17] dt-bindings: spi: Add rockchip,rk3562-spi compatible Date: Tue, 24 Dec 2024 17:49:11 +0800 Message-Id: <20241224094920.3821861-9-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241224094920.3821861-1-kever.yang@rock-chips.com> References: <20241224094920.3821861-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQ0JDTlYaT0pJTE9LSkkdQ0NWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSEpOTE 5VSktLVUpCS0tZBg++ X-HM-Tid: 0a93f812647d03afkunm6aad4f1b X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6MS46Nxw5DjITPkodS1EvLCo1 NQMaCw9VSlVKTEhOS0hITExNT01KVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFDT0o3Bg++ DKIM-Signature: a=rsa-sha256; b=aIC4AIcWKqKoT7LNOzi3cjWVG65DmdskHtqwrE28ZQDWJltkEJs9GEM8YYIm/lHy6ezEtwUeZSGqS9x8XL/4bkC4F6pYHknE00uMA3alZaocRHp07Iqg93Yf5VPrlx4Fwe20YQkfz6soDVs5O5K7ryO9OYSnuv4IrLrqGF2AiO0=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=IOM1U89s1aYg720JAUn/jQO6iCYKE+w0kQFvGel09Ys=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add rockchip,rk3562-spi compatible for rk3562. Signed-off-by: Kever Yang Reviewed-by: Heiko Stuebner --- Changes in v2: None Documentation/devicetree/bindings/spi/spi-rockchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.yaml b/Docu= mentation/devicetree/bindings/spi/spi-rockchip.yaml index 46d9d6ee0923..104f5ffdd04e 100644 --- a/Documentation/devicetree/bindings/spi/spi-rockchip.yaml +++ b/Documentation/devicetree/bindings/spi/spi-rockchip.yaml @@ -34,6 +34,7 @@ properties: - rockchip,rk3328-spi - rockchip,rk3368-spi - rockchip,rk3399-spi + - rockchip,rk3562-spi - rockchip,rk3568-spi - rockchip,rk3576-spi - rockchip,rk3588-spi --=20 2.25.1 From nobody Mon Feb 9 01:52:26 2026 Received: from mail-m32122.qiye.163.com (mail-m32122.qiye.163.com [220.197.32.122]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C37511B0F15; Tue, 24 Dec 2024 10:04:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.122 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735034699; cv=none; b=p7GsaPlrwJp8yce0iPsuhTxmEE+1KmU+3KfKx9jLCfw2wbX3zkfxwb+Wg00tKAXWM8eerqpzLd5MimQf9i1ONLfmuDPYFuvYD8COs4zQepnVdDO01jLmik1GxVBVoedu+JzxAlxwkAJvsj1yMSiOkFUxCM8Wjqkz19h8TU+bKB0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735034699; c=relaxed/simple; bh=w1sYguIT9Fej9Y7r2rAQOrte9SJwK4CiC+goidounq4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nIP+3MvAK7bmUEBbaw03ZJ4/idiYNyfso7lZeLTDmMFA/RKvgmpTu7RPF08L7XB8hg8+lyB3iJrJIZ32+q//gE9WGEtpaD58wo9iZuHdsj5fWTQFSqnk4j5vBh/IKErAy/Nr/Izssf4YubdyhTM8iurjnNc/+Pgs+byrpAENR+g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=PaW1ZunR; arc=none smtp.client-ip=220.197.32.122 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="PaW1ZunR" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 6aad4f50; Tue, 24 Dec 2024 17:49:36 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , devicetree@vger.kernel.org, Conor Dooley , Rob Herring , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-serial@vger.kernel.org, Greg Kroah-Hartman , Jiri Slaby Subject: [PATCH v2 09/17] dt-bindings: serial: snps-dw-apb-uart: Add support for rk3562 Date: Tue, 24 Dec 2024 17:49:12 +0800 Message-Id: <20241224094920.3821861-10-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241224094920.3821861-1-kever.yang@rock-chips.com> References: <20241224094920.3821861-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGktJS1ZCSkhCHk4ZTR5DT05WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a93f81269ea03afkunm6aad4f50 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Nyo6ORw6DTIQPkoXS0s3LChM HxQKCihVSlVKTEhOS0hITExMTEJLVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFDQ083Bg++ DKIM-Signature: a=rsa-sha256; b=PaW1ZunRuKqrq2MEcyGvF1ID608tmpEBs1Ro/ydVWnjvr7HLMMz1O26g0VS1hqqnDc5P4TWf9gDt2Imm5nODPfT5p9LW1pKRKpA++M8yZHQFJBP84ZqWggVGGDH36hTeQ4RextZmgpNyVvv9ues5FURWMFR2LqgxBr9dBwve9+E=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=LL/r0W7SCVHJRGGyzbWqtnf2sNnv53u7nqfOYyaOwaI=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add rockchip,rk3562-uart compitable for rk3562. Signed-off-by: Kever Yang --- Changes in v2: None Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml= b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index 1c163cb5dff1..1c16ca3b4e29 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -51,6 +51,7 @@ properties: - rockchip,rk3368-uart - rockchip,rk3399-uart - rockchip,rk3528-uart + - rockchip,rk3562-uart - rockchip,rk3568-uart - rockchip,rk3576-uart - rockchip,rk3588-uart --=20 2.25.1 From nobody Mon Feb 9 01:52:26 2026 Received: from mail-m127215.xmail.ntesmail.com (mail-m127215.xmail.ntesmail.com [115.236.127.215]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DC331CDFBE; Tue, 24 Dec 2024 09:49:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.236.127.215 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735033789; cv=none; b=f5WaWP6bWK6bAvPHS0Sk7TDYN0pHIQJzTflyWGejBsTZItqAr+XKf60vIW1CpBn785XWJACoivkXzQnSOTpeYVE2CZPFR7dlo3oHL9JK4osAIzl+52fpNIPQxflmj+ahWRU78lFkkk3Jt8Gm5rW2r0uvAw2W/4Kr/uvIVZH4bzQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735033789; c=relaxed/simple; bh=cHLUqHGkKDoJ0mL+61QqCJNO8UunlVhfzuPKNlSkGQQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ePokThT9NpQM/iurOt3AdR0d4G0Hq5HDiP+j1WYAvIQL9Di9RGe+V07+pLv3AjjmUwLGAgst0XDroS3GNzhMNg0xRROQXznUVZmrQ8IahdajaPiEsQeQGqQwhIAtUOVDkW+9d2WurSJnORic+n9yA3IDzxpjRN1M+Y/IFcM78yE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=HlfSvl5/; arc=none smtp.client-ip=115.236.127.215 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="HlfSvl5/" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 6aad4f59; Tue, 24 Dec 2024 17:49:37 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , devicetree@vger.kernel.org, Conor Dooley , Rob Herring , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 10/17] dt-bindings: usb: dwc3: add compatible for rk3562 Date: Tue, 24 Dec 2024 17:49:13 +0800 Message-Id: <20241224094920.3821861-11-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241224094920.3821861-1-kever.yang@rock-chips.com> References: <20241224094920.3821861-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGhlIQlZNSk4YGEJNQx1JSE9WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a93f8126f1e03afkunm6aad4f59 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6M0k6Izo6GjIJPkoWLEsLLCE1 FxUwChhVSlVKTEhOS0hITExCS0NIVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFKSkxLNwY+ DKIM-Signature: a=rsa-sha256; b=HlfSvl5/UF4BxSCe2K7AJgdps7uY8ZjKeF60whpmphLfqs1dXG8m0vwT4jRHjuMOp+EsHrDbh5El5/tar0koX5MfIzdbYkoU+N/sCV1crnlTwsn8ssTQ7Ld3Zcoeo3NcLwNT7oKF8P6Za1UXSuc+fyUZUWQw3T4fYClKTspwgoA=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=68ftBDlYO9wugDwPKtS3dP5ZbdpY5EAp5ZhhRM8+9lk=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add "rockchip,rk3362-dwc3" for rk3562 SOC. Signed-off-by: Kever Yang --- Changes in v2: None Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Doc= umentation/devicetree/bindings/usb/rockchip,dwc3.yaml index a21cc098542d..999f704c3ec0 100644 --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml @@ -26,6 +26,7 @@ select: contains: enum: - rockchip,rk3328-dwc3 + - rockchip,rk3562-dwc3 - rockchip,rk3568-dwc3 - rockchip,rk3576-dwc3 - rockchip,rk3588-dwc3 @@ -37,6 +38,7 @@ properties: items: - enum: - rockchip,rk3328-dwc3 + - rockchip,rk3562-dwc3 - rockchip,rk3568-dwc3 - rockchip,rk3576-dwc3 - rockchip,rk3588-dwc3 @@ -72,6 +74,7 @@ properties: - enum: - grf_clk - utmi + - pipe - const: pipe =20 power-domains: --=20 2.25.1 From nobody Mon Feb 9 01:52:26 2026 Received: from mail-m3289.qiye.163.com (mail-m3289.qiye.163.com [220.197.32.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 089141B4F08; Tue, 24 Dec 2024 09:54:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735034098; cv=none; b=kq6tETUusoe25hkxm6VnipxNDaBUBcXrW3UFa2CTH4s8eN3Ng/mgyMU0WytMCF+b0JLP+zWRoephoWZqXjeIakx4gbfE97WVt94MzuszFKcgrfHqdgstz3O2QEclJVO9PWFQ4ifShkIYnrgEX3AXg1yw0WFFuez8V2u4R0CAiUo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735034098; c=relaxed/simple; bh=hckWa6p0gk6GNcGRhA+PlXwIad0KLZaOWT8kBhYpWCM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JB+644ipn4wPcU7IvgsCdHFVRNahyfuuTpUgaPtpR3CummtxVqN5ECblD9uMw2lXyqr14SVYEy2HtCINfrdLcUQWFiC8EKjlE5VF8KYIKYohhENBBRon1FGsL8uIhFd/J0RTXZE8UY0GGFg/zWZrUoAr3mZeYQdd9/iK0KKb6E0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=cNBvizXw; arc=none smtp.client-ip=220.197.32.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="cNBvizXw" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 6aad4f5e; Tue, 24 Dec 2024 17:49:39 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , linux-pwm@vger.kernel.org, Conor Dooley , Rob Herring , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , devicetree@vger.kernel.org, =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 11/17] dt-bindings: pwm: rockchip: Add rockchip,rk3562-pwm Date: Tue, 24 Dec 2024 17:49:14 +0800 Message-Id: <20241224094920.3821861-12-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241224094920.3821861-1-kever.yang@rock-chips.com> References: <20241224094920.3821861-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGUJOSlYYTEweSkoeThhKSB9WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSEtNT0 1VSktLVUpCWQY+ X-HM-Tid: 0a93f812742d03afkunm6aad4f5e X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6MRA6KBw6LTINLko*LEo2LC0P ShQKFD9VSlVKTEhOS0hITENLTklLVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFDSkw3Bg++ DKIM-Signature: a=rsa-sha256; b=cNBvizXwpV1e0xw7155UyKzIz+tVZDUiMSgZtdb3yHjj2jdauY7AUm8yUDhAGDzFd2NL9w7KbZsyeXnJemM2sWNwD0bxw0rbZTXs8AgZ5f7lKOPddhFyO3tlVoOpy6g1mm+V+hgqIwMavzwUmngGp1Hw5rGhLwDKd4xstPKS0sM=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=DTvew9FRb8bcd/cfA8z7sQXsLhbV+v0u07kTJMk/M2w=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add rockchip,rk3562-pwm compatible string. Signed-off-by: Kever Yang Acked-by: Uwe Kleine-K=C3=B6nig --- Changes in v2: None Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml b/Docu= mentation/devicetree/bindings/pwm/pwm-rockchip.yaml index 65bfb492b3a4..e4e1976c542d 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml @@ -30,6 +30,7 @@ properties: - enum: - rockchip,px30-pwm - rockchip,rk3308-pwm + - rockchip,rk3562-pwm - rockchip,rk3568-pwm - rockchip,rk3588-pwm - rockchip,rv1126-pwm --=20 2.25.1 From nobody Mon Feb 9 01:52:26 2026 Received: from mail-m15589.qiye.163.com (mail-m15589.qiye.163.com [101.71.155.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 435C61B218E for ; Tue, 24 Dec 2024 12:12:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=101.71.155.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735042332; cv=none; b=lLvCIZkSVsxluZH/2tBIH35Js1FGLh1X4eHl5UYcTD8j3WYT3n/cuipUlm72dpoaNnHnzQ0kr7cdpEmBYRbivU26mmN2hsh8BLs7F/ao02qy9W6lxHYKpkoTozuXds5NDIAjVhGq5kUhXX1E16CRKSxjE/fnwfSIIkfsKTw3Aok= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735042332; c=relaxed/simple; bh=66tJrPYvnaX7wPQnC2UpY8qpklVA4/zHerJmYRAsOSo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jGu+7STp/FA2bH/fkCWtVUjrgNKoB1Vs+cCLcvSKjngNstT4r+6BSgSEpnwnB7ahJmd278eA2NeNVvt9SmkzedHDMk4CP8K5zqCeUYlr4vU2g4E6fxwaNFyK/GTV7rYUcE6pWH6SiCYi3a6TkB1B9Wk0iTmRR6l8o2OwiSIaB0A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=GxW+ybFg; arc=none smtp.client-ip=101.71.155.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="GxW+ybFg" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 6aad4f6a; Tue, 24 Dec 2024 17:49:40 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , devicetree@vger.kernel.org, Conor Dooley , Rob Herring , Detlev Casanova , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Elaine Zhang , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 12/17] dt-bindings: rockchip: pmu: Add rk3562 compatible Date: Tue, 24 Dec 2024 17:49:15 +0800 Message-Id: <20241224094920.3821861-13-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241224094920.3821861-1-kever.yang@rock-chips.com> References: <20241224094920.3821861-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQxlNSFZLGR8aShoeTUseGUxWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCSE NVSktLVUpCS0tZBg++ X-HM-Tid: 0a93f81279c003afkunm6aad4f6a X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Pyo6ETo6HzILKkpNS0s3LC80 KSoKCRlVSlVKTEhOS0hITENKQ0NNVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFKS0xCNwY+ DKIM-Signature: a=rsa-sha256; b=GxW+ybFgP2oUmDg0xlRk4yaXjbq2z0+x6wbauAKR4c0pGEyoLX8OAohEGqQ56JXikf/zuKx5WrMfj61ASq+X5Yv1gQmodM2PA1NcgcPhJWK0SmfsBTqBWvGEhWsZ61c6NK7F7F45+r+/cIDaLJFDAamLK4EYaqi47nGiFXeULNY=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=rWeRULdaEAjUyPyZtlil4hxdnVPJSdzZYhFcp4YiY6Q=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add the compatible for the pmu mfd on rk3562. Signed-off-by: Kever Yang --- Changes in v2: None Documentation/devicetree/bindings/arm/rockchip/pmu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml b/Docu= mentation/devicetree/bindings/arm/rockchip/pmu.yaml index 932f981265cc..9b1919fc5598 100644 --- a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml @@ -25,6 +25,7 @@ select: - rockchip,rk3288-pmu - rockchip,rk3368-pmu - rockchip,rk3399-pmu + - rockchip,rk3562-pmu - rockchip,rk3568-pmu - rockchip,rk3576-pmu - rockchip,rk3588-pmu @@ -43,6 +44,7 @@ properties: - rockchip,rk3288-pmu - rockchip,rk3368-pmu - rockchip,rk3399-pmu + - rockchip,rk3562-pmu - rockchip,rk3568-pmu - rockchip,rk3576-pmu - rockchip,rk3588-pmu --=20 2.25.1 From nobody Mon Feb 9 01:52:26 2026 Received: from mail-m19731116.qiye.163.com (mail-m19731116.qiye.163.com [220.197.31.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4403119D062; Tue, 24 Dec 2024 10:05:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735034710; cv=none; b=fMrSIJ5IVD0Zr1cyB4Q0+MmDVdbIQK0DaIrINpfLDlYPMftw6ZIEiS+r3y8XN8uspCOFX1jxzkCIbsRxhEBPXyTTrbQGZ2nm7KuFX2/SfQ90XE8sGCZ1awnxMbjDPEKwMgd0fW9ivPHJsz1n9EPcH32TXWXBbS/0agOHX7rNOXg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735034710; c=relaxed/simple; bh=iDGXC2yu/AvvpiZWdscwTRUl3T8SVOF1Ay/nTPzvz/4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=P5LUYWF/D91pCWYsBWsuJOZSGut0HOj92pGcHYSDl6+ytHxW5GhnAlVEOW7ybnRaeTpsye35oWhikF2ylIJWgLss5b60LJCmz8mMmUU0QZ+I7dBGqpYSv7XSJUs7HSfBluXS+05y/FAYbul8dNNoVgCti4cN74TM12uw0kRHUjg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=ciGeaKql; arc=none smtp.client-ip=220.197.31.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="ciGeaKql" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 6aad4f70; Tue, 24 Dec 2024 17:49:41 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , devicetree@vger.kernel.org, Conor Dooley , Cristian Ciocaltea , Rob Herring , Detlev Casanova , linux-kernel@vger.kernel.org, Shresth Prasad , Sebastian Reichel , linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , Frank Wang Subject: [PATCH v2 13/17] dt-bindings: soc: rockchip: Add rk3562 syscon compatibles Date: Tue, 24 Dec 2024 17:49:16 +0800 Message-Id: <20241224094920.3821861-14-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241224094920.3821861-1-kever.yang@rock-chips.com> References: <20241224094920.3821861-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQx1LTVZLGExOSx5MTU9DT0xWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCSE NVSktLVUpCS0tZBg++ X-HM-Tid: 0a93f8127f1a03afkunm6aad4f70 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6MVE6Sxw5MTIIUUo9FkoKLCoC IT4aCShVSlVKTEhOS0hITENIT0pCVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFKSE5CNwY+ DKIM-Signature: a=rsa-sha256; b=ciGeaKqlnc1SjGU8x8bXpagzM/61jmc+YzK/MfzkSDZpliDcvYNr1tbggcuyX2Rz4UEt0yo1aXWxbJafnOpCHDqqSchl0Pw7aYU3Bax44ZrTvUNiVFZY32dOR0HqjM4fNbPGOduUU6G23At/ctRpGwPzsIuLM7cTwWU6NFMr0Rw=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=ETcqNtL3RNj/yE8+dpP3KC+3XumtE7FIB8FYa35ra/U=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add all syscon compatibles for rk3562. Signed-off-by: Kever Yang --- Changes in v2: None Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Docu= mentation/devicetree/bindings/soc/rockchip/grf.yaml index 7eca9e1ad6a3..40e6781f4ec1 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -15,6 +15,12 @@ properties: - items: - enum: - rockchip,rk3288-sgrf + - rockchip,rk3562-ioc-grf + - rockchip,rk3562-peri-grf + - rockchip,rk3562-pipephy-grf + - rockchip,rk3562-pmu-grf + - rockchip,rk3562-sys-grf + - rockchip,rk3562-usbphy-grf - rockchip,rk3566-pipe-grf - rockchip,rk3568-pcie3-phy-grf - rockchip,rk3568-pipe-grf @@ -78,6 +84,7 @@ properties: - rockchip,rk3368-pmugrf - rockchip,rk3399-grf - rockchip,rk3399-pmugrf + - rockchip,rk3562-pmu-grf - rockchip,rk3568-grf - rockchip,rk3568-pmugrf - rockchip,rk3576-ioc-grf --=20 2.25.1 From nobody Mon Feb 9 01:52:26 2026 Received: from mail-m49239.qiye.163.com (mail-m49239.qiye.163.com [45.254.49.239]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E36A91CEE82; Tue, 24 Dec 2024 09:49:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.239 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735033795; cv=none; b=k+7qTb0yqaMCQRFXW7uL/ntK83K4ngP3Ws7gzwL641xtfZ+ldS7PjtO6avPKQKNHVL0UUD24t8rV2SUiKokI8Yj0X5i7h13jkKUOm+NnvKWImWp1O3abQTZA9PvWwaNWpsD7sVLXHMBkLJSxL+Gf6A/VsnYXBFexKZ8fscvwuMY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735033795; c=relaxed/simple; bh=/3PB4YY83BzB8Vujvtm79iFjM/5EPVPMSaYKjX6/0tM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TCtAEZzcBqnFka2fvLnaZ9lBgC+VbSU1oTGDvFkN7cFN40HmWsRiGG7ue2R2cmO3Jnxpi1rnZvTyT+I2icOavO7d+ooNh2DeaB5CJFBV/6wNgBe+Q8TQD4cpgLTY7SLjvxq36VDsRn0HJ5ux6A3JG/TZRs7r1MMQwRr0Y75wcSY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=V4EpYXmG; arc=none smtp.client-ip=45.254.49.239 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="V4EpYXmG" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 6aad4f7a; Tue, 24 Dec 2024 17:49:43 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , devicetree@vger.kernel.org, Conor Dooley , Chris Morgan , Rob Herring , Dragan Simic , Jonas Karlman , linux-kernel@vger.kernel.org, Tim Lunn , linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , Andy Yan Subject: [PATCH v2 14/17] dt-bindings: arm: rockchip: Add rk3562 evb2 board Date: Tue, 24 Dec 2024 17:49:17 +0800 Message-Id: <20241224094920.3821861-15-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241224094920.3821861-1-kever.yang@rock-chips.com> References: <20241224094920.3821861-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQk5JS1YeQh0aGkhJSEMZS0JWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a93f812852303afkunm6aad4f7a X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Njo6Pio4HjINOkoNPEpKLCEJ MAgwCUtVSlVKTEhOS0hITENOS01CVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFCTEg3Bg++ DKIM-Signature: a=rsa-sha256; b=V4EpYXmG4grMHKIU83NHoDgupDZeUsyUQF0dsblajsus9+ifKLnWJxj3m4W3GMVC9s9L+1LZl+bQqXkPFuZBVh/Dc9XSnxqV4WkaYp6qAPsMpeqp222wXfHCNF/Tcp9gGz2IoKkIly2XAMbjGeCSn9hPQwvg5S/VLlAxJbSHLCU=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=Oq00+y/kuWMjOL0bTcvLlpDd0OK7vNwa3VWp6ptm2Lk=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add device tree documentation for rk3562-evb2-v10. Signed-off-by: Kever Yang Acked-by: Krzysztof Kozlowski --- Changes in v2: - Update in sort order Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 1bd1b609fcff..0d182360f165 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -1006,6 +1006,11 @@ properties: - const: rockchip,rk3399-sapphire-excavator - const: rockchip,rk3399 =20 + - description: Rockchip RK3562 Evaluation board 2 + items: + - const: rockchip,rk3562-evb2-v10 + - const: rockchip,rk3562 + - description: Rockchip RK3566 BOX Evaluation Demo board items: - const: rockchip,rk3566-box-demo --=20 2.25.1 From nobody Mon Feb 9 01:52:26 2026 Received: from mail-m12780.qiye.163.com (mail-m12780.qiye.163.com [115.236.127.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 775501B0F1B; Tue, 24 Dec 2024 10:05:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.236.127.80 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735034712; cv=none; b=E6LvDqetIb+xqcXEheCg6Ca9NpYXJjSoj8Umgxv4pUZb8171Xen/9E22XexGyiFFSnDFuajd1KC4VpqlAWLMPo5oSRn5vmyg9wOanV8qUamlgeHzP2IUPDr3f3kt8B6RjnSYDkHiF6lS95Tudc8IvDS86ZrXXDwXaS7W400othY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735034712; c=relaxed/simple; bh=IJ3ZC7aM9ktxzp48GdsTTcOSTQnW5Jfj2N/LMnId7Dc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SMXCTP06LbpfhMEZkUeGa3LkIqZqfShO+D7az80/kKDhhjYfl6FSyS8l4uivZKNTZpfEFTmbLlbVzMwoR6RahjfJhFUab7dnGihDaUDJ9+fDGDvtPrWLt/d72svr3WWrFjLfN83RGL0JKaBVmzcN7SoonBa6GcIJgXaI88mH+1o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=glO0dxbI; arc=none smtp.client-ip=115.236.127.80 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="glO0dxbI" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 6aad4f82; Tue, 24 Dec 2024 17:49:45 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , devicetree@vger.kernel.org, Lee Jones , Rob Herring , linux-kernel@vger.kernel.org, Conor Dooley , Krzysztof Kozlowski Subject: [PATCH v2 15/17] dt-bindings: mfd: syscon: Add rk3562 QoS register compatible Date: Tue, 24 Dec 2024 17:49:18 +0800 Message-Id: <20241224094920.3821861-16-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241224094920.3821861-1-kever.yang@rock-chips.com> References: <20241224094920.3821861-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQ0IaGFYYQ0JJQ0tOGExCTEpWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSEtNT0 1VSktLVUpCWQY+ X-HM-Tid: 0a93f8128b8703afkunm6aad4f82 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6MCI6Ghw5NjIUKkoBFlYsLCo3 Ly0wFExVSlVKTEhOS0hITENNSUxOVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFKS05INwY+ DKIM-Signature: a=rsa-sha256; b=glO0dxbIc5mAlSbO4TG6QTNTemfww1OyLNPrv8Ydpx1FdMDDasxs2HRJTuZqv32JwA4JgHhkAuCNoZMebwRGWJkIlue622UP7YYY1FR4khMwbiNVU1RG3GA2gPalU0HOZNjhYv/12fg7OgaCqgTqXEOV9Fy1te+W7dTM2EOqRZc=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=PA0QQbiZYVOq710Nd9y5Bo6g0MIw2h3IL327OaalC58=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Document rk3562 compatible for QoS registers. Signed-off-by: Kever Yang --- Changes in v2: None Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index b414de4fa779..03937a82db0f 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -103,6 +103,7 @@ select: - rockchip,rk3288-qos - rockchip,rk3368-qos - rockchip,rk3399-qos + - rockchip,rk3562-qos - rockchip,rk3568-qos - rockchip,rk3576-qos - rockchip,rk3588-qos @@ -201,6 +202,7 @@ properties: - rockchip,rk3288-qos - rockchip,rk3368-qos - rockchip,rk3399-qos + - rockchip,rk3562-qos - rockchip,rk3568-qos - rockchip,rk3576-qos - rockchip,rk3588-qos --=20 2.25.1 From nobody Mon Feb 9 01:52:26 2026 Received: from mail-m32124.qiye.163.com (mail-m32124.qiye.163.com [220.197.32.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8D941B78E7; Tue, 24 Dec 2024 09:54:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735034105; cv=none; b=aOvT8B2PwHF4GlvQOFBPfkE3QQqeithmn/Nu3bpm8NiDuKy+y6oE0LcrBCpKQLZ6TBCH/jgGnfA3jhmsYFxh4yYixfSTNn9/QfehJwuuzWS4pPR79I7/ajHFSJpXM1HD2CspcQTnQW607LdtVof0J1TM7iAmlvv3AGBKgMN+vh4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735034105; c=relaxed/simple; bh=CZsZ87HNH1xJepJrrvybIV+We89lMn9sGaIBxsBfbcA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=j3zAS4EqmqP/crBKcFlytq8w6T+Dunx5H3dFSMQUUtDRm9XGbAWCu3UB+dZz4vv48I/wAanLBigNER0ByNcHXIJbYSKLTUynccPWcZKy2CGQh2y8vaQn9vZ9JJ/88EflAKoEW6zGF4b+JhXXWp4wa8i2PjbR4j9+9p/7Qe7ZMUw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=ZZHptFQz; arc=none smtp.client-ip=220.197.32.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="ZZHptFQz" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 6aad4f8c; Tue, 24 Dec 2024 17:49:46 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Finley Xiao , Kever Yang , devicetree@vger.kernel.org, Conor Dooley , Rob Herring , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 16/17] arm64: dts: rockchip: add core dtsi for RK3562 Soc Date: Tue, 24 Dec 2024 17:49:19 +0800 Message-Id: <20241224094920.3821861-17-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241224094920.3821861-1-kever.yang@rock-chips.com> References: <20241224094920.3821861-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGRkfGVYfTRofHhkYSU8eT0lWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a93f812904f03afkunm6aad4f8c X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6M006AQw4ETITCEoKLFYILBA2 OU4KCyFVSlVKTEhOS0hITENMQkNNVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFCTUhIQzcG DKIM-Signature: a=rsa-sha256; b=ZZHptFQzn0tI+AX64DBQ5zj3zbhmoeJxHXJr9XjDTh7Jj5v3b6ItRX7/SXAvRYL5/jqiNWsrrT8b+xW2zZesTYKTEO/8hlWnupEgwN+Ym6eIAvLAFZ9nRHFo+d8pKc/aI5t2R2YJVWzhZupVK2esunez8B2g3hYBJbQ63P7oEQA=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=iXsVm48ou7TQ4uxZLRqNvWPlI8+MIc/Z8ryKyBiQyNg=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" From: Finley Xiao RK3562 is a Soc from Rockchip, which embedded with quad ARM Cortex-A53. Signed-off-by: Finley Xiao Signed-off-by: Kever Yang --- Changes in v2: - remove grf in cru - Update some properties order .../boot/dts/rockchip/rk3562-pinctrl.dtsi | 2352 +++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3562.dtsi | 1432 ++++++++++ 2 files changed, 3784 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3562.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi b/arch/arm64/= boot/dts/rockchip/rk3562-pinctrl.dtsi new file mode 100644 index 000000000000..b311448d77a3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi @@ -0,0 +1,2352 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + cam { + /omit-if-no-ref/ + camm0_clk0_out: camm0-clk0-out { + rockchip,pins =3D + /* camm0_clk0_out */ + <3 RK_PB2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + camm0_clk1_out: camm0-clk1-out { + rockchip,pins =3D + /* camm0_clk1_out */ + <3 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + camm1_clk0_out: camm1-clk0-out { + rockchip,pins =3D + /* camm1_clk0_out */ + <4 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + camm1_clk1_out: camm1-clk1-out { + rockchip,pins =3D + /* camm1_clk1_out */ + <4 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cam_clk2_out: cam-clk2-out { + rockchip,pins =3D + /* cam_clk2_out */ + <3 RK_PB4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cam_clk3_out: cam-clk3-out { + rockchip,pins =3D + /* cam_clk3_out */ + <3 RK_PB5 2 &pcfg_pull_none>; + }; + }; + + can0 { + /omit-if-no-ref/ + can0m0_pins: can0m0-pins { + rockchip,pins =3D + /* can0_rx_m0 */ + <3 RK_PA1 4 &pcfg_pull_none>, + /* can0_tx_m0 */ + <3 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can0m1_pins: can0m1-pins { + rockchip,pins =3D + /* can0_rx_m1 */ + <3 RK_PB7 6 &pcfg_pull_none>, + /* can0_tx_m1 */ + <3 RK_PB6 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can0m2_pins: can0m2-pins { + rockchip,pins =3D + /* can0_rx_m2 */ + <0 RK_PC7 2 &pcfg_pull_none>, + /* can0_tx_m2 */ + <0 RK_PC6 2 &pcfg_pull_none>; + }; + }; + + can1 { + /omit-if-no-ref/ + can1m0_pins: can1m0-pins { + rockchip,pins =3D + /* can1_rx_m0 */ + <1 RK_PB7 4 &pcfg_pull_none>, + /* can1_tx_m0 */ + <1 RK_PC0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can1m1_pins: can1m1-pins { + rockchip,pins =3D + /* can1_rx_m1 */ + <0 RK_PC1 4 &pcfg_pull_none>, + /* can1_tx_m1 */ + <0 RK_PC0 4 &pcfg_pull_none>; + }; + }; + + clk { + /omit-if-no-ref/ + clk_32k_in: clk-32k-in { + rockchip,pins =3D + /* clk_32k_in */ + <0 RK_PB0 1 &pcfg_pull_none>; + }; + }; + + clk0 { + /omit-if-no-ref/ + clk0_32k_out: clk0-32k-out { + rockchip,pins =3D + /* clk0_32k_out */ + <0 RK_PB0 2 &pcfg_pull_none>; + }; + }; + + clk1 { + /omit-if-no-ref/ + clk1_32k_out: clk1-32k-out { + rockchip,pins =3D + /* clk1_32k_out */ + <2 RK_PA1 3 &pcfg_pull_none>; + }; + }; + + cpu { + /omit-if-no-ref/ + cpu_pins: cpu-pins { + rockchip,pins =3D + /* cpu_avs */ + <0 RK_PB7 3 &pcfg_pull_none>; + }; + }; + + dsm { + /omit-if-no-ref/ + dsm_pins: dsm-pins { + rockchip,pins =3D + /* dsm_aud_ln */ + <1 RK_PB4 5 &pcfg_pull_none>, + /* dsm_aud_lp */ + <1 RK_PB3 5 &pcfg_pull_none>, + /* dsm_aud_rn */ + <1 RK_PB6 6 &pcfg_pull_none>, + /* dsm_aud_rp */ + <1 RK_PB5 6 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins =3D + /* emmc_d0 */ + <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins =3D + /* emmc_clk */ + <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins =3D + /* emmc_cmd */ + <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_strb: emmc-strb { + rockchip,pins =3D + /* emmc_strb */ + <1 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + eth { + /omit-if-no-ref/ + ethm0_pins: ethm0-pins { + rockchip,pins =3D + /* eth_clk_25m_out_m0 */ + <4 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + ethm1_pins: ethm1-pins { + rockchip,pins =3D + /* eth_clk_25m_out_m1 */ + <2 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspi_pins: fspi-pins { + rockchip,pins =3D + /* fspi_clk */ + <1 RK_PB1 2 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PA0 2 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PA1 2 &pcfg_pull_none>, + /* fspi_d2 */ + <1 RK_PA2 2 &pcfg_pull_none>, + /* fspi_d3 */ + <1 RK_PA3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fspi_csn0: fspi-csn0 { + rockchip,pins =3D + /* fspi_csn0 */ + <1 RK_PB0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + fspi_csn1: fspi-csn1 { + rockchip,pins =3D + /* fspi_csn1 */ + <1 RK_PB2 2 &pcfg_pull_none>; + }; + }; + + gpu { + /omit-if-no-ref/ + gpu_pins: gpu-pins { + rockchip,pins =3D + /* gpu_avs */ + <0 RK_PC0 3 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0_xfer: i2c0-xfer { + rockchip,pins =3D + /* i2c0_scl */ + <0 RK_PB1 1 &pcfg_pull_none_smt>, + /* i2c0_sda */ + <0 RK_PB2 1 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1m0_xfer: i2c1m0-xfer { + rockchip,pins =3D + /* i2c1_scl_m0 */ + <0 RK_PB3 1 &pcfg_pull_none_smt>, + /* i2c1_sda_m0 */ + <0 RK_PB4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m1_xfer: i2c1m1-xfer { + rockchip,pins =3D + /* i2c1_scl_m1 */ + <4 RK_PB4 5 &pcfg_pull_none_smt>, + /* i2c1_sda_m1 */ + <4 RK_PB5 5 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins =3D + /* i2c2_scl_m0 */ + <0 RK_PB5 1 &pcfg_pull_none_smt>, + /* i2c2_sda_m0 */ + <0 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins =3D + /* i2c2_scl_m1 */ + <3 RK_PD2 5 &pcfg_pull_none_smt>, + /* i2c2_sda_m1 */ + <3 RK_PD3 5 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins =3D + /* i2c3_scl_m0 */ + <3 RK_PA0 1 &pcfg_pull_none_smt>, + /* i2c3_sda_m0 */ + <3 RK_PA1 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins =3D + /* i2c3_scl_m1 */ + <4 RK_PA5 5 &pcfg_pull_none_smt>, + /* i2c3_sda_m1 */ + <4 RK_PA6 5 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m0_xfer: i2c4m0-xfer { + rockchip,pins =3D + /* i2c4_scl_m0 */ + <3 RK_PB6 5 &pcfg_pull_none_smt>, + /* i2c4_sda_m0 */ + <3 RK_PB7 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m1_xfer: i2c4m1-xfer { + rockchip,pins =3D + /* i2c4_scl_m1 */ + <0 RK_PA5 2 &pcfg_pull_none_smt>, + /* i2c4_sda_m1 */ + <0 RK_PA4 2 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins =3D + /* i2c5_scl_m0 */ + <3 RK_PC2 1 &pcfg_pull_none_smt>, + /* i2c5_sda_m0 */ + <3 RK_PC3 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins =3D + /* i2c5_scl_m1 */ + <1 RK_PC7 4 &pcfg_pull_none_smt>, + /* i2c5_sda_m1 */ + <1 RK_PD0 4 &pcfg_pull_none_smt>; + }; + }; + + i2s0 { + /omit-if-no-ref/ + i2s0m0_lrck: i2s0m0-lrck { + rockchip,pins =3D + /* i2s0_lrck_m0 */ + <3 RK_PA4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_mclk: i2s0m0-mclk { + rockchip,pins =3D + /* i2s0_mclk_m0 */ + <3 RK_PA2 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_sclk: i2s0m0-sclk { + rockchip,pins =3D + /* i2s0_sclk_m0 */ + <3 RK_PA3 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi0: i2s0m0-sdi0 { + rockchip,pins =3D + /* i2s0_sdi0_m0 */ + <3 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi1: i2s0m0-sdi1 { + rockchip,pins =3D + /* i2s0_sdi1_m0 */ + <3 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi2: i2s0m0-sdi2 { + rockchip,pins =3D + /* i2s0_sdi2_m0 */ + <3 RK_PA7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi3: i2s0m0-sdi3 { + rockchip,pins =3D + /* i2s0_sdi3_m0 */ + <3 RK_PA6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdo0: i2s0m0-sdo0 { + rockchip,pins =3D + /* i2s0_sdo0_m0 */ + <3 RK_PA5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdo1: i2s0m0-sdo1 { + rockchip,pins =3D + /* i2s0_sdo1_m0 */ + <3 RK_PA6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdo2: i2s0m0-sdo2 { + rockchip,pins =3D + /* i2s0_sdo2_m0 */ + <3 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdo3: i2s0m0-sdo3 { + rockchip,pins =3D + /* i2s0_sdo3_m0 */ + <3 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_lrck: i2s0m1-lrck { + rockchip,pins =3D + /* i2s0_lrck_m1 */ + <1 RK_PC4 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_mclk: i2s0m1-mclk { + rockchip,pins =3D + /* i2s0_mclk_m1 */ + <1 RK_PC6 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_sclk: i2s0m1-sclk { + rockchip,pins =3D + /* i2s0_sclk_m1 */ + <1 RK_PC5 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi0: i2s0m1-sdi0 { + rockchip,pins =3D + /* i2s0_sdi0_m1 */ + <1 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi1: i2s0m1-sdi1 { + rockchip,pins =3D + /* i2s0_sdi1_m1 */ + <1 RK_PC2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi2: i2s0m1-sdi2 { + rockchip,pins =3D + /* i2s0_sdi2_m1 */ + <1 RK_PD3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi3: i2s0m1-sdi3 { + rockchip,pins =3D + /* i2s0_sdi3_m1 */ + <1 RK_PD4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdo0: i2s0m1-sdo0 { + rockchip,pins =3D + /* i2s0_sdo0_m1 */ + <1 RK_PC3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdo1: i2s0m1-sdo1 { + rockchip,pins =3D + /* i2s0_sdo1_m1 */ + <1 RK_PD1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdo2: i2s0m1-sdo2 { + rockchip,pins =3D + /* i2s0_sdo2_m1 */ + <1 RK_PD2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdo3: i2s0m1-sdo3 { + rockchip,pins =3D + /* i2s0_sdo3_m1 */ + <2 RK_PA1 5 &pcfg_pull_none>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1m0_lrck: i2s1m0-lrck { + rockchip,pins =3D + /* i2s1_lrck_m0 */ + <3 RK_PC6 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m0_mclk: i2s1m0-mclk { + rockchip,pins =3D + /* i2s1_mclk_m0 */ + <3 RK_PC4 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m0_sclk: i2s1m0-sclk { + rockchip,pins =3D + /* i2s1_sclk_m0 */ + <3 RK_PC5 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi0: i2s1m0-sdi0 { + rockchip,pins =3D + /* i2s1_sdi0_m0 */ + <3 RK_PD0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi1: i2s1m0-sdi1 { + rockchip,pins =3D + /* i2s1_sdi1_m0 */ + <3 RK_PD1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi2: i2s1m0-sdi2 { + rockchip,pins =3D + /* i2s1_sdi2_m0 */ + <3 RK_PD2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi3: i2s1m0-sdi3 { + rockchip,pins =3D + /* i2s1_sdi3_m0 */ + <3 RK_PD3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo0: i2s1m0-sdo0 { + rockchip,pins =3D + /* i2s1_sdo0_m0 */ + <3 RK_PC7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo1: i2s1m0-sdo1 { + rockchip,pins =3D + /* i2s1_sdo1_m0 */ + <4 RK_PB4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo2: i2s1m0-sdo2 { + rockchip,pins =3D + /* i2s1_sdo2_m0 */ + <4 RK_PB5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo3: i2s1m0-sdo3 { + rockchip,pins =3D + /* i2s1_sdo3_m0 */ + <4 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_lrck: i2s1m1-lrck { + rockchip,pins =3D + /* i2s1_lrck_m1 */ + <3 RK_PB4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m1_mclk: i2s1m1-mclk { + rockchip,pins =3D + /* i2s1_mclk_m1 */ + <3 RK_PB2 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m1_sclk: i2s1m1-sclk { + rockchip,pins =3D + /* i2s1_sclk_m1 */ + <3 RK_PB3 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi0: i2s1m1-sdi0 { + rockchip,pins =3D + /* i2s1_sdi0_m1 */ + <3 RK_PC1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi1: i2s1m1-sdi1 { + rockchip,pins =3D + /* i2s1_sdi1_m1 */ + <3 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi2: i2s1m1-sdi2 { + rockchip,pins =3D + /* i2s1_sdi2_m1 */ + <3 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi3: i2s1m1-sdi3 { + rockchip,pins =3D + /* i2s1_sdi3_m1 */ + <3 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo0: i2s1m1-sdo0 { + rockchip,pins =3D + /* i2s1_sdo0_m1 */ + <3 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo1: i2s1m1-sdo1 { + rockchip,pins =3D + /* i2s1_sdo1_m1 */ + <3 RK_PB6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo2: i2s1m1-sdo2 { + rockchip,pins =3D + /* i2s1_sdo2_m1 */ + <3 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo3: i2s1m1-sdo3 { + rockchip,pins =3D + /* i2s1_sdo3_m1 */ + <3 RK_PC0 1 &pcfg_pull_none>; + }; + }; + + i2s2 { + /omit-if-no-ref/ + i2s2m0_lrck: i2s2m0-lrck { + rockchip,pins =3D + /* i2s2_lrck_m0 */ + <1 RK_PD6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins =3D + /* i2s2_mclk_m0 */ + <2 RK_PA1 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m0_sclk: i2s2m0-sclk { + rockchip,pins =3D + /* i2s2_sclk_m0 */ + <1 RK_PD5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins =3D + /* i2s2_sdi_m0 */ + <2 RK_PA0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins =3D + /* i2s2_sdo_m0 */ + <1 RK_PD7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_lrck: i2s2m1-lrck { + rockchip,pins =3D + /* i2s2_lrck_m1 */ + <4 RK_PA1 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m1_mclk: i2s2m1-mclk { + rockchip,pins =3D + /* i2s2_mclk_m1 */ + <3 RK_PD6 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m1_sclk: i2s2m1-sclk { + rockchip,pins =3D + /* i2s2_sclk_m1 */ + <4 RK_PB1 4 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m1_sdi: i2s2m1-sdi { + rockchip,pins =3D + /* i2s2_sdi_m1 */ + <3 RK_PD4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdo: i2s2m1-sdo { + rockchip,pins =3D + /* i2s2_sdo_m1 */ + <3 RK_PD5 4 &pcfg_pull_none>; + }; + }; + + isp { + /omit-if-no-ref/ + isp_pins: isp-pins { + rockchip,pins =3D + /* isp_flash_trigin */ + <3 RK_PC1 2 &pcfg_pull_none>, + /* isp_flash_trigout */ + <3 RK_PC3 2 &pcfg_pull_none>, + /* isp_prelight_trigout */ + <3 RK_PC2 2 &pcfg_pull_none>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtagm0_pins: jtagm0-pins { + rockchip,pins =3D + /* jtag_cpu_mcu_tck_m0 */ + <0 RK_PD1 2 &pcfg_pull_none>, + /* jtag_cpu_mcu_tms_m0 */ + <0 RK_PD0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm1_pins: jtagm1-pins { + rockchip,pins =3D + /* jtag_cpu_mcu_tck_m1 */ + <1 RK_PB5 2 &pcfg_pull_none>, + /* jtag_cpu_mcu_tms_m1 */ + <1 RK_PB6 2 &pcfg_pull_none>; + }; + }; + + npu { + /omit-if-no-ref/ + npu_pins: npu-pins { + rockchip,pins =3D + /* npu_avs */ + <0 RK_PC1 3 &pcfg_pull_none>; + }; + }; + + pcie20 { + /omit-if-no-ref/ + pcie20m0_pins: pcie20m0-pins { + rockchip,pins =3D + /* pcie20_clkreqn_m0 */ + <0 RK_PA6 1 &pcfg_pull_none>, + /* pcie20_perstn_m0 */ + <0 RK_PB5 2 &pcfg_pull_none>, + /* pcie20_waken_m0 */ + <0 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20m1_pins: pcie20m1-pins { + rockchip,pins =3D + /* pcie20_clkreqn_m1 */ + <3 RK_PA6 4 &pcfg_pull_none>, + /* pcie20_perstn_m1 */ + <3 RK_PB0 4 &pcfg_pull_none>, + /* pcie20_waken_m1 */ + <3 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20_buttonrstn: pcie20-buttonrstn { + rockchip,pins =3D + /* pcie20_buttonrstn */ + <0 RK_PB0 3 &pcfg_pull_none>; + }; + }; + + pdm { + /omit-if-no-ref/ + pdmm0_clk0: pdmm0-clk0 { + rockchip,pins =3D + /* pdm_clk0_m0 */ + <3 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_clk1: pdmm0-clk1 { + rockchip,pins =3D + /* pdm_clk1_m0 */ + <3 RK_PA2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi0: pdmm0-sdi0 { + rockchip,pins =3D + /* pdm_sdi0_m0 */ + <3 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi1: pdmm0-sdi1 { + rockchip,pins =3D + /* pdm_sdi1_m0 */ + <3 RK_PB0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi2: pdmm0-sdi2 { + rockchip,pins =3D + /* pdm_sdi2_m0 */ + <3 RK_PA7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi3: pdmm0-sdi3 { + rockchip,pins =3D + /* pdm_sdi3_m0 */ + <3 RK_PA0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk0: pdmm1-clk0 { + rockchip,pins =3D + /* pdm_clk0_m1 */ + <4 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk1: pdmm1-clk1 { + rockchip,pins =3D + /* pdm_clk1_m1 */ + <4 RK_PB1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi0: pdmm1-sdi0 { + rockchip,pins =3D + /* pdm_sdi0_m1 */ + <4 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi1: pdmm1-sdi1 { + rockchip,pins =3D + /* pdm_sdi1_m1 */ + <4 RK_PB0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi2: pdmm1-sdi2 { + rockchip,pins =3D + /* pdm_sdi2_m1 */ + <4 RK_PA5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi3: pdmm1-sdi3 { + rockchip,pins =3D + /* pdm_sdi3_m1 */ + <4 RK_PA6 4 &pcfg_pull_none>; + }; + }; + + pmic { + /omit-if-no-ref/ + pmic_int: pmic-int { + rockchip,pins =3D + <0 RK_PA3 0 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + soc_slppin_gpio: soc-slppin-gpio { + rockchip,pins =3D + <0 RK_PA2 0 &pcfg_output_low>; + }; + + /omit-if-no-ref/ + soc_slppin_slp: soc-slppin-slp { + rockchip,pins =3D + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + pmu { + /omit-if-no-ref/ + pmu_pins: pmu-pins { + rockchip,pins =3D + /* pmu_debug */ + <0 RK_PA5 3 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_pins: pwm0m0-pins { + rockchip,pins =3D + /* pwm0_m0 */ + <0 RK_PC3 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm0m1_pins: pwm0m1-pins { + rockchip,pins =3D + /* pwm0_m1 */ + <1 RK_PC5 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_pins: pwm1m0-pins { + rockchip,pins =3D + /* pwm1_m0 */ + <0 RK_PC4 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm1m1_pins: pwm1m1-pins { + rockchip,pins =3D + /* pwm1_m1 */ + <1 RK_PC6 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins =3D + /* pwm2_m0 */ + <0 RK_PC5 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm2m1_pins: pwm2m1-pins { + rockchip,pins =3D + /* pwm2_m1 */ + <1 RK_PC7 3 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm3 { + /omit-if-no-ref/ + pwm3m0_pins: pwm3m0-pins { + rockchip,pins =3D + /* pwm3_m0 */ + <0 RK_PA7 1 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm3m1_pins: pwm3m1-pins { + rockchip,pins =3D + /* pwm3_m1 */ + <1 RK_PD0 3 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4m0_pins: pwm4m0-pins { + rockchip,pins =3D + /* pwm4_m0 */ + <0 RK_PB7 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm4m1_pins: pwm4m1-pins { + rockchip,pins =3D + /* pwm4_m1 */ + <1 RK_PD1 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5m0_pins: pwm5m0-pins { + rockchip,pins =3D + /* pwm5_m0 */ + <0 RK_PC2 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm5m1_pins: pwm5m1-pins { + rockchip,pins =3D + /* pwm5_m1 */ + <1 RK_PD2 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6m0_pins: pwm6m0-pins { + rockchip,pins =3D + /* pwm6_m0 */ + <0 RK_PC1 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm6m1_pins: pwm6m1-pins { + rockchip,pins =3D + /* pwm6_m1 */ + <1 RK_PD3 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7m0_pins: pwm7m0-pins { + rockchip,pins =3D + /* pwm7_m0 */ + <0 RK_PC0 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm7m1_pins: pwm7m1-pins { + rockchip,pins =3D + /* pwm7_m1 */ + <1 RK_PD4 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm8 { + /omit-if-no-ref/ + pwm8m0_pins: pwm8m0-pins { + rockchip,pins =3D + /* pwm8_m0 */ + <3 RK_PA4 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm8m1_pins: pwm8m1-pins { + rockchip,pins =3D + /* pwm8_m1 */ + <1 RK_PC1 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm9 { + /omit-if-no-ref/ + pwm9m0_pins: pwm9m0-pins { + rockchip,pins =3D + /* pwm9_m0 */ + <3 RK_PA5 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm9m1_pins: pwm9m1-pins { + rockchip,pins =3D + /* pwm9_m1 */ + <1 RK_PC2 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm10 { + /omit-if-no-ref/ + pwm10m0_pins: pwm10m0-pins { + rockchip,pins =3D + /* pwm10_m0 */ + <1 RK_PB5 5 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm10m1_pins: pwm10m1-pins { + rockchip,pins =3D + /* pwm10_m1 */ + <1 RK_PC3 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm11 { + /omit-if-no-ref/ + pwm11m0_pins: pwm11m0-pins { + rockchip,pins =3D + /* pwm11_m0 */ + <1 RK_PB6 5 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm11m1_pins: pwm11m1-pins { + rockchip,pins =3D + /* pwm11_m1 */ + <1 RK_PC4 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm12 { + /omit-if-no-ref/ + pwm12m0_pins: pwm12m0-pins { + rockchip,pins =3D + /* pwm12_m0 */ + <4 RK_PA1 4 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm12m1_pins: pwm12m1-pins { + rockchip,pins =3D + /* pwm12_m1 */ + <3 RK_PB4 5 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm13 { + /omit-if-no-ref/ + pwm13m0_pins: pwm13m0-pins { + rockchip,pins =3D + /* pwm13_m0 */ + <4 RK_PA4 3 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm13m1_pins: pwm13m1-pins { + rockchip,pins =3D + /* pwm13_m1 */ + <3 RK_PB5 5 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm14 { + /omit-if-no-ref/ + pwm14m0_pins: pwm14m0-pins { + rockchip,pins =3D + /* pwm14_m0 */ + <3 RK_PC5 4 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm14m1_pins: pwm14m1-pins { + rockchip,pins =3D + /* pwm14_m1 */ + <1 RK_PD7 5 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm15 { + /omit-if-no-ref/ + pwm15m0_pins: pwm15m0-pins { + rockchip,pins =3D + /* pwm15_m0 */ + <3 RK_PC6 4 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm15m1_pins: pwm15m1-pins { + rockchip,pins =3D + /* pwm15_m1 */ + <2 RK_PA0 5 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwr { + /omit-if-no-ref/ + pwr_pins: pwr-pins { + rockchip,pins =3D + /* pwr_ctrl0 */ + <0 RK_PA2 1 &pcfg_pull_none>, + /* pwr_ctrl1 */ + <0 RK_PA3 1 &pcfg_pull_none>; + }; + }; + + ref { + /omit-if-no-ref/ + ref_pins: ref-pins { + rockchip,pins =3D + /* ref_clk_out */ + <0 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + rgmii { + /omit-if-no-ref/ + rgmiim0_miim: rgmiim0-miim { + rockchip,pins =3D + /* rgmii_mdc_m0 */ + <4 RK_PB2 2 &pcfg_pull_none>, + /* rgmii_mdio_m0 */ + <4 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_rx_er: rgmiim0-rx_er { + rockchip,pins =3D + /* rgmii_rxer_m0 */ + <4 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_rx_bus2: rgmiim0-rx_bus2 { + rockchip,pins =3D + /* rgmii_rxd0_m0 */ + <4 RK_PA5 2 &pcfg_pull_none>, + /* rgmii_rxd1_m0 */ + <4 RK_PA6 2 &pcfg_pull_none>, + /* rgmii_rxdv_m0 */ + <4 RK_PA7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_tx_bus2: rgmiim0-tx_bus2 { + rockchip,pins =3D + /* rgmii_txd0_m0 */ + <4 RK_PA2 2 &pcfg_pull_none>, + /* rgmii_txd1_m0 */ + <4 RK_PA3 2 &pcfg_pull_none>, + /* rgmii_txen_m0 */ + <4 RK_PA4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_rgmii_clk: rgmiim0-rgmii_clk { + rockchip,pins =3D + /* rgmii_rxclk_m0 */ + <4 RK_PA1 2 &pcfg_pull_none>, + /* rgmii_txclk_m0 */ + <3 RK_PD6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_rgmii_bus: rgmiim0-rgmii_bus { + rockchip,pins =3D + /* rgmii_rxd2_m0 */ + <3 RK_PD7 2 &pcfg_pull_none>, + /* rgmii_rxd3_m0 */ + <4 RK_PA0 2 &pcfg_pull_none>, + /* rgmii_txd2_m0 */ + <3 RK_PD4 2 &pcfg_pull_none>, + /* rgmii_txd3_m0 */ + <3 RK_PD5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_clk: rgmiim0-clk { + rockchip,pins =3D + /* rgmiim0_clk */ + <4 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_miim: rgmiim1-miim { + rockchip,pins =3D + /* rgmii_mdc_m1 */ + <1 RK_PC7 2 &pcfg_pull_none>, + /* rgmii_mdio_m1 */ + <1 RK_PD0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_rx_er: rgmiim1-rx_er { + rockchip,pins =3D + /* rgmii_rxer_m1 */ + <2 RK_PA0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_rx_bus2: rgmiim1-rx_bus2 { + rockchip,pins =3D + /* rgmii_rxd0_m1 */ + <1 RK_PD4 2 &pcfg_pull_none>, + /* rgmii_rxd1_m1 */ + <1 RK_PD7 2 &pcfg_pull_none>, + /* rgmii_rxdv_m1 */ + <1 RK_PD6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_tx_bus2: rgmiim1-tx_bus2 { + rockchip,pins =3D + /* rgmii_txd0_m1 */ + <1 RK_PD1 2 &pcfg_pull_none>, + /* rgmii_txd1_m1 */ + <1 RK_PD2 2 &pcfg_pull_none>, + /* rgmii_txen_m1 */ + <1 RK_PD3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_rgmii_clk: rgmiim1-rgmii_clk { + rockchip,pins =3D + /* rgmii_rxclk_m1 */ + <1 RK_PC6 2 &pcfg_pull_none>, + /* rgmii_txclk_m1 */ + <1 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_rgmii_bus: rgmiim1-rgmii_bus { + rockchip,pins =3D + /* rgmii_rxd2_m1 */ + <1 RK_PC4 2 &pcfg_pull_none>, + /* rgmii_rxd3_m1 */ + <1 RK_PC5 2 &pcfg_pull_none>, + /* rgmii_txd2_m1 */ + <1 RK_PC1 2 &pcfg_pull_none>, + /* rgmii_txd3_m1 */ + <1 RK_PC2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_clk: rgmiim1-clk { + rockchip,pins =3D + /* rgmiim1_clk */ + <1 RK_PD5 2 &pcfg_pull_none>; + }; + }; + + rmii { + /omit-if-no-ref/ + rmii_pins: rmii-pins { + rockchip,pins =3D + /* rmii_clk */ + <1 RK_PD5 5 &pcfg_pull_none>, + /* rmii_mdc */ + <1 RK_PC7 5 &pcfg_pull_none>, + /* rmii_mdio */ + <1 RK_PD0 5 &pcfg_pull_none>, + /* rmii_rxd0 */ + <1 RK_PD4 5 &pcfg_pull_none>, + /* rmii_rxd1 */ + <1 RK_PD7 6 &pcfg_pull_none>, + /* rmii_rxdv_crs */ + <1 RK_PD6 5 &pcfg_pull_none>, + /* rmii_rxer */ + <2 RK_PA0 6 &pcfg_pull_none>, + /* rmii_txd0 */ + <1 RK_PD1 5 &pcfg_pull_none>, + /* rmii_txd1 */ + <1 RK_PD2 5 &pcfg_pull_none>, + /* rmii_txen */ + <1 RK_PD3 5 &pcfg_pull_none>; + }; + }; + + sdmmc0 { + /omit-if-no-ref/ + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins =3D + /* sdmmc0_d0 */ + <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d1 */ + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d2 */ + <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d3 */ + <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_clk: sdmmc0-clk { + rockchip,pins =3D + /* sdmmc0_clk */ + <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins =3D + /* sdmmc0_cmd */ + <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_det: sdmmc0-det { + rockchip,pins =3D + /* sdmmc0_detn */ + <0 RK_PA4 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc0_pwren: sdmmc0-pwren { + rockchip,pins =3D + /* sdmmc0_pwren */ + <0 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins =3D + /* sdmmc1_d0 */ + <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d1 */ + <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d2 */ + <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d3 */ + <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins =3D + /* sdmmc1_clk */ + <1 RK_PC6 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins =3D + /* sdmmc1_cmd */ + <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_det: sdmmc1-det { + rockchip,pins =3D + /* sdmmc1_detn */ + <1 RK_PD0 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc1_pwren: sdmmc1-pwren { + rockchip,pins =3D + /* sdmmc1_pwren */ + <1 RK_PC7 1 &pcfg_pull_none>; + }; + }; + + spdif { + /omit-if-no-ref/ + spdifm0_pins: spdifm0-pins { + rockchip,pins =3D + /* spdif_tx_m0 */ + <3 RK_PA1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm1_pins: spdifm1-pins { + rockchip,pins =3D + /* spdif_tx_m1 */ + <0 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm2_pins: spdifm2-pins { + rockchip,pins =3D + /* spdif_tx_m2 */ + <1 RK_PB7 2 &pcfg_pull_none>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0m0_pins: spi0m0-pins { + rockchip,pins =3D + /* spi0_clk_m0 */ + <0 RK_PC3 3 &pcfg_pull_none_drv_level_3>, + /* spi0_miso_m0 */ + <0 RK_PC5 3 &pcfg_pull_none_drv_level_3>, + /* spi0_mosi_m0 */ + <0 RK_PC4 3 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi0m0_csn0: spi0m0-csn0 { + rockchip,pins =3D + /* spi0m0_csn0 */ + <0 RK_PC2 3 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi0m0_csn1: spi0m0-csn1 { + rockchip,pins =3D + /* spi0m0_csn1 */ + <0 RK_PB7 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi0m1_pins: spi0m1-pins { + rockchip,pins =3D + /* spi0_clk_m1 */ + <3 RK_PB5 4 &pcfg_pull_none_drv_level_3>, + /* spi0_miso_m1 */ + <3 RK_PC0 4 &pcfg_pull_none_drv_level_3>, + /* spi0_mosi_m1 */ + <3 RK_PB4 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi0m1_csn0: spi0m1-csn0 { + rockchip,pins =3D + /* spi0m1_csn0 */ + <3 RK_PB7 4 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi0m1_csn1: spi0m1-csn1 { + rockchip,pins =3D + /* spi0m1_csn1 */ + <3 RK_PB6 4 &pcfg_pull_none_drv_level_3>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1m0_pins: spi1m0-pins { + rockchip,pins =3D + /* spi1_clk_m0 */ + <3 RK_PD6 4 &pcfg_pull_none_drv_level_3>, + /* spi1_miso_m0 */ + <4 RK_PA3 4 &pcfg_pull_none_drv_level_3>, + /* spi1_mosi_m0 */ + <4 RK_PA2 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi1m0_csn0: spi1m0-csn0 { + rockchip,pins =3D + /* spi1m0_csn0 */ + <3 RK_PD7 4 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi1m0_csn1: spi1m0-csn1 { + rockchip,pins =3D + /* spi1m0_csn1 */ + <4 RK_PA0 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi1m1_pins: spi1m1-pins { + rockchip,pins =3D + /* spi1_clk_m1 */ + <1 RK_PC0 4 &pcfg_pull_none_drv_level_3>, + /* spi1_miso_m1 */ + <1 RK_PB4 4 &pcfg_pull_none_drv_level_3>, + /* spi1_mosi_m1 */ + <1 RK_PB3 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi1m1_csn0: spi1m1-csn0 { + rockchip,pins =3D + /* spi1m1_csn0 */ + <1 RK_PB6 4 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi1m1_csn1: spi1m1-csn1 { + rockchip,pins =3D + /* spi1m1_csn1 */ + <1 RK_PB5 4 &pcfg_pull_none_drv_level_3>; + }; + }; + + spi2 { + /omit-if-no-ref/ + spi2m0_pins: spi2m0-pins { + rockchip,pins =3D + /* spi2_clk_m0 */ + <4 RK_PB6 4 &pcfg_pull_none_drv_level_3>, + /* spi2_miso_m0 */ + <3 RK_PD2 4 &pcfg_pull_none_drv_level_3>, + /* spi2_mosi_m0 */ + <3 RK_PD3 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi2m0_csn0: spi2m0-csn0 { + rockchip,pins =3D + /* spi2m0_csn0 */ + <4 RK_PB5 4 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi2m0_csn1: spi2m0-csn1 { + rockchip,pins =3D + /* spi2m0_csn1 */ + <4 RK_PB4 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi2m1_pins: spi2m1-pins { + rockchip,pins =3D + /* spi2_clk_m1 */ + <2 RK_PA1 4 &pcfg_pull_none_drv_level_3>, + /* spi2_miso_m1 */ + <2 RK_PA0 4 &pcfg_pull_none_drv_level_3>, + /* spi2_mosi_m1 */ + <1 RK_PD7 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi2m1_csn0: spi2m1-csn0 { + rockchip,pins =3D + /* spi2m1_csn0 */ + <1 RK_PD6 4 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi2m1_csn1: spi2m1-csn1 { + rockchip,pins =3D + /* spi2m1_csn1 */ + <1 RK_PD5 4 &pcfg_pull_none_drv_level_3>; + }; + }; + + tsadc { + /omit-if-no-ref/ + tsadcm0_pins: tsadcm0-pins { + rockchip,pins =3D + /* tsadc_shut_m0 */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadcm1_pins: tsadcm1-pins { + rockchip,pins =3D + /* tsadc_shut_m1 */ + <0 RK_PA2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadc_shut_org: tsadc-shut-org { + rockchip,pins =3D + /* tsadc_shut_org */ + <0 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0m0_xfer: uart0m0-xfer { + rockchip,pins =3D + /* uart0_rx_m0 */ + <0 RK_PD0 1 &pcfg_pull_up>, + /* uart0_tx_m0 */ + <0 RK_PD1 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m1_xfer: uart0m1-xfer { + rockchip,pins =3D + /* uart0_rx_m1 */ + <1 RK_PB3 2 &pcfg_pull_up>, + /* uart0_tx_m1 */ + <1 RK_PB4 2 &pcfg_pull_up>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins =3D + /* uart1_rx_m0 */ + <1 RK_PD1 1 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <1 RK_PD2 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m0_ctsn: uart1m0-ctsn { + rockchip,pins =3D + /* uart1m0_ctsn */ + <1 RK_PD4 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1m0_rtsn: uart1m0-rtsn { + rockchip,pins =3D + /* uart1m0_rtsn */ + <1 RK_PD3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins =3D + /* uart1_rx_m1 */ + <4 RK_PA6 3 &pcfg_pull_up>, + /* uart1_tx_m1 */ + <4 RK_PA5 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_ctsn: uart1m1-ctsn { + rockchip,pins =3D + /* uart1m1_ctsn */ + <4 RK_PB0 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1m1_rtsn: uart1m1-rtsn { + rockchip,pins =3D + /* uart1m1_rtsn */ + <4 RK_PA7 3 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins =3D + /* uart2_rx_m0 */ + <0 RK_PC1 1 &pcfg_pull_up>, + /* uart2_tx_m0 */ + <0 RK_PC0 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m0_ctsn: uart2m0-ctsn { + rockchip,pins =3D + /* uart2m0_ctsn */ + <0 RK_PC2 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m0_rtsn: uart2m0-rtsn { + rockchip,pins =3D + /* uart2m0_rtsn */ + <0 RK_PC3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins =3D + /* uart2_rx_m1 */ + <3 RK_PA1 2 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <3 RK_PA0 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_ctsn: uart2m1-ctsn { + rockchip,pins =3D + /* uart2m1_ctsn */ + <3 RK_PA2 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m1_rtsn: uart2m1-rtsn { + rockchip,pins =3D + /* uart2m1_rtsn */ + <3 RK_PA3 2 &pcfg_pull_none>; + }; + }; + + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins =3D + /* uart3_rx_m0 */ + <4 RK_PB5 6 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <4 RK_PB4 6 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m0_ctsn: uart3m0-ctsn { + rockchip,pins =3D + /* uart3m0_ctsn */ + <4 RK_PB6 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart3m0_rtsn: uart3m0-rtsn { + rockchip,pins =3D + /* uart3m0_rtsn */ + <3 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3m1_xfer: uart3m1-xfer { + rockchip,pins =3D + /* uart3_rx_m1 */ + <3 RK_PC0 3 &pcfg_pull_up>, + /* uart3_tx_m1 */ + <3 RK_PB7 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m1_ctsn: uart3m1-ctsn { + rockchip,pins =3D + /* uart3m1_ctsn */ + <3 RK_PB6 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart3m1_rtsn: uart3m1-rtsn { + rockchip,pins =3D + /* uart3m1_rtsn */ + <3 RK_PC1 3 &pcfg_pull_none>; + }; + }; + + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins =3D + /* uart4_rx_m0 */ + <3 RK_PD1 3 &pcfg_pull_up>, + /* uart4_tx_m0 */ + <3 RK_PD0 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m0_ctsn: uart4m0-ctsn { + rockchip,pins =3D + /* uart4m0_ctsn */ + <3 RK_PC5 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart4m0_rtsn: uart4m0-rtsn { + rockchip,pins =3D + /* uart4m0_rtsn */ + <3 RK_PC6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4m1_xfer: uart4m1-xfer { + rockchip,pins =3D + /* uart4_rx_m1 */ + <1 RK_PD5 3 &pcfg_pull_up>, + /* uart4_tx_m1 */ + <1 RK_PD6 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m1_ctsn: uart4m1-ctsn { + rockchip,pins =3D + /* uart4m1_ctsn */ + <2 RK_PA0 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart4m1_rtsn: uart4m1-rtsn { + rockchip,pins =3D + /* uart4m1_rtsn */ + <1 RK_PD7 3 &pcfg_pull_none>; + }; + }; + + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins =3D + /* uart5_rx_m0 */ + <1 RK_PB7 3 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <1 RK_PC0 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins =3D + /* uart5m0_ctsn */ + <1 RK_PB5 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins =3D + /* uart5m0_rtsn */ + <1 RK_PB6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_xfer: uart5m1-xfer { + rockchip,pins =3D + /* uart5_rx_m1 */ + <3 RK_PA7 5 &pcfg_pull_up>, + /* uart5_tx_m1 */ + <3 RK_PA6 5 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m1_ctsn: uart5m1-ctsn { + rockchip,pins =3D + /* uart5m1_ctsn */ + <3 RK_PA0 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5m1_rtsn: uart5m1-rtsn { + rockchip,pins =3D + /* uart5m1_rtsn */ + <3 RK_PA1 5 &pcfg_pull_none>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m0_xfer: uart6m0-xfer { + rockchip,pins =3D + /* uart6_rx_m0 */ + <0 RK_PC7 1 &pcfg_pull_up>, + /* uart6_tx_m0 */ + <0 RK_PC6 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m0_ctsn: uart6m0-ctsn { + rockchip,pins =3D + /* uart6m0_ctsn */ + <0 RK_PC4 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart6m0_rtsn: uart6m0-rtsn { + rockchip,pins =3D + /* uart6m0_rtsn */ + <0 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m1_xfer: uart6m1-xfer { + rockchip,pins =3D + /* uart6_rx_m1 */ + <4 RK_PB0 5 &pcfg_pull_up>, + /* uart6_tx_m1 */ + <4 RK_PA7 5 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m1_ctsn: uart6m1-ctsn { + rockchip,pins =3D + /* uart6m1_ctsn */ + <4 RK_PA2 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart6m1_rtsn: uart6m1-rtsn { + rockchip,pins =3D + /* uart6m1_rtsn */ + <4 RK_PA3 3 &pcfg_pull_none>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m0_xfer: uart7m0-xfer { + rockchip,pins =3D + /* uart7_rx_m0 */ + <3 RK_PC7 3 &pcfg_pull_up>, + /* uart7_tx_m0 */ + <3 RK_PC4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m0_ctsn: uart7m0-ctsn { + rockchip,pins =3D + /* uart7m0_ctsn */ + <3 RK_PD2 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart7m0_rtsn: uart7m0-rtsn { + rockchip,pins =3D + /* uart7m0_rtsn */ + <3 RK_PD3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m1_xfer: uart7m1-xfer { + rockchip,pins =3D + /* uart7_rx_m1 */ + <1 RK_PB3 3 &pcfg_pull_up>, + /* uart7_tx_m1 */ + <1 RK_PB4 3 &pcfg_pull_up>; + }; + }; + + uart8 { + /omit-if-no-ref/ + uart8m0_xfer: uart8m0-xfer { + rockchip,pins =3D + /* uart8_rx_m0 */ + <3 RK_PB3 3 &pcfg_pull_up>, + /* uart8_tx_m0 */ + <3 RK_PB2 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m0_ctsn: uart8m0-ctsn { + rockchip,pins =3D + /* uart8m0_ctsn */ + <3 RK_PB4 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart8m0_rtsn: uart8m0-rtsn { + rockchip,pins =3D + /* uart8m0_rtsn */ + <3 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m1_xfer: uart8m1-xfer { + rockchip,pins =3D + /* uart8_rx_m1 */ + <3 RK_PD5 3 &pcfg_pull_up>, + /* uart8_tx_m1 */ + <3 RK_PD4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m1_ctsn: uart8m1-ctsn { + rockchip,pins =3D + /* uart8m1_ctsn */ + <3 RK_PD7 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart8m1_rtsn: uart8m1-rtsn { + rockchip,pins =3D + /* uart8m1_rtsn */ + <4 RK_PA0 3 &pcfg_pull_none>; + }; + }; + + uart9 { + /omit-if-no-ref/ + uart9m0_xfer: uart9m0-xfer { + rockchip,pins =3D + /* uart9_rx_m0 */ + <4 RK_PB3 3 &pcfg_pull_up>, + /* uart9_tx_m0 */ + <4 RK_PB2 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m0_ctsn: uart9m0-ctsn { + rockchip,pins =3D + /* uart9m0_ctsn */ + <4 RK_PB4 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart9m0_rtsn: uart9m0-rtsn { + rockchip,pins =3D + /* uart9m0_rtsn */ + <4 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m1_xfer: uart9m1-xfer { + rockchip,pins =3D + /* uart9_rx_m1 */ + <3 RK_PC3 3 &pcfg_pull_up>, + /* uart9_tx_m1 */ + <3 RK_PC2 3 &pcfg_pull_up>; + }; + }; + + vo { + /omit-if-no-ref/ + vo_pins: vo-pins { + rockchip,pins =3D + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d0 */ + <4 RK_PA4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d1 */ + <4 RK_PA5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d2 */ + <4 RK_PB2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d8 */ + <4 RK_PA6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d9 */ + <4 RK_PA7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d16 */ + <4 RK_PB0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d17 */ + <4 RK_PB1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d18 */ + <4 RK_PB3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; + }; + }; +}; + +/* + * This part is edited handly. + */ +&pinctrl { + vo { + /omit-if-no-ref/ + bt1120_pins: bt1120-pins { + rockchip,pins =3D + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + bt656_pins: bt656-pins { + rockchip,pins =3D + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + rgb3x8_pins_m0: rgb3x8-pins-m0 { + rockchip,pins =3D + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + rgb3x8_pins_m1: rgb3x8-pins-m1 { + rockchip,pins =3D + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + rgb565_pins: rgb565-pins { + rockchip,pins =3D + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + rgb666_pins: rgb666-pins { + rockchip,pins =3D + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d2 */ + <4 RK_PB2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d18 */ + <4 RK_PB3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts= /rockchip/rk3562.dtsi new file mode 100644 index 000000000000..c32c737b7004 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -0,0 +1,1432 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible =3D "rockchip,rk3562"; + + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; + gpio0 =3D &gpio0; + gpio1 =3D &gpio1; + gpio2 =3D &gpio2; + gpio3 =3D &gpio3; + gpio4 =3D &gpio4; + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c2 =3D &i2c2; + i2c3 =3D &i2c3; + i2c4 =3D &i2c4; + i2c5 =3D &i2c5; + serial0 =3D &uart0; + serial1 =3D &uart1; + serial2 =3D &uart2; + serial3 =3D &uart3; + serial4 =3D &uart4; + serial5 =3D &uart5; + serial6 =3D &uart6; + serial7 =3D &uart7; + serial8 =3D &uart8; + serial9 =3D &uart9; + spi0 =3D &spi0; + spi1 =3D &spi1; + spi2 =3D &spi2; + spi3 =3D &sfc; + }; + + xin32k: clock-xin32k { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + clock-output-names =3D "xin32k"; + }; + + xin24m: clock-xin24m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "xin24m"; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + clocks =3D <&scmi_clk ARMCLK>; + cpu-idle-states =3D <&CPU_SLEEP>; + operating-points-v2 =3D <&cpu0_opp_table>; + #cooling-cells =3D <2>; + dynamic-power-coefficient =3D <138>; + }; + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x1>; + enable-method =3D "psci"; + clocks =3D <&scmi_clk ARMCLK>; + cpu-idle-states =3D <&CPU_SLEEP>; + operating-points-v2 =3D <&cpu0_opp_table>; + #cooling-cells =3D <2>; + dynamic-power-coefficient =3D <138>; + }; + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x2>; + enable-method =3D "psci"; + clocks =3D <&scmi_clk ARMCLK>; + cpu-idle-states =3D <&CPU_SLEEP>; + operating-points-v2 =3D <&cpu0_opp_table>; + #cooling-cells =3D <2>; + dynamic-power-coefficient =3D <138>; + }; + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x3>; + enable-method =3D "psci"; + clocks =3D <&scmi_clk ARMCLK>; + cpu-idle-states =3D <&CPU_SLEEP>; + operating-points-v2 =3D <&cpu0_opp_table>; + #cooling-cells =3D <2>; + dynamic-power-coefficient =3D <138>; + }; + + idle-states { + entry-method =3D "psci"; + CPU_SLEEP: cpu-sleep { + compatible =3D "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param =3D <0x0010000>; + entry-latency-us =3D <120>; + exit-latency-us =3D <250>; + min-residency-us =3D <900>; + }; + }; + }; + + cpu0_opp_table: opp-table-cpu0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz =3D /bits/ 64 <408000000>; + opp-microvolt =3D <825000 825000 1150000>; + clock-latency-ns =3D <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + opp-microvolt =3D <825000 825000 1150000>; + clock-latency-ns =3D <40000>; + }; + opp-816000000 { + opp-hz =3D /bits/ 64 <816000000>; + opp-microvolt =3D <825000 825000 1150000>; + clock-latency-ns =3D <40000>; + }; + opp-1008000000 { + opp-hz =3D /bits/ 64 <1008000000>; + opp-microvolt =3D <850000 850000 1150000>; + clock-latency-ns =3D <40000>; + }; + opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + opp-microvolt =3D <925000 925000 1150000>; + clock-latency-ns =3D <40000>; + }; + opp-1416000000 { + opp-hz =3D /bits/ 64 <1416000000>; + opp-microvolt =3D <1000000 1000000 1150000>; + clock-latency-ns =3D <40000>; + }; + opp-1608000000 { + opp-supported-hw =3D <0xf9 0xffff>; + opp-hz =3D /bits/ 64 <1608000000>; + opp-microvolt =3D <1037500 1037500 1150000>; + clock-latency-ns =3D <40000>; + }; + opp-1800000000 { + opp-hz =3D /bits/ 64 <1800000000>; + opp-microvolt =3D <1125000 1125000 1150000>; + clock-latency-ns =3D <40000>; + }; + opp-2016000000 { + opp-hz =3D /bits/ 64 <2016000000>; + opp-microvolt =3D <1150000 1150000 1150000>; + clock-latency-ns =3D <40000>; + }; + + }; + + arm_pmu: arm-pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D , + , + , + ; + interrupt-affinity =3D <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + firmware { + scmi: scmi { + compatible =3D "arm,scmi-smc"; + shmem =3D <&scmi_shmem>; + arm,smc-id =3D <0x82000010>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_clk: protocol@14 { + reg =3D <0x14>; + #clock-cells =3D <1>; + }; + }; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + scmi_shmem: scmi-shmem@10f000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x0010f000 0x0 0x100>; + }; + + usbdrd_dwc3: usb@fe500000 { + compatible =3D "rockchip,rk3562-dwc3", "snps,dwc3"; + reg =3D <0x0 0xfe500000 0x0 0x400000>; + clocks =3D <&cru CLK_USB3OTG_REF>, <&cru CLK_USB3OTG_SUSPEND>, + <&cru ACLK_USB3OTG>, <&cru PCLK_PHP>; + clock-names =3D "ref_clk", "suspend_clk", "bus_clk", "pipe"; + interrupts =3D ; + power-domains =3D <&power RK3562_PD_PHP>; + resets =3D <&cru SRST_USB3OTG>; + dr_mode =3D "otg"; + phys =3D <&u2phy_otg>; + phy-names =3D "usb2-phy"; + phy_type =3D "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + status =3D "disabled"; + }; + + gic: interrupt-controller@fe901000 { + compatible =3D "arm,gic-400"; + #interrupt-cells =3D <3>; + #address-cells =3D <0>; + interrupt-controller; + reg =3D <0x0 0xfe901000 0 0x1000>, + <0x0 0xfe902000 0 0x2000>, + <0x0 0xfe904000 0 0x2000>, + <0x0 0xfe906000 0 0x2000>; + interrupts =3D ; + }; + + usb_host0_ehci: usb@fed00000 { + compatible =3D "generic-ehci"; + reg =3D <0x0 0xfed00000 0x0 0x40000>; + interrupts =3D ; + clocks =3D <&cru HCLK_USB2HOST>, <&cru HCLK_USB2HOST_ARB>, + <&u2phy>; + phys =3D <&u2phy_host>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + usb_host0_ohci: usb@fed40000 { + compatible =3D "generic-ohci"; + reg =3D <0x0 0xfed40000 0x0 0x40000>; + interrupts =3D ; + clocks =3D <&cru HCLK_USB2HOST>, <&cru HCLK_USB2HOST_ARB>, + <&u2phy>; + phys =3D <&u2phy_host>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + qos_dma2ddr: qos@fee03800 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee03800 0x0 0x20>; + }; + + qos_mcu: qos@fee10000 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee10000 0x0 0x20>; + }; + + qos_dft_apb: qos@fee10100 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee10100 0x0 0x20>; + }; + + qos_gmac: qos@fee10200 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee10200 0x0 0x20>; + }; + + qos_mac100: qos@fee10300 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee10300 0x0 0x20>; + }; + + qos_dcf: qos@fee10400 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee10400 0x0 0x20>; + }; + + qos_cpu: qos@fee20000 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee20000 0x0 0x20>; + }; + + qos_gpu: qos@fee30000 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee30000 0x0 0x20>; + }; + + qos_npu: qos@fee40000 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee40000 0x0 0x20>; + }; + + qos_rkvdec: qos@fee50000 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee50000 0x0 0x20>; + }; + + qos_vepu: qos@fee60000 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee60000 0x0 0x20>; + }; + + qos_isp: qos@fee70000 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee70000 0x0 0x20>; + }; + + qos_vicap: qos@fee70100 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee70100 0x0 0x20>; + }; + + qos_vop: qos@fee80000 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee80000 0x0 0x20>; + }; + + qos_jpeg: qos@fee90000 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee90000 0x0 0x20>; + }; + + qos_rga_rd: qos@fee90100 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee90100 0x0 0x20>; + }; + + qos_rga_wr: qos@fee90200 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee90200 0x0 0x20>; + }; + + qos_pcie: qos@feea0000 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfeea0000 0x0 0x20>; + }; + + qos_usb3: qos@feea0100 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfeea0100 0x0 0x20>; + }; + + qos_crypto_apb: qos@feeb0000 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfeeb0000 0x0 0x20>; + }; + + qos_crypto: qos@feeb0100 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfeeb0100 0x0 0x20>; + }; + + qos_dmac: qos@feeb0200 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfeeb0200 0x0 0x20>; + }; + + qos_emmc: qos@feeb0300 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfeeb0300 0x0 0x20>; + }; + + qos_fspi: qos@feeb0400 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfeeb0400 0x0 0x20>; + }; + + qos_rkdma: qos@feeb0500 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfeeb0500 0x0 0x20>; + }; + + qos_sdmmc0: qos@feeb0600 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfeeb0600 0x0 0x20>; + }; + + qos_sdmmc1: qos@feeb0700 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfeeb0700 0x0 0x20>; + }; + + qos_usb2: qos@feeb0800 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfeeb0800 0x0 0x20>; + }; + + pmu_grf: syscon@ff010000 { + compatible =3D "rockchip,rk3562-pmu-grf", "syscon", "simple-mfd"; + reg =3D <0x0 0xff010000 0x0 0x10000>; + + reboot_mode: reboot-mode { + compatible =3D "syscon-reboot-mode"; + offset =3D <0x220>; + mode-normal =3D ; + mode-loader =3D ; + mode-recovery =3D ; + mode-bootloader =3D ; + }; + }; + + sys_grf: syscon@ff030000 { + compatible =3D "rockchip,rk3562-sys-grf", "syscon"; + reg =3D <0x0 0xff030000 0x0 0x10000>; + }; + + peri_grf: syscon@ff040000 { + compatible =3D "rockchip,rk3562-peri-grf", "syscon"; + reg =3D <0x0 0xff040000 0x0 0x10000>; + }; + + ioc_grf: syscon@ff060000 { + compatible =3D "rockchip,rk3562-ioc-grf", "syscon"; + reg =3D <0x0 0xff060000 0x0 0x30000>; + }; + + usbphy_grf: syscon@ff090000 { + compatible =3D "rockchip,rk3562-usbphy-grf", "syscon"; + reg =3D <0x0 0xff090000 0x0 0x8000>; + }; + + pipephy_grf: syscon@ff098000 { + compatible =3D "rockchip,rk3562-pipephy-grf", "syscon"; + reg =3D <0x0 0xff098000 0x0 0x8000>; + }; + + cru: clock-controller@ff100000 { + compatible =3D "rockchip,rk3562-cru"; + reg =3D <0x0 0xff100000 0x0 0x40000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + + assigned-clocks =3D + <&cru PLL_GPLL>, <&cru PLL_CPLL>, <&cru PLL_HPLL>; + assigned-clock-rates =3D + <1188000000>, <1000000000>, <983040000>; + }; + + i2c0: i2c@ff200000 { + compatible =3D "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xff200000 0x0 0x1000>; + clocks =3D <&cru CLK_PMU0_I2C0>, <&cru PCLK_PMU0_I2C0>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_xfer>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart0: serial@ff210000 { + compatible =3D "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xff210000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_PMU1_UART0>, <&cru PCLK_PMU1_UART0>; + clock-names =3D "baudclk", "apb_pclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + spi0: spi@ff220000 { + compatible =3D "rockchip,rk3562-spi", "rockchip,rk3066-spi"; + reg =3D <0x0 0xff220000 0x0 0x1000>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cru CLK_PMU1_SPI0>, <&cru PCLK_PMU1_SPI0>; + clock-names =3D "spiclk", "apb_pclk"; + dmas =3D <&dmac 13>, <&dmac 12>; + dma-names =3D "tx", "rx"; + num-cs =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>; + status =3D "disabled"; + }; + + pwm0: pwm@ff230000 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff230000 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm0m0_pins>; + clocks =3D <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm1: pwm@ff230010 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff230010 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm1m0_pins>; + clocks =3D <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm2: pwm@ff230020 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff230020 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm2m0_pins>; + clocks =3D <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm3: pwm@ff230030 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff230030 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm3m0_pins>; + clocks =3D <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pmu: power-management@ff258000 { + compatible =3D "rockchip,rk3562-pmu", "syscon", "simple-mfd"; + reg =3D <0x0 0xff258000 0x0 0x1000>; + + power: power-controller { + compatible =3D "rockchip,rk3562-power-controller"; + #power-domain-cells =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + /* These power domains are grouped by VD_GPU */ + power-domain@RK3562_PD_GPU { + reg =3D ; + pm_qos =3D <&qos_gpu>; + #power-domain-cells =3D <0>; + }; + /* These power domains are grouped by VD_NPU */ + power-domain@RK3562_PD_NPU { + reg =3D ; + pm_qos =3D <&qos_npu>; + #power-domain-cells =3D <0>; + }; + /* These power domains are grouped by VD_LOGIC */ + power-domain@RK3562_PD_VDPU { + reg =3D ; + pm_qos =3D <&qos_rkvdec>; + #power-domain-cells =3D <0>; + }; + power-domain@RK3562_PD_VI { + reg =3D ; + #power-domain-cells =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + pm_qos =3D <&qos_isp>, + <&qos_vicap>; + + power-domain@RK3562_PD_VEPU { + reg =3D ; + pm_qos =3D <&qos_vepu>; + #power-domain-cells =3D <0>; + }; + }; + power-domain@RK3562_PD_VO { + reg =3D ; + #power-domain-cells =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + pm_qos =3D <&qos_vop>; + + power-domain@RK3562_PD_RGA { + reg =3D ; + pm_qos =3D <&qos_rga_rd>, + <&qos_rga_wr>, + <&qos_jpeg>; + #power-domain-cells =3D <0>; + }; + }; + power-domain@RK3562_PD_PHP { + reg =3D ; + pm_qos =3D <&qos_pcie>, + <&qos_usb3>; + #power-domain-cells =3D <0>; + }; + }; + }; + + gpu: gpu@ff320000 { + compatible =3D "rockchip,rk3562-mali", "arm,mali-bifrost"; + reg =3D <0x0 0xff320000 0x0 0x4000>; + + interrupts =3D , + , + ; + interrupt-names =3D "job", "mmu", "gpu"; + + clocks =3D <&scmi_clk CLK_GPU>, <&cru CLK_GPU>, + <&cru CLK_GPU_BRG>, <&cru ACLK_GPU_PRE>; + clock-names =3D "clk_mali", "clk_gpu", "clk_gpu_brg", "aclk_gpu"; + power-domains =3D <&power RK3562_PD_GPU>; + operating-points-v2 =3D <&gpu_opp_table>; + #cooling-cells =3D <2>; + dynamic-power-coefficient =3D <820>; + + status =3D "disabled"; + }; + + gpu_opp_table: opp-table-gpu { + compatible =3D "operating-points-v2"; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + opp-microvolt =3D <825000 825000 1000000>; + }; + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + opp-microvolt =3D <825000 825000 1000000>; + }; + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + opp-microvolt =3D <825000 825000 1000000>; + }; + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + opp-microvolt =3D <825000 825000 1000000>; + }; + opp-700000000 { + opp-hz =3D /bits/ 64 <700000000>; + opp-microvolt =3D <900000 900000 1000000>; + }; + opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-microvolt =3D <950000 950000 1000000>; + }; + opp-900000000 { + opp-hz =3D /bits/ 64 <900000000>; + opp-microvolt =3D <1000000 1000000 1000000>; + }; + }; + + pcie2x1: pcie@ff500000 { + compatible =3D "rockchip,rk3562-pcie", "rockchip,rk3568-pcie"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x0 0xff>; + clocks =3D <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, + <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, + <&cru CLK_PCIE20_AUX>; + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type =3D "pci"; + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "sys", "pmc", "msg", "legacy", "err", "msi"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie2x1_intc 0>, + <0 0 0 2 &pcie2x1_intc 1>, + <0 0 0 3 &pcie2x1_intc 2>, + <0 0 0 4 &pcie2x1_intc 3>; + linux,pci-domain =3D <0>; + max-link-speed =3D <2>; + num-ib-windows =3D <8>; + num-viewport =3D <8>; + num-ob-windows =3D <2>; + num-lanes =3D <1>; + phys =3D <&combphy_pu PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + power-domains =3D <&power RK3562_PD_PHP>; + ranges =3D <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000 + 0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000 + 0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>; + reg =3D <0x0 0xfe000000 0x0 0x400000>, + <0x0 0xff500000 0x0 0x10000>, + <0x0 0xfc000000 0x0 0x100000>; + reg-names =3D "dbi", "apb", "config"; + resets =3D <&cru SRST_PCIE20_POWERUP>; + reset-names =3D "pipe"; + status =3D "disabled"; + + pcie2x1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + }; + + spi1: spi@ff640000 { + compatible =3D "rockchip,rk3066-spi"; + reg =3D <0x0 0xff640000 0x0 0x1000>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names =3D "spiclk", "apb_pclk"; + dmas =3D <&dmac 15>, <&dmac 14>; + dma-names =3D "tx", "rx"; + num-cs =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>; + status =3D "disabled"; + }; + + spi2: spi@ff650000 { + compatible =3D "rockchip,rk3066-spi"; + reg =3D <0x0 0xff650000 0x0 0x1000>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cru CLK_SPI2>, <&cru PCLK_SPI2>; + clock-names =3D "spiclk", "apb_pclk"; + dmas =3D <&dmac 17>, <&dmac 16>; + dma-names =3D "tx", "rx"; + num-cs =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>; + status =3D "disabled"; + }; + + uart1: serial@ff670000 { + compatible =3D "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xff670000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names =3D "baudclk", "apb_pclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart2: serial@ff680000 { + compatible =3D "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xff680000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names =3D "baudclk", "apb_pclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart3: serial@ff690000 { + compatible =3D "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xff690000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names =3D "baudclk", "apb_pclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart4: serial@ff6a0000 { + compatible =3D "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xff6a0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names =3D "baudclk", "apb_pclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart5: serial@ff6b0000 { + compatible =3D "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xff6b0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names =3D "baudclk", "apb_pclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart6: serial@ff6c0000 { + compatible =3D "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xff6c0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names =3D "baudclk", "apb_pclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart7: serial@ff6d0000 { + compatible =3D "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xff6d0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names =3D "baudclk", "apb_pclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart8: serial@ff6e0000 { + compatible =3D "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xff6e0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART8>, <&cru PCLK_UART8>; + clock-names =3D "baudclk", "apb_pclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart9: serial@ff6f0000 { + compatible =3D "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xff6f0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART9>, <&cru PCLK_UART9>; + clock-names =3D "baudclk", "apb_pclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + pwm4: pwm@ff700000 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff700000 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm4m0_pins>; + clocks =3D <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm5: pwm@ff700010 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff700010 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm5m0_pins>; + clocks =3D <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm6: pwm@ff700020 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff700020 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm6m0_pins>; + clocks =3D <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm7: pwm@ff700030 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff700030 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm7m0_pins>; + clocks =3D <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm8: pwm@ff710000 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff710000 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm8m0_pins>; + clocks =3D <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm9: pwm@ff710010 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff710010 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm9m0_pins>; + clocks =3D <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm10: pwm@ff710020 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff710020 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm10m0_pins>; + clocks =3D <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm11: pwm@ff710030 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff710030 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm11m0_pins>; + clocks =3D <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm12: pwm@ff720000 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff720000 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm12m0_pins>; + clocks =3D <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm13: pwm@ff720010 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff720010 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm13m0_pins>; + clocks =3D <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm14: pwm@ff720020 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff720020 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm14m0_pins>; + clocks =3D <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm15: pwm@ff720030 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff720030 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm15m0_pins>; + clocks =3D <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + saradc0: saradc@ff730000 { + compatible =3D "rockchip,rk3562-saradc"; + reg =3D <0x0 0xff730000 0x0 0x100>; + interrupts =3D ; + #io-channel-cells =3D <1>; + clocks =3D <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names =3D "saradc", "apb_pclk"; + resets =3D <&cru SRST_P_SARADC>; + reset-names =3D "saradc-apb"; + status =3D "disabled"; + }; + + u2phy: usb2-phy@ff740000 { + compatible =3D "rockchip,rk3562-usb2phy"; + reg =3D <0x0 0xff740000 0x0 0x10000>; + clocks =3D <&cru CLK_USB2PHY_REF>; + clock-names =3D "phyclk"; + #clock-cells =3D <0>; + clock-output-names =3D "usb480m_phy"; + rockchip,usbgrf =3D <&usbphy_grf>; + status =3D "disabled"; + + u2phy_otg: otg-port { + #phy-cells =3D <0>; + interrupts =3D , + , + ; + interrupt-names =3D "otg-bvalid", "otg-id", "linestate"; + status =3D "disabled"; + }; + + u2phy_host: host-port { + #phy-cells =3D <0>; + interrupts =3D ; + interrupt-names =3D "linestate"; + status =3D "disabled"; + }; + }; + + combphy_pu: phy@ff750000 { + compatible =3D "rockchip,rk3562-naneng-combphy"; + reg =3D <0x0 0xff750000 0x0 0x100>; + #phy-cells =3D <1>; + clocks =3D <&cru CLK_PIPEPHY_REF>, <&cru PCLK_PIPEPHY>, + <&cru PCLK_PHP>; + clock-names =3D "ref", "apb", "pipe"; + assigned-clocks =3D <&cru CLK_PIPEPHY_REF>; + assigned-clock-rates =3D <100000000>; + resets =3D <&cru SRST_PIPEPHY>; + reset-names =3D "phy"; + rockchip,pipe-grf =3D <&peri_grf>; + rockchip,pipe-phy-grf =3D <&pipephy_grf>; + status =3D "disabled"; + }; + + sfc: spi@ff860000 { + compatible =3D "rockchip,sfc"; + reg =3D <0x0 0xff860000 0x0 0x10000>; + interrupts =3D ; + clocks =3D <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names =3D "clk_sfc", "hclk_sfc"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + sdhci: mmc@ff870000 { + compatible =3D "rockchip,rk3562-dwcmshc", "rockchip,rk3588-dwcmshc"; + reg =3D <0x0 0xff870000 0x0 0x10000>; + interrupts =3D ; + assigned-clocks =3D <&cru BCLK_EMMC>, <&cru CCLK_EMMC>; + assigned-clock-rates =3D <200000000>, <200000000>; + clocks =3D <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TMCLK_EMMC>; + clock-names =3D "core", "bus", "axi", "block", "timer"; + resets =3D <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, + <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, + <&cru SRST_T_EMMC>; + reset-names =3D "core", "bus", "axi", "block", "timer"; + max-frequency =3D <200000000>; + status =3D "disabled"; + }; + + sdmmc0: mmc@ff880000 { + compatible =3D "rockchip,rk3562-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg =3D <0x0 0xff880000 0x0 0x10000>; + interrupts =3D ; + max-frequency =3D <200000000>; + clocks =3D <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>, + <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; + clock-names =3D "biu", "ciu", "ciu-drive", "ciu-sample"; + resets =3D <&cru SRST_H_SDMMC0>; + reset-names =3D "reset"; + fifo-depth =3D <0x100>; + status =3D "disabled"; + }; + + sdmmc1: mmc@ff890000 { + compatible =3D "rockchip,rk3562-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg =3D <0x0 0xff890000 0x0 0x10000>; + interrupts =3D ; + max-frequency =3D <200000000>; + clocks =3D <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>, + <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; + clock-names =3D "biu", "ciu", "ciu-drive", "ciu-sample"; + resets =3D <&cru SRST_H_SDMMC1>; + reset-names =3D "reset"; + fifo-depth =3D <0x100>; + status =3D "disabled"; + }; + + otp: otp@ff930000 { + compatible =3D "rockchip,rk3562-otp"; + reg =3D <0x0 0xff930000 0x0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>, + <&cru PCLK_OTPC_NS>, <&cru PCLK_OTPPHY>; + clock-names =3D "usr", "sbpi", "apb_pclk", "phy"; + resets =3D <&cru SRST_USER_OTPC_NS>, <&cru SRST_SBPI_OTPC_NS>, + <&cru SRST_P_OTPC_NS>, <&cru SRST_P_OTPPHY>; + reset-names =3D "usr", "sbpi", "apb", "phy"; + + /* Data cells */ + cpu_code: cpu-code@2 { + reg =3D <0x02 0x2>; + }; + specification_serial_number: specification-serial-number@7 { + reg =3D <0x07 0x1>; + bits =3D <0 5>; + }; + otp_cpu_version: cpu-version@8 { + reg =3D <0x08 0x1>; + bits =3D <3 3>; + }; + mbist_vmin: mbist-vmin@9 { + reg =3D <0x09 0x1>; + bits =3D <0 2>; + }; + log_mbist_vmin: log-mbist-vmin@9 { + reg =3D <0x09 0x1>; + bits =3D <4 2>; + }; + otp_id: id@a { + reg =3D <0x0a 0x10>; + }; + cpu_leakage: cpu-leakage@1a { + reg =3D <0x1a 0x1>; + }; + log_leakage: log-leakage@1b { + reg =3D <0x1b 0x1>; + }; + npu_leakage: npu-leakage@1c { + reg =3D <0x1c 0x1>; + }; + gpu_leakage: gpu-leakage@1d { + reg =3D <0x1d 0x1>; + }; + cpu_tsadc_trim_l: cpu-tsadc-trim-l@2a { + reg =3D <0x2a 0x1>; + }; + cpu_tsadc_trim_h: cpu-tsadc-trim-h@2b { + reg =3D <0x2b 0x1>; + }; + tsadc_trim_base_frac: tsadc-trim-base-frac@2c { + reg =3D <0x2c 0x1>; + bits =3D <4 4>; + }; + tsadc_trim_base: tsadc-trim-base@2d { + reg =3D <0x2d 0x1>; + }; + cpu_opp_info: cpu-opp-info@2e { + reg =3D <0x2e 0x6>; + }; + gpu_opp_info: gpu-opp-info@34 { + reg =3D <0x34 0x6>; + }; + npu_opp_info: npu-opp-info@3a { + reg =3D <0x3a 0x6>; + }; + dmc_opp_info: dmc-opp-info@40 { + reg =3D <0x40 0x6>; + }; + cpu_pvtpll: cpu-pvtpll@46 { + reg =3D <0x46 0x2>; + }; + gpu_pvtpll: gpu-pvtpll@48 { + reg =3D <0x48 0x2>; + }; + npu_pvtpll: npu-pvtpll@4a { + reg =3D <0x4a 0x2>; + }; + }; + + dmac: dma-controller@ff990000 { + compatible =3D "arm,pl330", "arm,primecell"; + reg =3D <0x0 0xff990000 0x0 0x4000>; + interrupts =3D , + ; + clocks =3D <&cru ACLK_DMAC>; + clock-names =3D "apb_pclk"; + #dma-cells =3D <1>; + arm,pl330-periph-burst; + }; + + i2c1: i2c@ffa00000 { + compatible =3D "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xffa00000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1m0_xfer>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c2: i2c@ffa10000 { + compatible =3D "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xffa10000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2m0_xfer>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c3: i2c@ffa20000 { + compatible =3D "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xffa20000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3m0_xfer>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c4: i2c@ffa30000 { + compatible =3D "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xffa30000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c4m0_xfer>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c5: i2c@ffa40000 { + compatible =3D "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xffa40000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c5m0_xfer>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + wdt: watchdog@ffa60000 { + compatible =3D "rockchip,rk3562-wdt", "snps,dw-wdt"; + reg =3D <0x0 0xffa60000 0x0 0x100>; + clocks =3D <&cru CLK_WDTNS>, <&cru PCLK_WDTNS>; + clock-names =3D "tclk", "pclk"; + interrupts =3D ; + status =3D "disabled"; + }; + + gmac0: ethernet@ffa80000 { + compatible =3D "rockchip,rk3562-gmac", "snps,dwmac-4.20a"; + reg =3D <0x0 0xffa80000 0x0 0x10000>; + interrupts =3D , + ; + interrupt-names =3D "macirq", "eth_wake_irq"; + rockchip,grf =3D <&sys_grf>; + rockchip,php-grf =3D <&ioc_grf>; + clocks =3D <&cru CLK_GMAC_125M_CRU_I>, <&cru CLK_GMAC_50M_CRU_I>, + <&cru PCLK_GMAC>, <&cru ACLK_GMAC>; + clock-names =3D "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac"; + resets =3D <&cru SRST_A_GMAC>; + reset-names =3D "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config =3D <&gmac0_stmmac_axi_setup>; + snps,mtl-rx-config =3D <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config =3D <&gmac0_mtl_tx_setup>; + status =3D "disabled"; + + mdio0: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <4>; + snps,rd_osr_lmt =3D <8>; + snps,blen =3D <0 0 0 0 16 8 4>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <1>; + queue0 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <1>; + queue0 {}; + }; + }; + + saradc1: saradc@ffaa0000 { + compatible =3D "rockchip,rk3562-saradc"; + reg =3D <0x0 0xffaa0000 0x0 0x100>; + interrupts =3D ; + #io-channel-cells =3D <1>; + clocks =3D <&cru CLK_SARADC_VCCIO156>, <&cru PCLK_SARADC_VCCIO156>; + clock-names =3D "saradc", "apb_pclk"; + resets =3D <&cru SRST_P_SARADC_VCCIO156>; + reset-names =3D "saradc-apb"; + status =3D "disabled"; + }; + + gmac1: ethernet@ffb30000 { + compatible =3D "rockchip,rk3562-gmac", "snps,dwmac-4.20a"; + reg =3D <0x0 0xffb30000 0x0 0x10000>; + interrupts =3D , + ; + interrupt-names =3D "macirq", "eth_wake_irq"; + rockchip,grf =3D <&sys_grf>; + rockchip,php-grf =3D <&ioc_grf>; + clocks =3D <&cru CLK_MAC100_50M_MATRIX>, <&cru CLK_MAC100_50M_MATRIX>, + <&cru PCLK_MAC100>, <&cru ACLK_MAC100>; + clock-names =3D "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac"; + resets =3D <&cru SRST_A_MAC100>; + reset-names =3D "stmmaceth"; + status =3D "disabled"; + + mdio1: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + }; + }; + + pinctrl: pinctrl { + compatible =3D "rockchip,rk3562-pinctrl"; + rockchip,grf =3D <&ioc_grf>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gpio0: gpio@ff260000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xff260000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 0 32>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpio1: gpio@ff620000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xff620000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 32 32>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpio2: gpio@ff630000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xff630000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 64 32>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpio3: gpio@ffac0000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xffac0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 96 32>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpio4: gpio@ffad0000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xffad0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 128 32>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; +}; + +#include "rk3562-pinctrl.dtsi" --=20 2.25.1 From nobody Mon Feb 9 01:52:26 2026 Received: from mail-m12790.qiye.163.com (mail-m12790.qiye.163.com [115.236.127.90]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE6161DE88C; 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arc=none smtp.client-ip=115.236.127.90 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="KeGjISfy" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 6aad4f94; Tue, 24 Dec 2024 17:49:48 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Finley Xiao , Kever Yang , devicetree@vger.kernel.org, Conor Dooley , Chris Morgan , Rob Herring , Johan Jonker , FUKAUMI Naoki , Jonas Karlman , linux-kernel@vger.kernel.org, Diederik de Haas , linux-arm-kernel@lists.infradead.org, Michael Riesch , Krzysztof Kozlowski , Andy Yan Subject: [PATCH v2 17/17] arm64: dts: rockchip: Add RK3562 evb2 devicetree Date: Tue, 24 Dec 2024 17:49:20 +0800 Message-Id: <20241224094920.3821861-18-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241224094920.3821861-1-kever.yang@rock-chips.com> References: <20241224094920.3821861-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGUgfTVZOTBhKQhkaTkNOSBhWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCS0 NVSktLVUpCWQY+ X-HM-Tid: 0a93f81296ea03afkunm6aad4f94 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Oio6Qxw6KDIULkpNPEpPLA1N Li4wCQtVSlVKTEhOS0hITENCTUlMVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFKT0tNTjcG DKIM-Signature: a=rsa-sha256; b=KeGjISfyt/yleGdbf1m6kJADTxOHkJJ47JYH8+glqBUQcq//YiDKyjvDxUWNOYIcy5NBXeww0799fAjzg02ZJt+xXFWezmNa/QCRfVAM2A437FYRhyEVFrGKnadaOtds5BGLGF0UhY1m2KcedeA4kISH34Ztbz21sX9w6fASSjk=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=a5L8h1NQ2pdseIC+YzF9pT5cAQA24JS3tO66J9WegHo=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" From: Finley Xiao DRAM: DDR4 Storage: eMMC PMIC: RK809 Audio: Headphone and speaker Interface: - USB3.0 HOST - USB2.0 HOST - PCIe x4 slot(pcie2x1 available) - SD card slot - GMAC - debug UART0 NOTE: the USB3.0 and the PCIe reuse the comboPHY, so the USB3.0 work in USB2 only mode. Signed-off-by: Finley Xiao Signed-off-by: Kever Yang --- Changes in v2: None arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3562-evb2-v10.dts | 520 ++++++++++++++++++ 2 files changed, 521 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-evb2-v10.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 2e683d7eab58..3849a0d388e3 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -78,6 +78,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399-sapphire.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399-sapphire-excavator.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3528-radxa-e20c.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3562-evb2-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-anbernic-rg-arc-d.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-anbernic-rg-arc-s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-anbernic-rg353p.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb2-v10.dts b/arch/arm64/= boot/dts/rockchip/rk3562-evb2-v10.dts new file mode 100644 index 000000000000..f3669e965cbf --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb2-v10.dts @@ -0,0 +1,520 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "rk3562.dtsi" + +/ { + model =3D "Rockchip RK3562 EVB V20 Board"; + compatible =3D "rockchip,rk3562-evb2-v10", "rockchip,rk3562"; + + chosen: chosen { + stdout-path =3D "serial0:1500000n8"; + }; + + adc_keys: adc-keys { + compatible =3D "adc-keys"; + io-channels =3D <&saradc0 1>; + io-channel-names =3D "buttons"; + keyup-threshold-microvolt =3D <1800000>; + poll-interval =3D <100>; + + button-vol-up { + linux,code =3D ; + label =3D "volume up"; + press-threshold-microvolt =3D <17000>; + }; + + button-vol-down { + linux,code =3D ; + label =3D "volume down"; + press-threshold-microvolt =3D <414000>; + }; + + button-menu { + linux,code =3D ; + label =3D "menu"; + press-threshold-microvolt =3D <800000>; + }; + + button-back { + linux,code =3D ; + label =3D "back"; + press-threshold-microvolt =3D <1200000>; + }; + }; + + leds: leds { + compatible =3D "gpio-leds"; + work_led: led-0 { + gpios =3D <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + dc_12v: dc-12v { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + clocks =3D <&rk809 1>; + clock-names =3D "ext_clock"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms =3D <200>; + reset-gpios =3D <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; + }; + + vcc3v3_pcie20: vcc3v3-pcie20 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_pcie20"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + enable-active-high; + gpios =3D <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + startup-delay-us =3D <5000>; + vin-supply =3D <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&dc_12v>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&dc_12v>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&vcc5v0_usb>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb_host_pwren>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb_otg"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&vcc5v0_usb>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb_otg_pwren>; + }; + + vcc3v3_clk: vcc3v3-clk { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_clk"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc3v3_sys: vcc-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&dc_12v>; + }; +}; + +&combphy_pu { + status =3D "okay"; +}; + +&gmac0 { + phy-mode =3D "rgmii-rxid"; + clock_in_out =3D "output"; + + snps,reset-gpio =3D <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us =3D <0 20000 100000>; + + tx_delay =3D <0x42>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmiim0_miim + &rgmiim0_tx_bus2 + &rgmiim0_rx_bus2 + &rgmiim0_rgmii_clk + &rgmiim0_rgmii_bus + ðm0_pins>; + + phy-handle =3D <&rgmii_phy>; + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; + + rk809: pmic@20 { + compatible =3D "rockchip,rk809"; + reg =3D <0x20>; + interrupt-parent =3D <&gpio0>; + interrupts =3D <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names =3D "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 =3D <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells =3D <1>; + clock-output-names =3D "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply =3D <&vcc3v3_sys>; + vcc2-supply =3D <&vcc3v3_sys>; + vcc3-supply =3D <&vcc3v3_sys>; + vcc4-supply =3D <&vcc3v3_sys>; + vcc5-supply =3D <&vcc3v3_sys>; + vcc6-supply =3D <&vcc3v3_sys>; + vcc7-supply =3D <&vcc3v3_sys>; + vcc8-supply =3D <&vcc3v3_sys>; + vcc9-supply =3D <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + regulator-initial-mode =3D <0x2>; + regulator-name =3D "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + regulator-initial-mode =3D <0x2>; + regulator-name =3D "vdd_cpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode =3D <0x2>; + regulator-name =3D "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + regulator-initial-mode =3D <0x2>; + regulator-name =3D "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG1 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-name =3D "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-name =3D "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG9 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&mdio0 { + rgmii_phy: phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + clocks =3D <&cru CLK_GMAC_ETH_OUT2IO>; + assigned-clocks =3D <&cru CLK_GMAC_ETH_OUT2IO>; + assigned-clock-rates =3D <25000000>; + }; +}; + +&pcie2x1 { + reset-gpios =3D <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie20>; + status =3D "okay"; +}; + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins =3D <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins =3D <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg_pwren: usb-otg-pwren { + rockchip,pins =3D <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc0 { + status =3D "okay"; + vref-supply =3D <&vcc_1v8>; +}; + +&sdhci { + bus-width =3D <8>; + no-sdio; + no-sd; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status =3D "okay"; +}; + +&sdmmc0 { + no-sdio; + no-mmc; + bus-width =3D <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc3v3_sd>; + vqmmc-supply =3D <&vccio_sd>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status =3D "okay"; +}; + +&sdmmc1 { + no-sd; + no-mmc; + bus-width =3D <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq =3D <&sdio_pwrseq>; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status =3D "okay"; +}; + +&u2phy { + status =3D "okay"; +}; + +&u2phy_host { + status =3D "okay"; + phy-supply =3D <&vcc5v0_usb_host>; +}; + +&u2phy_otg { + status =3D "okay"; + phy-supply =3D <&vcc5v0_usb_otg>; +}; + +&uart0 { + status =3D "okay"; +}; + +&uart1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&usbdrd_dwc3 { + status =3D "okay"; + dr_mode =3D "host"; + extcon =3D <&u2phy>; + maximum-speed =3D "high-speed"; + phys =3D <&u2phy_otg>; + phy-names =3D "usb2-phy"; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; +}; --=20 2.25.1