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Tue, 24 Dec 2024 01:28:14 -0800 (PST) Received: from hsinchu36-syssw02.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72af8dcff60sm516341b3a.152.2024.12.24.01.28.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 01:28:14 -0800 (PST) From: Nylon Chen To: linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org Cc: Nylon Chen , Zong Li , Vincent Chen , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Paul Walmsley , Samuel Holland , linux-riscv@lists.infradead.org Subject: [PATCH v10 2/3] pwm: sifive: change the PWM algorithm Date: Tue, 24 Dec 2024 17:39:00 +0800 Message-Id: <20241224093902.1632627-3-nylon.chen@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241224093902.1632627-1-nylon.chen@sifive.com> References: <20241224093902.1632627-1-nylon.chen@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The `frac` variable represents the pulse inactive time, and the result of this algorithm is the pulse active time. Therefore, we must reverse the result. The reference is SiFive FU740-C000 Manual[0] Link: https://sifive.cdn.prismic.io/sifive/1a82e600-1f93-4f41-b2d8-86ed8b16= acba_fu740-c000-manual-v1p6.pdf [0] Co-developed-by: Zong Li Signed-off-by: Zong Li Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Nylon Chen --- drivers/pwm/pwm-sifive.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c index d5b647e6be78..bb9146267bc5 100644 --- a/drivers/pwm/pwm-sifive.c +++ b/drivers/pwm/pwm-sifive.c @@ -110,9 +110,10 @@ static int pwm_sifive_get_state(struct pwm_chip *chip,= struct pwm_device *pwm, struct pwm_state *state) { struct pwm_sifive_ddata *ddata =3D pwm_sifive_chip_to_ddata(chip); - u32 duty, val; + u32 duty, val, inactive; =20 - duty =3D readl(ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm)); + inactive =3D readl(ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm)); + duty =3D (1U << PWM_SIFIVE_CMPWIDTH) - 1 - inactive; =20 state->enabled =3D duty > 0; =20 @@ -123,7 +124,7 @@ static int pwm_sifive_get_state(struct pwm_chip *chip, = struct pwm_device *pwm, state->period =3D ddata->real_period; state->duty_cycle =3D (u64)duty * ddata->real_period >> PWM_SIFIVE_CMPWIDTH; - state->polarity =3D PWM_POLARITY_INVERSED; + state->polarity =3D PWM_POLARITY_NORMAL; =20 return 0; } @@ -137,9 +138,9 @@ static int pwm_sifive_apply(struct pwm_chip *chip, stru= ct pwm_device *pwm, unsigned long long num; bool enabled; int ret =3D 0; - u32 frac; + u32 frac, inactive; =20 - if (state->polarity !=3D PWM_POLARITY_INVERSED) + if (state->polarity !=3D PWM_POLARITY_NORMAL) return -EINVAL; =20 cur_state =3D pwm->state; @@ -157,8 +158,9 @@ static int pwm_sifive_apply(struct pwm_chip *chip, stru= ct pwm_device *pwm, */ num =3D (u64)duty_cycle * (1U << PWM_SIFIVE_CMPWIDTH); frac =3D DIV64_U64_ROUND_CLOSEST(num, state->period); - /* The hardware cannot generate a 100% duty cycle */ + /* The hardware cannot generate a 0% duty cycle */ frac =3D min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1); + inactive =3D (1U << PWM_SIFIVE_CMPWIDTH) - 1 - frac; =20 mutex_lock(&ddata->lock); if (state->period !=3D ddata->approx_period) { @@ -190,7 +192,7 @@ static int pwm_sifive_apply(struct pwm_chip *chip, stru= ct pwm_device *pwm, } } =20 - writel(frac, ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm)); + writel(inactive, ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm)); =20 if (!state->enabled) clk_disable(ddata->clk); --=20 2.34.1