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[2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43661219a7csm160932535e9.24.2024.12.24.01.34.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 01:34:37 -0800 (PST) From: Julien Stephan Date: Tue, 24 Dec 2024 10:34:31 +0100 Subject: [PATCH RFC v2 2/4] iio: adc: ad7380: enable regmap cache Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241224-ad7380-add-alert-support-v2-2-7c89b2bf7cb3@baylibre.com> References: <20241224-ad7380-add-alert-support-v2-0-7c89b2bf7cb3@baylibre.com> In-Reply-To: <20241224-ad7380-add-alert-support-v2-0-7c89b2bf7cb3@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Jonathan Corbet Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.14.2 Enable regmap cache, to avoid useless access on spi bus. Don't store anymore the oversampling ratio in private data structure. Signed-off-by: Julien Stephan --- drivers/iio/adc/ad7380.c | 98 +++++++++++++++++++++++++++++++++++++++++---= ---- 1 file changed, 84 insertions(+), 14 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index 4e26e0e7ac1d5a1c4c67118dbc34f2921fc171a4..b49067c36fdd1bb0e760faf71d7= fa0c8c1f610e9 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -582,7 +582,6 @@ struct ad7380_state { const struct ad7380_chip_info *chip_info; struct spi_device *spi; struct regmap *regmap; - unsigned int oversampling_ratio; bool resolution_boost_enabled; unsigned int ch; bool seq; @@ -663,6 +662,20 @@ static int ad7380_regmap_reg_read(void *context, unsig= ned int reg, return 0; } =20 +static const struct reg_default ad7380_reg_defaults[] =3D { + { AD7380_REG_ADDR_ALERT_LOW_TH, 0x800 }, + { AD7380_REG_ADDR_ALERT_HIGH_TH, 0x7FF }, +}; + +static const struct regmap_range ad7380_volatile_reg_ranges[] =3D { + regmap_reg_range(AD7380_REG_ADDR_CONFIG2, AD7380_REG_ADDR_ALERT), +}; + +static const struct regmap_access_table ad7380_volatile_regs =3D { + .yes_ranges =3D ad7380_volatile_reg_ranges, + .n_yes_ranges =3D ARRAY_SIZE(ad7380_volatile_reg_ranges), +}; + static const struct regmap_config ad7380_regmap_config =3D { .reg_bits =3D 3, .val_bits =3D 12, @@ -670,6 +683,10 @@ static const struct regmap_config ad7380_regmap_config= =3D { .reg_write =3D ad7380_regmap_reg_write, .max_register =3D AD7380_REG_ADDR_ALERT_HIGH_TH, .can_sleep =3D true, + .reg_defaults =3D ad7380_reg_defaults, + .num_reg_defaults =3D ARRAY_SIZE(ad7380_reg_defaults), + .volatile_table =3D &ad7380_volatile_regs, + .cache_type =3D REGCACHE_MAPLE, }; =20 static int ad7380_debugfs_reg_access(struct iio_dev *indio_dev, u32 reg, @@ -692,6 +709,37 @@ static int ad7380_debugfs_reg_access(struct iio_dev *i= ndio_dev, u32 reg, return ret; } =20 +/** + * ad7380_regval_to_osr - convert OSR register value to ratio + * @regval: register value to check + * + * Returns: the ratio corresponding to the OSR register. If regval is not = in + * bound, return 1 (oversampling disabled) + * + */ +static int ad7380_regval_to_osr(int regval) +{ + if (regval < 0 || regval >=3D ARRAY_SIZE(ad7380_oversampling_ratios)) + return 1; + + return ad7380_oversampling_ratios[regval]; +} + +static int ad7380_get_osr(struct ad7380_state *st, int *val) +{ + int tmp; + int ret =3D 0; + + ret =3D regmap_read(st->regmap, AD7380_REG_ADDR_CONFIG1, &tmp); + if (ret) + return ret; + + *val =3D ad7380_regval_to_osr(FIELD_GET(AD7380_CONFIG1_OSR, tmp)); + + return 0; +} + + /* * When switching channel, the ADC require an additional settling time. * According to the datasheet, data is value on the third CS low. We alrea= dy @@ -707,11 +755,15 @@ static int ad7380_set_ch(struct ad7380_state *st, uns= igned int ch) .unit =3D SPI_DELAY_UNIT_NSECS, } }; - int ret; + int oversampling_ratio, ret; =20 if (st->ch =3D=3D ch) return 0; =20 + ret =3D ad7380_get_osr(st, &oversampling_ratio); + if (ret) + return ret; + ret =3D regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG1, AD7380_CONFIG1_CH, @@ -722,9 +774,9 @@ static int ad7380_set_ch(struct ad7380_state *st, unsig= ned int ch) =20 st->ch =3D ch; =20 - if (st->oversampling_ratio > 1) + if (oversampling_ratio > 1) xfer.delay.value =3D T_CONVERT_0_NS + - T_CONVERT_X_NS * (st->oversampling_ratio - 1) * + T_CONVERT_X_NS * (oversampling_ratio - 1) * st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES; =20 return spi_sync_transfer(st->spi, &xfer, 1); @@ -735,20 +787,25 @@ static int ad7380_set_ch(struct ad7380_state *st, uns= igned int ch) * @st: device instance specific state * @scan_type: current scan type */ -static void ad7380_update_xfers(struct ad7380_state *st, +static int ad7380_update_xfers(struct ad7380_state *st, const struct iio_scan_type *scan_type) { struct spi_transfer *xfer =3D st->seq ? st->seq_xfer : st->normal_xfer; unsigned int t_convert =3D T_CONVERT_NS; + int oversampling_ratio, ret; =20 /* * In the case of oversampling, conversion time is higher than in normal * mode. Technically T_CONVERT_X_NS is lower for some chips, but we use * the maximum value for simplicity for now. */ - if (st->oversampling_ratio > 1) + ret =3D ad7380_get_osr(st, &oversampling_ratio); + if (ret) + return ret; + + if (oversampling_ratio > 1) t_convert =3D T_CONVERT_0_NS + T_CONVERT_X_NS * - (st->oversampling_ratio - 1) * + (oversampling_ratio - 1) * st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES; =20 if (st->seq) { @@ -761,7 +818,7 @@ static void ad7380_update_xfers(struct ad7380_state *st, st->chip_info->num_simult_channels; xfer[3].rx_buf =3D xfer[2].rx_buf + xfer[2].len; /* Additional delay required here when oversampling is enabled */ - if (st->oversampling_ratio > 1) + if (oversampling_ratio > 1) xfer[2].delay.value =3D t_convert; else xfer[2].delay.value =3D 0; @@ -773,6 +830,8 @@ static void ad7380_update_xfers(struct ad7380_state *st, xfer[1].len =3D BITS_TO_BYTES(scan_type->storagebits) * st->chip_info->num_simult_channels; } + + return 0; } =20 static int ad7380_triggered_buffer_preenable(struct iio_dev *indio_dev) @@ -780,6 +839,7 @@ static int ad7380_triggered_buffer_preenable(struct iio= _dev *indio_dev) struct ad7380_state *st =3D iio_priv(indio_dev); const struct iio_scan_type *scan_type; struct spi_message *msg =3D &st->normal_msg; + int ret; =20 /* * Currently, we always read all channels at the same time. The scan_type @@ -791,7 +851,6 @@ static int ad7380_triggered_buffer_preenable(struct iio= _dev *indio_dev) =20 if (st->chip_info->has_mux) { unsigned int index; - int ret; =20 /* * Depending on the requested scan_mask and current state, @@ -822,7 +881,9 @@ static int ad7380_triggered_buffer_preenable(struct iio= _dev *indio_dev) =20 } =20 - ad7380_update_xfers(st, scan_type); + ret =3D ad7380_update_xfers(st, scan_type); + if (ret) + return ret; =20 return spi_optimize_message(st->spi, msg); } @@ -895,7 +956,9 @@ static int ad7380_read_direct(struct ad7380_state *st, = unsigned int scan_index, return ret; } =20 - ad7380_update_xfers(st, scan_type); + ret =3D ad7380_update_xfers(st, scan_type); + if (ret) + return ret; =20 ret =3D spi_sync(st->spi, &st->normal_msg); if (ret < 0) @@ -973,7 +1036,16 @@ static int ad7380_read_raw(struct iio_dev *indio_dev, =20 return IIO_VAL_INT; case IIO_CHAN_INFO_OVERSAMPLING_RATIO: - *val =3D st->oversampling_ratio; + ret =3D iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + ret =3D ad7380_get_osr(st, val); + + iio_device_release_direct_mode(indio_dev); + + if (ret) + return ret; =20 return IIO_VAL_INT; default: @@ -1049,7 +1121,6 @@ static int ad7380_write_raw(struct iio_dev *indio_dev, if (ret) goto err; =20 - st->oversampling_ratio =3D val; st->resolution_boost_enabled =3D boost; =20 /* @@ -1109,7 +1180,6 @@ static int ad7380_init(struct ad7380_state *st, bool = external_ref_en) } =20 /* This is the default value after reset. */ - st->oversampling_ratio =3D 1; st->ch =3D 0; st->seq =3D false; =20 --=20 2.47.1