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[2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43661219a7csm160932535e9.24.2024.12.24.01.34.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 01:34:36 -0800 (PST) From: Julien Stephan Date: Tue, 24 Dec 2024 10:34:30 +0100 Subject: [PATCH RFC v2 1/4] iio: adc: ad7380: do not use iio_device_claim_direct_scoped anymore Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241224-ad7380-add-alert-support-v2-1-7c89b2bf7cb3@baylibre.com> References: <20241224-ad7380-add-alert-support-v2-0-7c89b2bf7cb3@baylibre.com> In-Reply-To: <20241224-ad7380-add-alert-support-v2-0-7c89b2bf7cb3@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Jonathan Corbet Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.14.2 Rollback and remove the scoped version of iio_dvice_claim_direct_mode. Signed-off-by: Julien Stephan --- drivers/iio/adc/ad7380.c | 89 ++++++++++++++++++++++++++++----------------= ---- 1 file changed, 53 insertions(+), 36 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index 4f32cb22f140442b831dc9a4f275e88e4ab2388e..4e26e0e7ac1d5a1c4c67118dbc3= 4f2921fc171a4 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -675,15 +675,21 @@ static const struct regmap_config ad7380_regmap_confi= g =3D { static int ad7380_debugfs_reg_access(struct iio_dev *indio_dev, u32 reg, u32 writeval, u32 *readval) { - iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { - struct ad7380_state *st =3D iio_priv(indio_dev); + struct ad7380_state *st =3D iio_priv(indio_dev); + int ret; =20 - if (readval) - return regmap_read(st->regmap, reg, readval); - else - return regmap_write(st->regmap, reg, writeval); - } - unreachable(); + ret =3D iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + if (readval) + ret =3D regmap_read(st->regmap, reg, readval); + else + ret =3D regmap_write(st->regmap, reg, writeval); + + iio_device_release_direct_mode(indio_dev); + + return ret; } =20 /* @@ -920,6 +926,7 @@ static int ad7380_read_raw(struct iio_dev *indio_dev, { struct ad7380_state *st =3D iio_priv(indio_dev); const struct iio_scan_type *scan_type; + int ret; =20 scan_type =3D iio_get_current_scan_type(indio_dev, chan); =20 @@ -928,11 +935,16 @@ static int ad7380_read_raw(struct iio_dev *indio_dev, =20 switch (info) { case IIO_CHAN_INFO_RAW: - iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { - return ad7380_read_direct(st, chan->scan_index, - scan_type, val); - } - unreachable(); + ret =3D iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + ret =3D ad7380_read_direct(st, chan->scan_index, + scan_type, val); + + iio_device_release_direct_mode(indio_dev); + + return ret; case IIO_CHAN_INFO_SCALE: /* * According to the datasheet, the LSB size is: @@ -1024,31 +1036,36 @@ static int ad7380_write_raw(struct iio_dev *indio_d= ev, /* always enable resolution boost when oversampling is enabled */ boost =3D osr > 0 ? 1 : 0; =20 - iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { - ret =3D regmap_update_bits(st->regmap, - AD7380_REG_ADDR_CONFIG1, - AD7380_CONFIG1_OSR | AD7380_CONFIG1_RES, - FIELD_PREP(AD7380_CONFIG1_OSR, osr) | - FIELD_PREP(AD7380_CONFIG1_RES, boost)); + ret =3D iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; =20 - if (ret) - return ret; + ret =3D regmap_update_bits(st->regmap, + AD7380_REG_ADDR_CONFIG1, + AD7380_CONFIG1_OSR | AD7380_CONFIG1_RES, + FIELD_PREP(AD7380_CONFIG1_OSR, osr) | + FIELD_PREP(AD7380_CONFIG1_RES, boost)); =20 - st->oversampling_ratio =3D val; - st->resolution_boost_enabled =3D boost; - - /* - * Perform a soft reset. This will flush the oversampling - * block and FIFO but will maintain the content of the - * configurable registers. - */ - return regmap_update_bits(st->regmap, - AD7380_REG_ADDR_CONFIG2, - AD7380_CONFIG2_RESET, - FIELD_PREP(AD7380_CONFIG2_RESET, - AD7380_CONFIG2_RESET_SOFT)); - } - unreachable(); + if (ret) + goto err; + + st->oversampling_ratio =3D val; + st->resolution_boost_enabled =3D boost; + + /* + * Perform a soft reset. This will flush the oversampling + * block and FIFO but will maintain the content of the + * configurable registers. + */ + ret =3D regmap_update_bits(st->regmap, + AD7380_REG_ADDR_CONFIG2, + AD7380_CONFIG2_RESET, + FIELD_PREP(AD7380_CONFIG2_RESET, + AD7380_CONFIG2_RESET_SOFT)); +err: + iio_device_release_direct_mode(indio_dev); + + return ret; default: return -EINVAL; } --=20 2.47.1 From nobody Sun Feb 8 20:37:56 2026 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F9F51A8F98 for ; Tue, 24 Dec 2024 09:34:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735032882; cv=none; b=CvadVWMHFOB5KFp60wHEE7CBm6d70t3ffpIH4X3TY1a2WKsH5ulRFMRsqXAWEQJ4G+EF4f2onei/IhUlWdXEcrBMrskcVx5RameQhNxsM5dzjFxbtmbDL2Mc2u2/7lHVN5JRBZLV5NiOIV9SGd4jPe2g6rKP1c2R3UrDw9po3IE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735032882; c=relaxed/simple; bh=yua/0zbTjMAmf2oFYpIk9LoTXBCtqmeHxVaLSwADFOI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pmk6Etm682zdIZNeneBdITFHigeKknxcqMY4acqG4gZ43ukEzGSrut2k7CqplsBiAp8pva1VIpjlF1WGec7lHGOGUQ04LgS5wcvODKKlTEno+eoktJlOI6RotGC7YAQa3A0KKzAqFpOSfdGC1C/oJjNS13E7idER9NqhW/nymAo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=TEyu7CRc; arc=none smtp.client-ip=209.85.221.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="TEyu7CRc" Received: by mail-wr1-f44.google.com with SMTP id ffacd0b85a97d-385d7b4da2bso4268334f8f.1 for ; Tue, 24 Dec 2024 01:34:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1735032877; x=1735637677; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=T+u4Jy5PvOQf+0yU+yfEzQNHFYwkap+NBzqGZU1Srk8=; b=TEyu7CRcUSamaKAOBgKktJln5RZZJA3bLD19Qzu4x5yLdOW3ZNMvvhJXlDr5xV4sPo L8X1So0gEd56Asim7J1yFiRZWf7D7BTI5Jj/gvqO0y25Bhy0CWdMidHJGBUJFt9X3pyR 6YLxGxlisLiY2btzOlhvXhji7nB7sIyJ91HccKU6hMbIXGWDIg+VksLQB1nMIMHZB5Yl geh867C27o0bvC+HPcdi++JP0x3BH0itDXvUrhcv/sTlDlYDoUWyNdEcGIo70TrM6rIT Chb2TvCrL3eIlBXi7HMTdD9WA1aebO+LAD3ezC1Bejg9zCmPL4kcU6VZAqBC9W5LtLv1 vhmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735032877; x=1735637677; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T+u4Jy5PvOQf+0yU+yfEzQNHFYwkap+NBzqGZU1Srk8=; b=RFVU1sYQtK+nD4MChYUwbGNCpz4aF153LA5O/6q+dEFp0Yl+v5L5pxyjFsWtmGZPXV KSa/H+Q2qlyPFJLI7+2s1fBJokfOdeseDwr3ioppZsEBg6maKB8Nn8LQbKt1glgUT/pm piRb+TwjJjPIzbPwHvFcWTqodyXqgL6uRbBI3p5Lwtou1rcF7GuET/EZyAloErk7i8cB lBIGvz/LXUZlh+bDWCT++Kzb0Hm+HPtItlvXtFupgOI3DQPTKsJZsSFfhSHDvXkZl6y3 gib6mocwgzvUwIQSqqttmXxKSHx++BF88K+mS6IC+pc0aRVBhBZGIqwCHww0VL1wQ7n7 llVQ== X-Forwarded-Encrypted: i=1; AJvYcCWBEwEJaBJH1gaw89hrBXYmxzIRN5Rdpm0Ghk6iMoSvrizVyUaN4kcsoSdKXXmqCyZjGJaFAms9CI3BkMA=@vger.kernel.org X-Gm-Message-State: AOJu0YwIi+gFbhipMtH8iK+YEd6chb+ML2kDlAY4R/NOpgcOf8PBtYhi DPxGzzF5GxQX/H2aPdq/Z6IfwXKqaSUCmH3bf96Ml84ZLewZhcROUsDuh12/b7s= X-Gm-Gg: ASbGncv0hhor3GJT08/VmdL+AQGTRZOFhA6Ze7y2uxgYnjH410eTceEZVUI6MHBic2Q 9WooIfEso5xi93Vvyg50dsZURfYmZi1a/WEzLsTf7PYlQUR+m/xjRgvrKBbuOVyla+agZd6qxGo leJ0RPwEkVBdXvBIOyZ694iw19hE1vCpk432g//kfLY6qXEASBRJDafKWAepdfuLh41uaHqQxko EaB55RT57eA62ZAFGrcH0lf6+to0bm9kMjbDv9IrenVPs3ZOcO3NXyCQzzY6x5JIh98WVTLSuhw ViK9gQSwlNcvMvRzNBjBxyIoASbtbJQmo1B/q162tFPE0tKf/Q== X-Google-Smtp-Source: AGHT+IHc62hSMXyBCQybh0DW1xl5UpUk+2FH16w/EZk5yE0yHwj0g8JiuD93nhp+FS97ASHVIN8/uQ== X-Received: by 2002:a05:6000:156f:b0:385:fd31:ca23 with SMTP id ffacd0b85a97d-38a223f8302mr16102917f8f.40.1735032877514; Tue, 24 Dec 2024 01:34:37 -0800 (PST) Received: from [192.168.1.62] (2a02-842a-d52e-6101-6fd0-06c4-5d68-f0a5.rev.sfr.net. [2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43661219a7csm160932535e9.24.2024.12.24.01.34.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 01:34:37 -0800 (PST) From: Julien Stephan Date: Tue, 24 Dec 2024 10:34:31 +0100 Subject: [PATCH RFC v2 2/4] iio: adc: ad7380: enable regmap cache Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241224-ad7380-add-alert-support-v2-2-7c89b2bf7cb3@baylibre.com> References: <20241224-ad7380-add-alert-support-v2-0-7c89b2bf7cb3@baylibre.com> In-Reply-To: <20241224-ad7380-add-alert-support-v2-0-7c89b2bf7cb3@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Jonathan Corbet Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.14.2 Enable regmap cache, to avoid useless access on spi bus. Don't store anymore the oversampling ratio in private data structure. Signed-off-by: Julien Stephan --- drivers/iio/adc/ad7380.c | 98 +++++++++++++++++++++++++++++++++++++++++---= ---- 1 file changed, 84 insertions(+), 14 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index 4e26e0e7ac1d5a1c4c67118dbc34f2921fc171a4..b49067c36fdd1bb0e760faf71d7= fa0c8c1f610e9 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -582,7 +582,6 @@ struct ad7380_state { const struct ad7380_chip_info *chip_info; struct spi_device *spi; struct regmap *regmap; - unsigned int oversampling_ratio; bool resolution_boost_enabled; unsigned int ch; bool seq; @@ -663,6 +662,20 @@ static int ad7380_regmap_reg_read(void *context, unsig= ned int reg, return 0; } =20 +static const struct reg_default ad7380_reg_defaults[] =3D { + { AD7380_REG_ADDR_ALERT_LOW_TH, 0x800 }, + { AD7380_REG_ADDR_ALERT_HIGH_TH, 0x7FF }, +}; + +static const struct regmap_range ad7380_volatile_reg_ranges[] =3D { + regmap_reg_range(AD7380_REG_ADDR_CONFIG2, AD7380_REG_ADDR_ALERT), +}; + +static const struct regmap_access_table ad7380_volatile_regs =3D { + .yes_ranges =3D ad7380_volatile_reg_ranges, + .n_yes_ranges =3D ARRAY_SIZE(ad7380_volatile_reg_ranges), +}; + static const struct regmap_config ad7380_regmap_config =3D { .reg_bits =3D 3, .val_bits =3D 12, @@ -670,6 +683,10 @@ static const struct regmap_config ad7380_regmap_config= =3D { .reg_write =3D ad7380_regmap_reg_write, .max_register =3D AD7380_REG_ADDR_ALERT_HIGH_TH, .can_sleep =3D true, + .reg_defaults =3D ad7380_reg_defaults, + .num_reg_defaults =3D ARRAY_SIZE(ad7380_reg_defaults), + .volatile_table =3D &ad7380_volatile_regs, + .cache_type =3D REGCACHE_MAPLE, }; =20 static int ad7380_debugfs_reg_access(struct iio_dev *indio_dev, u32 reg, @@ -692,6 +709,37 @@ static int ad7380_debugfs_reg_access(struct iio_dev *i= ndio_dev, u32 reg, return ret; } =20 +/** + * ad7380_regval_to_osr - convert OSR register value to ratio + * @regval: register value to check + * + * Returns: the ratio corresponding to the OSR register. If regval is not = in + * bound, return 1 (oversampling disabled) + * + */ +static int ad7380_regval_to_osr(int regval) +{ + if (regval < 0 || regval >=3D ARRAY_SIZE(ad7380_oversampling_ratios)) + return 1; + + return ad7380_oversampling_ratios[regval]; +} + +static int ad7380_get_osr(struct ad7380_state *st, int *val) +{ + int tmp; + int ret =3D 0; + + ret =3D regmap_read(st->regmap, AD7380_REG_ADDR_CONFIG1, &tmp); + if (ret) + return ret; + + *val =3D ad7380_regval_to_osr(FIELD_GET(AD7380_CONFIG1_OSR, tmp)); + + return 0; +} + + /* * When switching channel, the ADC require an additional settling time. * According to the datasheet, data is value on the third CS low. We alrea= dy @@ -707,11 +755,15 @@ static int ad7380_set_ch(struct ad7380_state *st, uns= igned int ch) .unit =3D SPI_DELAY_UNIT_NSECS, } }; - int ret; + int oversampling_ratio, ret; =20 if (st->ch =3D=3D ch) return 0; =20 + ret =3D ad7380_get_osr(st, &oversampling_ratio); + if (ret) + return ret; + ret =3D regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG1, AD7380_CONFIG1_CH, @@ -722,9 +774,9 @@ static int ad7380_set_ch(struct ad7380_state *st, unsig= ned int ch) =20 st->ch =3D ch; =20 - if (st->oversampling_ratio > 1) + if (oversampling_ratio > 1) xfer.delay.value =3D T_CONVERT_0_NS + - T_CONVERT_X_NS * (st->oversampling_ratio - 1) * + T_CONVERT_X_NS * (oversampling_ratio - 1) * st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES; =20 return spi_sync_transfer(st->spi, &xfer, 1); @@ -735,20 +787,25 @@ static int ad7380_set_ch(struct ad7380_state *st, uns= igned int ch) * @st: device instance specific state * @scan_type: current scan type */ -static void ad7380_update_xfers(struct ad7380_state *st, +static int ad7380_update_xfers(struct ad7380_state *st, const struct iio_scan_type *scan_type) { struct spi_transfer *xfer =3D st->seq ? st->seq_xfer : st->normal_xfer; unsigned int t_convert =3D T_CONVERT_NS; + int oversampling_ratio, ret; =20 /* * In the case of oversampling, conversion time is higher than in normal * mode. Technically T_CONVERT_X_NS is lower for some chips, but we use * the maximum value for simplicity for now. */ - if (st->oversampling_ratio > 1) + ret =3D ad7380_get_osr(st, &oversampling_ratio); + if (ret) + return ret; + + if (oversampling_ratio > 1) t_convert =3D T_CONVERT_0_NS + T_CONVERT_X_NS * - (st->oversampling_ratio - 1) * + (oversampling_ratio - 1) * st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES; =20 if (st->seq) { @@ -761,7 +818,7 @@ static void ad7380_update_xfers(struct ad7380_state *st, st->chip_info->num_simult_channels; xfer[3].rx_buf =3D xfer[2].rx_buf + xfer[2].len; /* Additional delay required here when oversampling is enabled */ - if (st->oversampling_ratio > 1) + if (oversampling_ratio > 1) xfer[2].delay.value =3D t_convert; else xfer[2].delay.value =3D 0; @@ -773,6 +830,8 @@ static void ad7380_update_xfers(struct ad7380_state *st, xfer[1].len =3D BITS_TO_BYTES(scan_type->storagebits) * st->chip_info->num_simult_channels; } + + return 0; } =20 static int ad7380_triggered_buffer_preenable(struct iio_dev *indio_dev) @@ -780,6 +839,7 @@ static int ad7380_triggered_buffer_preenable(struct iio= _dev *indio_dev) struct ad7380_state *st =3D iio_priv(indio_dev); const struct iio_scan_type *scan_type; struct spi_message *msg =3D &st->normal_msg; + int ret; =20 /* * Currently, we always read all channels at the same time. The scan_type @@ -791,7 +851,6 @@ static int ad7380_triggered_buffer_preenable(struct iio= _dev *indio_dev) =20 if (st->chip_info->has_mux) { unsigned int index; - int ret; =20 /* * Depending on the requested scan_mask and current state, @@ -822,7 +881,9 @@ static int ad7380_triggered_buffer_preenable(struct iio= _dev *indio_dev) =20 } =20 - ad7380_update_xfers(st, scan_type); + ret =3D ad7380_update_xfers(st, scan_type); + if (ret) + return ret; =20 return spi_optimize_message(st->spi, msg); } @@ -895,7 +956,9 @@ static int ad7380_read_direct(struct ad7380_state *st, = unsigned int scan_index, return ret; } =20 - ad7380_update_xfers(st, scan_type); + ret =3D ad7380_update_xfers(st, scan_type); + if (ret) + return ret; =20 ret =3D spi_sync(st->spi, &st->normal_msg); if (ret < 0) @@ -973,7 +1036,16 @@ static int ad7380_read_raw(struct iio_dev *indio_dev, =20 return IIO_VAL_INT; case IIO_CHAN_INFO_OVERSAMPLING_RATIO: - *val =3D st->oversampling_ratio; + ret =3D iio_device_claim_direct_mode(indio_dev); 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[2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43661219a7csm160932535e9.24.2024.12.24.01.34.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 01:34:37 -0800 (PST) From: Julien Stephan Date: Tue, 24 Dec 2024 10:34:32 +0100 Subject: [PATCH RFC v2 3/4] iio: adc: ad7380: add alert support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241224-ad7380-add-alert-support-v2-3-7c89b2bf7cb3@baylibre.com> References: <20241224-ad7380-add-alert-support-v2-0-7c89b2bf7cb3@baylibre.com> In-Reply-To: <20241224-ad7380-add-alert-support-v2-0-7c89b2bf7cb3@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Jonathan Corbet Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.14.2 The alert functionality is an out of range indicator and can be used as an early indicator of an out of bounds conversion result. ALERT_LOW_THRESHOLD and ALERT_HIGH_THRESHOLD registers are common to all channels. When using 1 SDO line (only mode supported by the driver right now), i.e data outputs only on SDOA, SDOB (or SDOD for 4 channels variants) is used as an alert pin. The alert pin is updated at the end of the conversion (set to low if an alert occurs) and is cleared on a falling edge of CS. The ALERT register contains information about the exact alert status: channel and direction. Unfortunately we can't read this register because in buffered read we cannot claim for direct mode. User can set high/low thresholds and enable event detection using the regular iio events: events/in_thresh_falling_value events/in_thresh_rising_value events/thresh_either_en If the interrupt properties is present in the device tree, an IIO event will be generated for each interrupt received. Because we cannot read ALERT register, we can't determine the exact channel that triggers the alert, neither the direction (hight/low threshold violation), so we send and IIO_EV_DIR_EITHER event for all channels. In buffered reads, if input stays out of thresholds limit, an interrupt will be generated for each sample read, because the alert pin is cleared on a falling edge of CS (i.e when starting a new conversion). To avoid generating to much interrupt, we introduce a reset_timeout that can be used to disable interrupt for a given time (in ms) events/thresh_either_reset_timeout When an interrupt is received, interrupts are disabled and re-enabled after thresh_either_reset_timeout ms. If the reset timeout is set to 0, interrupt are re-enabled directly. Note: interrupts are always disabled at least during the handling of the previous interrupt, because each read triggers 2 transactions, that can lead to 2 interrupts for a single user read. IRQF_ONESHOT is not enough, because, it postpones the 2nd irq after the handling of the first one, which can still trigger 2 interrupts for a single user read. Signed-off-by: Julien Stephan --- drivers/iio/adc/ad7380.c | 354 +++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 350 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index b49067c36fdd1bb0e760faf71d7fa0c8c1f610e9..fb59c2c064f402ea797fc0e563b= d535d0e0bf785 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -34,6 +34,7 @@ #include =20 #include +#include #include #include #include @@ -112,6 +113,43 @@ struct ad7380_chip_info { const struct ad7380_timing_specs *timing_specs; }; =20 +static const struct iio_event_spec ad7380_events[] =3D { + { + .type =3D IIO_EV_TYPE_THRESH, + .dir =3D IIO_EV_DIR_RISING, + .mask_shared_by_dir =3D BIT(IIO_EV_INFO_VALUE), + }, + { + .type =3D IIO_EV_TYPE_THRESH, + .dir =3D IIO_EV_DIR_FALLING, + .mask_shared_by_dir =3D BIT(IIO_EV_INFO_VALUE), + }, + { + .type =3D IIO_EV_TYPE_THRESH, + .dir =3D IIO_EV_DIR_EITHER, + .mask_shared_by_all =3D BIT(IIO_EV_INFO_ENABLE), + }, +}; + +static const struct iio_event_spec ad7380_events_irq[] =3D { + { + .type =3D IIO_EV_TYPE_THRESH, + .dir =3D IIO_EV_DIR_RISING, + .mask_shared_by_dir =3D BIT(IIO_EV_INFO_VALUE), + }, + { + .type =3D IIO_EV_TYPE_THRESH, + .dir =3D IIO_EV_DIR_FALLING, + .mask_shared_by_dir =3D BIT(IIO_EV_INFO_VALUE), + }, + { + .type =3D IIO_EV_TYPE_THRESH, + .dir =3D IIO_EV_DIR_EITHER, + .mask_shared_by_all =3D BIT(IIO_EV_INFO_ENABLE) | + BIT(IIO_EV_INFO_RESET_TIMEOUT), + }, +}; + enum { AD7380_SCAN_TYPE_NORMAL, AD7380_SCAN_TYPE_RESOLUTION_BOOST, @@ -214,6 +252,8 @@ static const struct iio_scan_type ad7380_scan_type_16_u= [] =3D { .has_ext_scan_type =3D 1, \ .ext_scan_type =3D ad7380_scan_type_##bits##_##sign, \ .num_ext_scan_type =3D ARRAY_SIZE(ad7380_scan_type_##bits##_##sign), \ + .event_spec =3D ad7380_events, \ + .num_event_specs =3D ARRAY_SIZE(ad7380_events), \ } =20 #define AD7380_CHANNEL(index, bits, diff, sign) \ @@ -585,6 +625,10 @@ struct ad7380_state { bool resolution_boost_enabled; unsigned int ch; bool seq; + struct timer_list alert_timer; + unsigned int alert_reset_timeout_ms; + atomic_t irq_enabled; + bool buffered_read_enabled; unsigned int vref_mv; unsigned int vcm_mv[MAX_NUM_CHANNELS]; unsigned int gain_milli[MAX_NUM_CHANNELS]; @@ -689,6 +733,26 @@ static const struct regmap_config ad7380_regmap_config= =3D { .cache_type =3D REGCACHE_MAPLE, }; =20 +static void ad7380_enable_irq(struct ad7380_state *st) +{ + if (st->spi->irq && !atomic_cmpxchg(&st->irq_enabled, 0, 1)) + enable_irq(st->spi->irq); +} + +static void ad7380_disable_irq(struct ad7380_state *st) +{ + if (st->spi->irq && atomic_cmpxchg(&st->irq_enabled, 1, 0)) { + disable_irq(st->spi->irq); + synchronize_irq(st->spi->irq); + } +} + +static void ad7380_disable_irq_nosync(struct ad7380_state *st) +{ + if (st->spi->irq && atomic_cmpxchg(&st->irq_enabled, 1, 0)) + disable_irq_nosync(st->spi->irq); +} + static int ad7380_debugfs_reg_access(struct iio_dev *indio_dev, u32 reg, u32 writeval, u32 *readval) { @@ -727,8 +791,8 @@ static int ad7380_regval_to_osr(int regval) =20 static int ad7380_get_osr(struct ad7380_state *st, int *val) { - int tmp; - int ret =3D 0; + u32 tmp; + int ret; =20 ret =3D regmap_read(st->regmap, AD7380_REG_ADDR_CONFIG1, &tmp); if (ret) @@ -834,6 +898,13 @@ static int ad7380_update_xfers(struct ad7380_state *st, return 0; } =20 +static void ad7380_handle_event_reset_timeout(struct timer_list *t) +{ + struct ad7380_state *st =3D from_timer(st, t, alert_timer); + + ad7380_enable_irq(st); +} + static int ad7380_triggered_buffer_preenable(struct iio_dev *indio_dev) { struct ad7380_state *st =3D iio_priv(indio_dev); @@ -841,6 +912,12 @@ static int ad7380_triggered_buffer_preenable(struct ii= o_dev *indio_dev) struct spi_message *msg =3D &st->normal_msg; int ret; =20 + timer_setup(&st->alert_timer, ad7380_handle_event_reset_timeout, 0); + + ad7380_enable_irq(st); + + st->buffered_read_enabled =3D true; + /* * Currently, we always read all channels at the same time. The scan_type * is the same for all channels, so we just pass the first channel. @@ -894,6 +971,8 @@ static int ad7380_triggered_buffer_postdisable(struct i= io_dev *indio_dev) struct spi_message *msg =3D &st->normal_msg; int ret; =20 + st->buffered_read_enabled =3D false; + if (st->seq) { ret =3D regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG1, @@ -908,6 +987,9 @@ static int ad7380_triggered_buffer_postdisable(struct i= io_dev *indio_dev) =20 spi_unoptimize_message(msg); =20 + ad7380_disable_irq(st); + timer_shutdown_sync(&st->alert_timer); + return 0; } =20 @@ -1002,8 +1084,11 @@ static int ad7380_read_raw(struct iio_dev *indio_dev, if (ret) return ret; =20 - ret =3D ad7380_read_direct(st, chan->scan_index, - scan_type, val); + ad7380_enable_irq(st); + + ret =3D ad7380_read_direct(st, chan->scan_index, scan_type, val); + + ad7380_disable_irq(st); =20 iio_device_release_direct_mode(indio_dev); =20 @@ -1151,12 +1236,190 @@ static int ad7380_get_current_scan_type(const stru= ct iio_dev *indio_dev, : AD7380_SCAN_TYPE_NORMAL; } =20 +static int ad7380_read_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir) +{ + struct ad7380_state *st =3D iio_priv(indio_dev); + int alert_en, tmp, ret; + + ret =3D iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + ret =3D regmap_read(st->regmap, AD7380_REG_ADDR_CONFIG1, &tmp); + + iio_device_release_direct_mode(indio_dev); + + if (ret) + return ret; + + alert_en =3D FIELD_GET(AD7380_CONFIG1_ALERTEN, tmp); + + return alert_en; +} + +static int ad7380_write_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + bool state) +{ + struct ad7380_state *st =3D iio_priv(indio_dev); + int ret; + + ret =3D iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + ret =3D regmap_update_bits(st->regmap, + AD7380_REG_ADDR_CONFIG1, + AD7380_CONFIG1_ALERTEN, + FIELD_PREP(AD7380_CONFIG1_ALERTEN, state)); + + iio_device_release_direct_mode(indio_dev); + + if (ret) + return ret; + + return 0; +} + +static int ad7380_read_event_value(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, + int *val, int *val2) +{ + struct ad7380_state *st =3D iio_priv(indio_dev); + int ret, tmp; + + switch (info) { + case IIO_EV_INFO_VALUE: + ret =3D iio_device_claim_direct_mode(indio_dev); + + switch (dir) { + case IIO_EV_DIR_RISING: + ret =3D regmap_read(st->regmap, + AD7380_REG_ADDR_ALERT_HIGH_TH, + &tmp); + if (ret) + return ret; + + *val =3D FIELD_GET(AD7380_ALERT_HIGH_TH, tmp); + ret =3D IIO_VAL_INT; + break; + case IIO_EV_DIR_FALLING: + ret =3D regmap_read(st->regmap, + AD7380_REG_ADDR_ALERT_LOW_TH, + &tmp); + if (ret) + return ret; + + FIELD_GET(AD7380_ALERT_LOW_TH, tmp); + ret =3D IIO_VAL_INT; + break; + default: + ret =3D -EINVAL; + break; + } + + iio_device_release_direct_mode(indio_dev); + return ret; + case IIO_EV_INFO_RESET_TIMEOUT: + *val =3D st->alert_reset_timeout_ms; + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int ad7380_write_event_value(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, + int val, int val2) +{ + struct ad7380_state *st =3D iio_priv(indio_dev); + const struct iio_scan_type *scan_type; + int ret; + u16 th; + + switch (info) { + case IIO_EV_INFO_VALUE: + ret =3D iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + /* + * According to the datasheet, + * AD7380_REG_ADDR_ALERT_HIGH_TH[11:0] are the 12 MSB of the + * 16-bits internal alert high register. LSB are set to 0xf. + * AD7380_REG_ADDR_ALERT_LOW_TH[11:0] are the 12 MSB of the + * 16 bits internal alert low register. LSB are set to 0x0. + * + * When alert is enabled the conversion from the adc is compared + * immediately to the alert high/low thresholds, before any + * oversampling. This means that the thresholds are the same for + * normal mode and oversampling mode. + */ + + /* Extract the 12 MSB of val */ + scan_type =3D iio_get_current_scan_type(indio_dev, chan); + if (IS_ERR(scan_type)) + return PTR_ERR(scan_type); + + th =3D val >> (scan_type->realbits - 12); + + switch (dir) { + case IIO_EV_DIR_RISING: + ret =3D regmap_write(st->regmap, + AD7380_REG_ADDR_ALERT_HIGH_TH, + th); + if (ret) + return ret; + + break; + case IIO_EV_DIR_FALLING: + ret =3D regmap_write(st->regmap, + AD7380_REG_ADDR_ALERT_LOW_TH, + th); + if (ret) + return ret; + + break; + default: + ret =3D -EINVAL; + break; + } + + iio_device_release_direct_mode(indio_dev); + return ret; + case IIO_EV_INFO_RESET_TIMEOUT: + if (val < 0) + return -EINVAL; + st->alert_reset_timeout_ms =3D val; + timer_reduce(&st->alert_timer, jiffies + msecs_to_jiffies(val)); + + return 0; + default: + return -EINVAL; + } +} + static const struct iio_info ad7380_info =3D { .read_raw =3D &ad7380_read_raw, .read_avail =3D &ad7380_read_avail, .write_raw =3D &ad7380_write_raw, .get_current_scan_type =3D &ad7380_get_current_scan_type, .debugfs_reg_access =3D &ad7380_debugfs_reg_access, + .read_event_config =3D &ad7380_read_event_config, + .write_event_config =3D &ad7380_write_event_config, + .read_event_value =3D &ad7380_read_event_value, + .write_event_value =3D &ad7380_write_event_value, }; =20 static int ad7380_init(struct ad7380_state *st, bool external_ref_en) @@ -1182,6 +1445,12 @@ static int ad7380_init(struct ad7380_state *st, bool= external_ref_en) /* This is the default value after reset. */ st->ch =3D 0; st->seq =3D false; + st->buffered_read_enabled =3D false; + + /* + * Set a minimum default 1s delay between each alert in buffered reads + */ + st->alert_reset_timeout_ms =3D 1000; =20 /* SPI 1-wire mode */ return regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, @@ -1190,6 +1459,50 @@ static int ad7380_init(struct ad7380_state *st, bool= external_ref_en) AD7380_NUM_SDO_LINES)); } =20 +static irqreturn_t ad7380_primary_event_handler(int irq, void *private) +{ + struct iio_dev *indio_dev =3D private; + struct ad7380_state *st =3D iio_priv(indio_dev); + + if (!atomic_read(&st->irq_enabled)) + return IRQ_NONE; + + ad7380_disable_irq_nosync(st); + + return IRQ_WAKE_THREAD; +} + +static irqreturn_t ad7380_event_handler(int irq, void *private) +{ + struct iio_dev *indio_dev =3D private; + s64 timestamp =3D iio_get_time_ns(indio_dev); + struct ad7380_state *st =3D iio_priv(indio_dev); + const struct iio_chan_spec *chan =3D &indio_dev->channels[0]; + unsigned int i; + + for (i =3D 0; i < st->chip_info->num_channels - 1; i++) { + iio_push_event(indio_dev, + chan->differential ? + IIO_DIFF_EVENT_CODE(IIO_VOLTAGE, + 2 * i, + 2 * i + 1, + IIO_EV_TYPE_THRESH, + IIO_EV_DIR_EITHER) : + IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, + i, + IIO_EV_TYPE_THRESH, + IIO_EV_DIR_EITHER), + timestamp); + } + + if (st->spi->irq && st->buffered_read_enabled) + mod_timer(&st->alert_timer, + jiffies + + msecs_to_jiffies(st->alert_reset_timeout_ms)); + + return IRQ_HANDLED; +} + static int ad7380_probe(struct spi_device *spi) { struct device *dev =3D &spi->dev; @@ -1361,6 +1674,39 @@ static int ad7380_probe(struct spi_device *spi) indio_dev->modes =3D INDIO_DIRECT_MODE; indio_dev->available_scan_masks =3D st->chip_info->available_scan_masks; =20 + if (spi->irq) { + struct iio_chan_spec *chans; + size_t size; + int ret; + + ret =3D devm_request_threaded_irq(dev, spi->irq, + &ad7380_primary_event_handler, + &ad7380_event_handler, + IRQF_TRIGGER_FALLING | IRQF_ONESHOT + | IRQF_NO_AUTOEN, + indio_dev->name, + indio_dev); + if (ret) + return dev_err_probe(dev, ret, "Failed to request irq\n"); + + atomic_set(&st->irq_enabled, 0); + + /* + * Copy channels to be able to update the event_spec, since some + * attributes are visible only when irq are configured + */ + size =3D indio_dev->num_channels * sizeof(*indio_dev->channels); + chans =3D devm_kzalloc(dev, size, GFP_KERNEL); + if (!chans) + return -ENOMEM; + + memcpy(chans, indio_dev->channels, size); + chans->event_spec =3D ad7380_events_irq; + chans->num_event_specs =3D ARRAY_SIZE(ad7380_events_irq); + + indio_dev->channels =3D chans; + } + ret =3D devm_iio_triggered_buffer_setup(dev, indio_dev, iio_pollfunc_store_time, ad7380_trigger_handler, --=20 2.47.1 From nobody Sun Feb 8 20:37:56 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13631192D6A for ; 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Tue, 24 Dec 2024 01:34:39 -0800 (PST) Received: from [192.168.1.62] (2a02-842a-d52e-6101-6fd0-06c4-5d68-f0a5.rev.sfr.net. [2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43661219a7csm160932535e9.24.2024.12.24.01.34.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 01:34:38 -0800 (PST) From: Julien Stephan Date: Tue, 24 Dec 2024 10:34:33 +0100 Subject: [PATCH RFC v2 4/4] docs: iio: ad7380: add alert support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241224-ad7380-add-alert-support-v2-4-7c89b2bf7cb3@baylibre.com> References: <20241224-ad7380-add-alert-support-v2-0-7c89b2bf7cb3@baylibre.com> In-Reply-To: <20241224-ad7380-add-alert-support-v2-0-7c89b2bf7cb3@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Jonathan Corbet Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Julien Stephan X-Mailer: b4 0.14.2 Add a section for alert support, explaining how user can use iio events attributes to enable alert and set thresholds, but also what kind of events will be generated. Signed-off-by: Julien Stephan --- Documentation/iio/ad7380.rst | 56 ++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/Documentation/iio/ad7380.rst b/Documentation/iio/ad7380.rst index c46127700e14ca9ec3cac0bd5776b6702f2659e2..7cca4a9ad42ae8b3fda2e063ffd= 864ffa9dac2f1 100644 --- a/Documentation/iio/ad7380.rst +++ b/Documentation/iio/ad7380.rst @@ -92,6 +92,61 @@ must restart iiod using the following command: =20 root:~# systemctl restart iiod =20 +Alert +----- + +When configured in 1 SDO line mode (see `SPI wiring modes`_), the SDOB or = the +SDOD line (respectively for the 2 or 4 channels variants) can act as an al= ert +pin. + +At the end of a conversion the low-active alert pin gets asserted if the +conversion result exceeds the alert high limit or falls below the alert low +limit. It is cleared, on a falling edge of CS. The alert pin is common to = all +channels. + +User can enable alert using the regular iio events attribute: + +.. code-block:: bash + + events/thresh_either_en + +The high and low thresholds are common to all channels and can also be set= using +regular iio events attributes: + +.. code-block:: bash + + events/in_thresh_falling_value + events/in_thresh_rising_value + +User space IIO events +~~~~~~~~~~~~~~~~~~~~~ + +If the ``interrupts`` property is set in the device tree, IIO events will = be +generated for alerts. A register identifies the faulty channel, and direc= tion, +but during buffered reads, registers are inaccessible, making it impossibl= e to +know the exact channel triggering the alert. A generic event is sent for e= ach +channel, resulting in 2 or 4 events per alert, depending on the number of +channels: + +.. code-block:: bash + + Event: time: 1733501917162945723, type: voltage, channel: 0-1, evtype: th= resh, direction: either + Event: time: 1733501917162945723, type: voltage, channel: 2-3, evtype: th= resh, direction: either + + +Alert Reset timeout (buffered read only) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +In buffered reads, if input stays out of thresholds limit, an interrupt wi= ll be +generated for each sample read, because the alert pin is cleared when CS g= et +active (i.e when starting a new conversion). As a result, excessive event +generation can occur. User can set a reset timeout in milliseconds, during +which interrupt will be disabled: + +.. code-block:: bash + + events/thresh_either_reset_timeout + Channel selection and sequencer (single-end chips only) ------------------------------------------------------- =20 @@ -144,7 +199,6 @@ Unimplemented features - Rolling average oversampling - Power down mode - CRC indication -- Alert =20 =20 Device buffers --=20 2.47.1