From nobody Sun Feb 8 09:11:34 2026 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21A99566A for ; Fri, 20 Dec 2024 01:26:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734657981; cv=none; b=OzVWYyYCU7sYyQbLZxKGrvKu17WLB0AVU7yFjdje802qXye8o30MNCUKZrA4dUdIqfgUcy1xz0JVwb2oXbRhOGtlwlXp8g8IZv99EC4NM1y7MKKXc7QFpsmT7mj1IwRvxyAQ+WKTRTmBJUiQPuBjlrPOjYfMs99cg8w7W8LI9sY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734657981; c=relaxed/simple; bh=TCLXqwFwmLMDrwmuSpqcyB7EUIXvzRWGraQwEAz73Oo=; h=Date:Mime-Version:Message-ID:Subject:From:To:Cc:Content-Type; b=W4YHjvlgw4q4tH0HYiEzZOR/Z6p0FHoRU+iyquR2OczTRhgDI/BmQfKJvdka8e0+b6Gb3dG6vCdgorb9Eo+cTu1/4C3PuDQjC1EydGt7rPvzvTTXlVfSUe+AkyfUFhFhCaUeSGH31EchZMw5y/+jQzm+sWc5giNpx/OKLelcDDg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=kVbg8OIm; arc=none smtp.client-ip=209.85.216.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="kVbg8OIm" Received: by mail-pj1-f73.google.com with SMTP id 98e67ed59e1d1-2ee5668e09bso1308605a91.3 for ; Thu, 19 Dec 2024 17:26:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1734657979; x=1735262779; darn=vger.kernel.org; h=cc:to:from:subject:message-id:mime-version:date:reply-to:from:to:cc :subject:date:message-id:reply-to; bh=QWYvHz9fM4KjcB+AnKzAVNHAbTmmX5uwW6sODCmo1gs=; b=kVbg8OImxs8HMioudnOESEpoV5qjw2ULbRWsXxk90pyLAk6ys4Ar9Jb4AHCLb96Ue6 EurutWzgF76yGIGO52IVnYPKPsLL7HjDhWU2s95PZ89F7CIx/8ETG6+I4OrnCDYi3wKB yMesN4OcUXQyCX8UxBufq01ryR/BjHyQoyBAfg7Qoyqr+OLdqddgaU/U/Ifoo9Z8UBiv eJgBnUW2fyp844vuMgCPmmZXaBPTX/GEt3lHeVlL8jpWZtnLRznaYYKpvYUBsHvB3+JO wVOX7c7dP5SzZUkwVS824bb0ZDnIBbSbUZ1U5WdPV0lRTEr6XyPGcLyjxUsPGT/bMQly z97g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734657979; x=1735262779; h=cc:to:from:subject:message-id:mime-version:date:reply-to :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=QWYvHz9fM4KjcB+AnKzAVNHAbTmmX5uwW6sODCmo1gs=; b=T0FzEZtETddlPBVYGhSKh7nL3GpVFIidQHMLcrRUPy1xEib4narwPqRcOngMeh/Cgn qYpB35jEq8yXk2RZA2yR6uCKD9/Xu+DF0TeBZ9zJASNl4ACwxtGRE2xo6oeCDJTT2E3w b3/2KNitulLRlEBSrMzP/QyNBI+AhyAAwG3QIPVSS3okhbDZWH4i12ayWkiCybEsTlKv o6TXGyAWGGYb72ttvf1bEi7vGYR/b7ppl50EscQIrLljF3heyoMM76M6XkEONlWiu6Rx oZvfd2kL8TQsCDWPxVv6hxCS0GeZqZChYUmwRU/FwpD+DdXpUMNML0b5vMpuHWJmqHvD B9Jg== X-Forwarded-Encrypted: i=1; AJvYcCWlIo/t+O8u7vTRChrRQYZA/exYdGT1IaRDgt8RLFJD5nU0VvIkDeNw9UxCYg6hobn/Ua98K1DumWVtspg=@vger.kernel.org X-Gm-Message-State: AOJu0Yxw18NbkX9vWlX7+kqqIvYwSTzUDUCGgP1aYifcK7NslIFpC1Sw kBfy4A/+ExaSzN+yIqUq3flLZQb6sRYwfcuap+hnToQkJzj25zTnj5DMuwu7lttViwsR+MFTMyG q/w== X-Google-Smtp-Source: AGHT+IG+5c9SrJO5xry8RVPssSWfXw9IHN+FSthC+5Hv7QBecTBRBBhL3VDJOaA1466ABt58kduoIeSJmJc= X-Received: from pjyr15.prod.google.com ([2002:a17:90a:e18f:b0:2f4:47fc:7f17]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:5183:b0:2ee:5111:a54b with SMTP id 98e67ed59e1d1-2f452eec7dcmr1409339a91.31.1734657979513; Thu, 19 Dec 2024 17:26:19 -0800 (PST) Reply-To: Sean Christopherson Date: Thu, 19 Dec 2024 17:26:17 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 X-Mailer: git-send-email 2.47.1.613.gc27f4b7a9f-goog Message-ID: <20241220012617.3513898-1-seanjc@google.com> Subject: [PATCH] KVM: selftests: Add helpers for locally (un)blocking IRQs on x86 From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Manali Shukla Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Copy KVM-Unit-Tests' x86 helpers for emitting STI and CLI, comments and all, and use them throughout x86 selftests. The safe_halt() and sti_nop() logic in particular benefits from centralized comments, as the behavior isn't obvious unless the reader is already aware of the STI shadow. Cc: Manali Shukla Signed-off-by: Sean Christopherson --- .../selftests/kvm/include/x86/processor.h | 40 +++++++++++++++++++ tools/testing/selftests/kvm/x86/hyperv_ipi.c | 6 ++- .../selftests/kvm/x86/svm_int_ctl_test.c | 5 +-- .../selftests/kvm/x86/ucna_injection_test.c | 2 +- .../selftests/kvm/x86/xapic_ipi_test.c | 3 +- .../selftests/kvm/x86/xapic_state_test.c | 4 +- .../selftests/kvm/x86/xen_shinfo_test.c | 5 +-- 7 files changed, 51 insertions(+), 14 deletions(-) diff --git a/tools/testing/selftests/kvm/include/x86/processor.h b/tools/te= sting/selftests/kvm/include/x86/processor.h index d60da8966772..1f9798ed71f1 100644 --- a/tools/testing/selftests/kvm/include/x86/processor.h +++ b/tools/testing/selftests/kvm/include/x86/processor.h @@ -1339,6 +1339,46 @@ static inline void kvm_hypercall_map_gpa_range(uint6= 4_t gpa, uint64_t size, GUEST_ASSERT(!ret); } =20 +/* + * Execute HLT in an STI interrupt shadow to ensure that a pending IRQ tha= t's + * intended to be a wake event arrives *after* HLT is executed. Modern CP= Us, + * except for a few oddballs that KVM is unlikely to run on, block IRQs fo= r one + * instruction after STI, *if* RFLAGS.IF=3D0 before STI. Note, Intel CPUs= may + * block other events beyond regular IRQs, e.g. may block NMIs and SMIs to= o. + */ +static inline void safe_halt(void) +{ + asm volatile("sti; hlt"); +} + +/* + * Enable interrupts and ensure that interrupts are evaluated upon return = from + * this function, i.e. execute a nop to consume the STi interrupt shadow. + */ +static inline void sti_nop(void) +{ + asm volatile ("sti; nop"); +} + +/* + * Enable interrupts for one instruction (nop), to allow the CPU to proces= s all + * interrupts that are already pending. + */ +static inline void sti_nop_cli(void) +{ + asm volatile ("sti; nop; cli"); +} + +static inline void sti(void) +{ + asm volatile("sti"); +} + +static inline void cli(void) +{ + asm volatile ("cli"); +} + void __vm_xsave_require_permission(uint64_t xfeature, const char *name); =20 #define vm_xsave_require_permission(xfeature) \ diff --git a/tools/testing/selftests/kvm/x86/hyperv_ipi.c b/tools/testing/s= elftests/kvm/x86/hyperv_ipi.c index 22c0c124582f..2b5b4bc6ef7e 100644 --- a/tools/testing/selftests/kvm/x86/hyperv_ipi.c +++ b/tools/testing/selftests/kvm/x86/hyperv_ipi.c @@ -63,8 +63,10 @@ static void receiver_code(void *hcall_page, vm_vaddr_t p= gs_gpa) /* Signal sender vCPU we're ready */ ipis_rcvd[vcpu_id] =3D (u64)-1; =20 - for (;;) - asm volatile("sti; hlt; cli"); + for (;;) { + safe_halt(); + cli(); + } } =20 static void guest_ipi_handler(struct ex_regs *regs) diff --git a/tools/testing/selftests/kvm/x86/svm_int_ctl_test.c b/tools/tes= ting/selftests/kvm/x86/svm_int_ctl_test.c index 916e04248fbb..917b6066cfc1 100644 --- a/tools/testing/selftests/kvm/x86/svm_int_ctl_test.c +++ b/tools/testing/selftests/kvm/x86/svm_int_ctl_test.c @@ -42,10 +42,7 @@ static void l2_guest_code(struct svm_test_data *svm) x2apic_write_reg(APIC_ICR, APIC_DEST_SELF | APIC_INT_ASSERT | INTR_IRQ_NUMBER); =20 - __asm__ __volatile__( - "sti\n" - "nop\n" - ); + sti_nop(); =20 GUEST_ASSERT(vintr_irq_called); GUEST_ASSERT(intr_irq_called); diff --git a/tools/testing/selftests/kvm/x86/ucna_injection_test.c b/tools/= testing/selftests/kvm/x86/ucna_injection_test.c index 57f157c06b39..1e5e564523b3 100644 --- a/tools/testing/selftests/kvm/x86/ucna_injection_test.c +++ b/tools/testing/selftests/kvm/x86/ucna_injection_test.c @@ -86,7 +86,7 @@ static void ucna_injection_guest_code(void) wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN); =20 /* Enables interrupt in guest. */ - asm volatile("sti"); + sti(); =20 /* Let user space inject the first UCNA */ GUEST_SYNC(SYNC_FIRST_UCNA); diff --git a/tools/testing/selftests/kvm/x86/xapic_ipi_test.c b/tools/testi= ng/selftests/kvm/x86/xapic_ipi_test.c index a76078a08ff8..6228c0806e89 100644 --- a/tools/testing/selftests/kvm/x86/xapic_ipi_test.c +++ b/tools/testing/selftests/kvm/x86/xapic_ipi_test.c @@ -106,7 +106,8 @@ static void halter_guest_code(struct test_data_page *da= ta) data->halter_tpr =3D xapic_read_reg(APIC_TASKPRI); data->halter_ppr =3D xapic_read_reg(APIC_PROCPRI); data->hlt_count++; - asm volatile("sti; hlt; cli"); + safe_halt(); + cli(); data->wake_count++; } } diff --git a/tools/testing/selftests/kvm/x86/xapic_state_test.c b/tools/tes= ting/selftests/kvm/x86/xapic_state_test.c index 88bcca188799..fdebff1165c7 100644 --- a/tools/testing/selftests/kvm/x86/xapic_state_test.c +++ b/tools/testing/selftests/kvm/x86/xapic_state_test.c @@ -18,7 +18,7 @@ struct xapic_vcpu { =20 static void xapic_guest_code(void) { - asm volatile("cli"); + cli(); =20 xapic_enable(); =20 @@ -38,7 +38,7 @@ static void xapic_guest_code(void) =20 static void x2apic_guest_code(void) { - asm volatile("cli"); + cli(); =20 x2apic_enable(); =20 diff --git a/tools/testing/selftests/kvm/x86/xen_shinfo_test.c b/tools/test= ing/selftests/kvm/x86/xen_shinfo_test.c index a59b3c799bb2..287829f850f7 100644 --- a/tools/testing/selftests/kvm/x86/xen_shinfo_test.c +++ b/tools/testing/selftests/kvm/x86/xen_shinfo_test.c @@ -191,10 +191,7 @@ static void guest_code(void) struct vcpu_runstate_info *rs =3D (void *)RUNSTATE_VADDR; int i; =20 - __asm__ __volatile__( - "sti\n" - "nop\n" - ); + sti_nop(); =20 /* Trigger an interrupt injection */ GUEST_SYNC(TEST_INJECT_VECTOR); base-commit: dcab55cef6f247a71a75a239d4063018dc83a671 --=20 2.47.1.613.gc27f4b7a9f-goog