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[34.34.173.130]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c832e74sm4044313f8f.30.2024.12.20.05.49.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2024 05:49:59 -0800 (PST) From: Tudor Ambarus Date: Fri, 20 Dec 2024 13:49:56 +0000 Subject: [PATCH v6 1/5] dt-bindings: mailbox: allow #mbox-cells = <0>; Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241220-acpm-v4-upstream-mbox-v6-1-a6942806e52a@linaro.org> References: <20241220-acpm-v4-upstream-mbox-v6-0-a6942806e52a@linaro.org> In-Reply-To: <20241220-acpm-v4-upstream-mbox-v6-0-a6942806e52a@linaro.org> To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Alim Akhtar Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, daniel.lezcano@linaro.org, vincent.guittot@linaro.org, ulf.hansson@linaro.org, arnd@arndb.de, Tudor Ambarus X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734702598; l=1213; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=98UdmgNXZR4Odm8WAK3DNauL946xSKIV8vPYFoFzXtc=; b=L27tekKbbbVcK6U5BoYlAcu5YGoP7VilFJa2kRv2a4piHaSjgl6c8pZq3lyr2xXRNPu1TQkQh AuzOHGFoQW1DsplvHHW5KhfrQXyL0uUAXa/BQ4Qcems105t6N1TPsWA X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= There are mailbox clients that can discover the mailbox channel identifiers at runtime. For such cases passing the channel identifiers via DT is redundant. The framework API will be supplied with mbox_request_channel_by_args(). It will allow clients to request a mailbox channel using the runtime discovered channel identifiers. Add support for referencing controllers solely by phandle. Signed-off-by: Tudor Ambarus Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mailbox/mailbox.txt | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox/mailbox.txt b/Docume= ntation/devicetree/bindings/mailbox/mailbox.txt index af8ecee2ac68..fc31a4a3b637 100644 --- a/Documentation/devicetree/bindings/mailbox/mailbox.txt +++ b/Documentation/devicetree/bindings/mailbox/mailbox.txt @@ -6,8 +6,7 @@ assign appropriate mailbox channel to client drivers. * Mailbox Controller =20 Required property: -- #mbox-cells: Must be at least 1. Number of cells in a mailbox - specifier. +- #mbox-cells: Must be at least 0. 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[34.34.173.130]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c832e74sm4044313f8f.30.2024.12.20.05.50.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2024 05:50:00 -0800 (PST) From: Tudor Ambarus Date: Fri, 20 Dec 2024 13:49:57 +0000 Subject: [PATCH v6 2/5] dt-bindings: mailbox: add google,gs101-mbox Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241220-acpm-v4-upstream-mbox-v6-2-a6942806e52a@linaro.org> References: <20241220-acpm-v4-upstream-mbox-v6-0-a6942806e52a@linaro.org> In-Reply-To: <20241220-acpm-v4-upstream-mbox-v6-0-a6942806e52a@linaro.org> To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Alim Akhtar Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, daniel.lezcano@linaro.org, vincent.guittot@linaro.org, ulf.hansson@linaro.org, arnd@arndb.de, Tudor Ambarus X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734702598; l=3101; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=gc/x/vd/iTT6DgRuhTHKKXPn1qQVX3+uctKpzIwRy8k=; b=1yqD4Mr6+HTppBrswLA85XgGW1DxBWk3OZasij4CNC75DdzHxr/YW9Uc8Rmqtjk0KoCQpB3uz qEW29wjIKGVDt2tWSzFxK7GDD7pOdikK2I0UV7O+C4Hcq7ipm9gl7Eb X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add bindings for the Samsung Exynos Mailbox Controller. Signed-off-by: Tudor Ambarus --- .../bindings/mailbox/google,gs101-mbox.yaml | 70 ++++++++++++++++++= ++++ include/dt-bindings/mailbox/google,gs101.h | 14 +++++ 2 files changed, 84 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/google,gs101-mbox.ya= ml b/Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml new file mode 100644 index 000000000000..a1fbc3b2b9de --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2024 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/google,gs101-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos Mailbox Controller + +maintainers: + - Tudor Ambarus + +description: | + The Samsung Exynos mailbox controller, used on Google GS101 SoC, has 16 = flag + bits for hardware interrupt generation and a shared register for passing + mailbox messages. When the controller is used by the ACPM protocol the s= hared + register is ignored and the mailbox controller acts as a doorbell. + The controller just raises the interrupt to the firmware after the + ACPM protocol has written the message to SRAM. + +properties: + compatible: + const: google,gs101-mbox + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pclk + + interrupts: + description: IRQ line for the RX mailbox. + maxItems: 1 + + '#mbox-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - '#mbox-cells' + +additionalProperties: false + +examples: + # Doorbell mode. + - | + #include + #include + + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + + ap2apm_mailbox: mailbox@17610000 { + compatible =3D "google,gs101-mbox"; + reg =3D <0x17610000 0x1000>; + clocks =3D <&cmu_apm CLK_GOUT_APM_MAILBOX_APM_AP_PCLK>; + clock-names =3D "pclk"; + interrupts =3D ; + #mbox-cells =3D <0>; + }; + }; diff --git a/include/dt-bindings/mailbox/google,gs101.h b/include/dt-bindin= gs/mailbox/google,gs101.h new file mode 100644 index 000000000000..7ff4fe669f9e --- /dev/null +++ b/include/dt-bindings/mailbox/google,gs101.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2024 Linaro Ltd. + * + * This header provides constants for the defined mailbox channel types. + */ + +#ifndef _DT_BINDINGS_MAILBOX_GOOGLE_GS101_H +#define _DT_BINDINGS_MAILBOX_GOOGLE_GS101_H + +#define DOORBELL 0 +#define DATA 1 + +#endif /* _DT_BINDINGS_MAILBOX_GOOGLE_GS101_H */ --=20 2.47.1.613.gc27f4b7a9f-goog From nobody Fri Dec 19 06:37:29 2025 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C823E21A421 for ; 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[34.34.173.130]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c832e74sm4044313f8f.30.2024.12.20.05.50.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2024 05:50:01 -0800 (PST) From: Tudor Ambarus Date: Fri, 20 Dec 2024 13:49:58 +0000 Subject: [PATCH v6 3/5] mailbox: add support for clients to request channels by args Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241220-acpm-v4-upstream-mbox-v6-3-a6942806e52a@linaro.org> References: <20241220-acpm-v4-upstream-mbox-v6-0-a6942806e52a@linaro.org> In-Reply-To: <20241220-acpm-v4-upstream-mbox-v6-0-a6942806e52a@linaro.org> To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Alim Akhtar Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, daniel.lezcano@linaro.org, vincent.guittot@linaro.org, ulf.hansson@linaro.org, arnd@arndb.de, Tudor Ambarus X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734702598; l=5904; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=yyB5CQGhVmNL0L7BcpLJ32JRUO4zLOTRcjHSgygE7Ik=; b=vsmN1tUctzs2mQxUDHpQYFZZw2uQY7/lH7aU0MJkG/FL5nc9qKT2nTT5HYlqjC6BnhqU8Jipu zaGST/SqFPyALdMnBZnXEks6QaRLLJw/KxnPYpoXUa0ql5fqZ+5W8/P X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= There are clients that can discover channel identifiers at runtime by parsing a shared memory for example, as in the ACPM interface's case. Supply a new framework API: mbox_request_channel_by_args(). It works by supplying the usual client pointer as the first argument, the usual index of the mailbox specifier in the 'mboxes' property as a second argument, and a pointer to a 'const struct mbox_xlate_args' as a third. The newly introduced struct is modeled after 'struct of_phandle_args'. The API identifies the controller's device node, and then calls that controller's xlate() method that will return a pointer to a mbox_chan or a ERR_PTR. The binding between the channel and the client is done in the typical way. Signed-off-by: Tudor Ambarus --- drivers/mailbox/mailbox.c | 60 ++++++++++++++++++++++++++++++++++= ++++ include/linux/mailbox.h | 17 +++++++++++ include/linux/mailbox_client.h | 3 ++ include/linux/mailbox_controller.h | 4 +++ 4 files changed, 84 insertions(+) diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c index d3d26a2c9895..0eecffd5a2ad 100644 --- a/drivers/mailbox/mailbox.c +++ b/drivers/mailbox/mailbox.c @@ -467,6 +467,66 @@ struct mbox_chan *mbox_request_channel_byname(struct m= box_client *cl, } EXPORT_SYMBOL_GPL(mbox_request_channel_byname); =20 +/** + * mbox_request_channel_by_args - request a mailbox channel using client's + * channel identifiers. + * @cl: identity of the client requesting the channel. + * @index: index of mailbox specifier in 'mboxes' property. + * @spec: arguments that describe the channel. + * + * Used by clients that can discover the channel identifiers at runtime (by + * parsing a shared memory for example). The description of + * mbox_request_channel() applies here as well. + * + * Return: Pointer to the channel assigned to the client if successful. + * ERR_PTR for request failure. + */ +struct mbox_chan *mbox_request_channel_by_args(struct mbox_client *cl, + int index, const struct mbox_xlate_args *mbox_spec) +{ + struct of_phandle_args of_args; + struct device *dev =3D cl->dev; + struct mbox_controller *mbox; + struct mbox_chan *chan; + int ret; + + if (!dev || !dev->of_node) { + pr_debug("%s: No owner device node\n", __func__); + return ERR_PTR(-ENODEV); + } + + if (of_parse_phandle_with_args(dev->of_node, "mboxes", + "#mbox-cells", index, &of_args)) { + dev_dbg(dev, "%s: can't parse \"mboxes\" property\n", __func__); + return ERR_PTR(-ENODEV); + } + + mutex_lock(&con_mutex); + + chan =3D ERR_PTR(-EPROBE_DEFER); + list_for_each_entry(mbox, &mbox_cons, node) + if (mbox->dev->of_node =3D=3D of_args.np && mbox->xlate) { + chan =3D mbox->xlate(mbox, mbox_spec); + if (!IS_ERR(chan)) + break; + } + + of_node_put(of_args.np); + + if (IS_ERR(chan)) { + mutex_unlock(&con_mutex); + return chan; + } + + ret =3D __mbox_bind_client(chan, cl); + if (ret) + chan =3D ERR_PTR(ret); + + mutex_unlock(&con_mutex); + return chan; +} +EXPORT_SYMBOL_GPL(mbox_request_channel_by_args); + /** * mbox_free_channel - The client relinquishes control of a mailbox * channel by this call. diff --git a/include/linux/mailbox.h b/include/linux/mailbox.h new file mode 100644 index 000000000000..cef88c5ae49d --- /dev/null +++ b/include/linux/mailbox.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2024 Linaro Ltd. + */ + +#ifndef __LINUX_MAILBOX_H +#define __LINUX_MAILBOX_H + +#include + +#define MBOX_XLATE_MAX_ARGS 16 +struct mbox_xlate_args { + int args_count; + u32 args[MBOX_XLATE_MAX_ARGS]; +}; + +#endif /* __LINUX_MAILBOX_H */ diff --git a/include/linux/mailbox_client.h b/include/linux/mailbox_client.h index 734694912ef7..06e2721313ca 100644 --- a/include/linux/mailbox_client.h +++ b/include/linux/mailbox_client.h @@ -9,6 +9,7 @@ =20 #include #include +#include =20 struct mbox_chan; =20 @@ -41,6 +42,8 @@ int mbox_bind_client(struct mbox_chan *chan, struct mbox_= client *cl); struct mbox_chan *mbox_request_channel_byname(struct mbox_client *cl, const char *name); struct mbox_chan *mbox_request_channel(struct mbox_client *cl, int index); +struct mbox_chan *mbox_request_channel_by_args(struct mbox_client *cl, + int index, const struct mbox_xlate_args *mbox_spec); int mbox_send_message(struct mbox_chan *chan, void *mssg); int mbox_flush(struct mbox_chan *chan, unsigned long timeout); void mbox_client_txdone(struct mbox_chan *chan, int r); /* atomic */ diff --git a/include/linux/mailbox_controller.h b/include/linux/mailbox_con= troller.h index 6fee33cb52f5..dfddcf966f9f 100644 --- a/include/linux/mailbox_controller.h +++ b/include/linux/mailbox_controller.h @@ -8,6 +8,7 @@ #include #include #include +#include =20 struct mbox_chan; =20 @@ -67,6 +68,7 @@ struct mbox_chan_ops { * @txpoll_period: If 'txdone_poll' is in effect, the API polls for * last TX's status after these many millisecs * @of_xlate: Controller driver specific mapping of channel via DT + * @xlate: Controller driver specific mapping of channel * @poll_hrt: API private. hrtimer used to poll for TXDONE on all * channels. * @node: API private. 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[34.34.173.130]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c832e74sm4044313f8f.30.2024.12.20.05.50.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2024 05:50:02 -0800 (PST) From: Tudor Ambarus Date: Fri, 20 Dec 2024 13:49:59 +0000 Subject: [PATCH v6 4/5] mailbox: add Samsung Exynos driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241220-acpm-v4-upstream-mbox-v6-4-a6942806e52a@linaro.org> References: <20241220-acpm-v4-upstream-mbox-v6-0-a6942806e52a@linaro.org> In-Reply-To: <20241220-acpm-v4-upstream-mbox-v6-0-a6942806e52a@linaro.org> To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Alim Akhtar Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, daniel.lezcano@linaro.org, vincent.guittot@linaro.org, ulf.hansson@linaro.org, arnd@arndb.de, Tudor Ambarus X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734702598; l=7455; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=8V4hRjvTjS/OPHho+b5gFECG0twWFwovkcgrCiubsOw=; b=aFSKkY8CH0jktsAVfeCjhnjjDoAFx4ULnLvakRK6H6Z+77IEJyqtRBaxSWah93ELQ7I8E4wWw nM/5nv7SeA+A0J15n+UpbuzK9zJ4psVXCTpXcGxYoVWX9ALZbNSHk2w X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= The Samsung Exynos mailbox controller, used on Google GS101 SoC, has 16 flag bits for hardware interrupt generation and a shared register for passing mailbox messages. When the controller is used by the ACPM protocol the shared register is ignored and the mailbox controller acts as a doorbell. The controller just raises the interrupt to APM after the ACPM protocol has written the message to SRAM. Add support for the Samsung Exynos mailbox controller. Signed-off-by: Tudor Ambarus --- drivers/mailbox/Kconfig | 11 +++ drivers/mailbox/Makefile | 2 + drivers/mailbox/exynos-mailbox.c | 174 +++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 187 insertions(+) diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 8ecba7fb999e..44b808c4d97f 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -36,6 +36,17 @@ config ARM_MHU_V3 that provides different means of transports: supported extensions will be discovered and possibly managed at probe-time. =20 +config EXYNOS_MBOX + tristate "Exynos Mailbox" + depends on ARCH_EXYNOS || COMPILE_TEST + help + Say Y here if you want to build the Samsung Exynos Mailbox controller + driver. The controller has 16 flag bits for hardware interrupt + generation and a shared register for passing mailbox messages. + When the controller is used by the ACPM protocol the shared register + is ignored and the mailbox controller acts as a doorbell that raises + the interrupt to the ACPM firmware. + config IMX_MBOX tristate "i.MX Mailbox" depends on ARCH_MXC || COMPILE_TEST diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 5f4f5b0ce2cc..86192b5c7c32 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -11,6 +11,8 @@ obj-$(CONFIG_ARM_MHU_V2) +=3D arm_mhuv2.o =20 obj-$(CONFIG_ARM_MHU_V3) +=3D arm_mhuv3.o =20 +obj-$(CONFIG_EXYNOS_MBOX) +=3D exynos-mailbox.o + obj-$(CONFIG_IMX_MBOX) +=3D imx-mailbox.o =20 obj-$(CONFIG_ARMADA_37XX_RWTM_MBOX) +=3D armada-37xx-rwtm-mailbox.o diff --git a/drivers/mailbox/exynos-mailbox.c b/drivers/mailbox/exynos-mail= box.c new file mode 100644 index 000000000000..07bbc6b442ef --- /dev/null +++ b/drivers/mailbox/exynos-mailbox.c @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 Samsung Electronics Co., Ltd. + * Copyright 2020 Google LLC. + * Copyright 2024 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EXYNOS_MBOX_MCUCTRL 0x0 /* Mailbox Control Register */ +#define EXYNOS_MBOX_INTCR0 0x24 /* Interrupt Clear Register 0 */ +#define EXYNOS_MBOX_INTMR0 0x28 /* Interrupt Mask Register 0 */ +#define EXYNOS_MBOX_INTSR0 0x2c /* Interrupt Status Register 0 */ +#define EXYNOS_MBOX_INTMSR0 0x30 /* Interrupt Mask Status Register 0 */ +#define EXYNOS_MBOX_INTGR1 0x40 /* Interrupt Generation Register 1 */ +#define EXYNOS_MBOX_INTMR1 0x48 /* Interrupt Mask Register 1 */ +#define EXYNOS_MBOX_INTSR1 0x4c /* Interrupt Status Register 1 */ +#define EXYNOS_MBOX_INTMSR1 0x50 /* Interrupt Mask Status Register 1 */ + +#define EXYNOS_MBOX_INTMR0_MASK GENMASK(15, 0) +#define EXYNOS_MBOX_INTGR1_MASK GENMASK(15, 0) + +#define EXYNOS_MBOX_CHAN_COUNT HWEIGHT32(EXYNOS_MBOX_INTGR1_MASK) + +enum { + EXYNOS_MBOX_CELL_ID, + EXYNOS_MBOX_CELL_TYPE, + EXYNOS_MBOX_CELLS +}; + +#define EXYNOS_MBOX_CELL_TYPE_COUNT 2 + +/** + * struct exynos_mbox - driver's private data. + * @regs: mailbox registers base address. + * @mbox: pointer to the mailbox controller. + * @dev: pointer to the mailbox device. + * @pclk: pointer to the mailbox peripheral clock. + */ +struct exynos_mbox { + void __iomem *regs; + struct mbox_controller *mbox; + struct device *dev; + struct clk *pclk; +}; + +static inline int exynos_mbox_chan_index(struct mbox_chan *chan) +{ + return chan - chan->mbox->chans; +} + +static int exynos_mbox_send_data(struct mbox_chan *chan, void *data) +{ + struct exynos_mbox *exynos_mbox =3D dev_get_drvdata(chan->mbox->dev); + int index =3D exynos_mbox_chan_index(chan); + + writel(BIT(index), exynos_mbox->regs + EXYNOS_MBOX_INTGR1); + + return 0; +} + +static const struct mbox_chan_ops exynos_mbox_chan_ops =3D { + .send_data =3D exynos_mbox_send_data, +}; + +static struct mbox_chan *exynos_mbox_xlate(struct mbox_controller *mbox, + const struct mbox_xlate_args *sp) +{ + u32 id, type; + + if (sp->args_count !=3D EXYNOS_MBOX_CELLS) { + dev_err(mbox->dev, "Invalid argument count %d\n", + sp->args_count); + return ERR_PTR(-EINVAL); + } + + id =3D sp->args[EXYNOS_MBOX_CELL_ID]; + if (id >=3D mbox->num_chans) { + dev_err(mbox->dev, "Invalid channel ID %d\n", id); + return ERR_PTR(-EINVAL); + } + + type =3D sp->args[EXYNOS_MBOX_CELL_TYPE]; + if (type >=3D EXYNOS_MBOX_CELL_TYPE_COUNT) { + dev_err(mbox->dev, "Invalid channel type %d\n", type); + return ERR_PTR(-EINVAL); + } + + if (type =3D=3D DATA) { + dev_err(mbox->dev, "DATA channel type [%d] not supported\n", + type); + return ERR_PTR(-EINVAL); + }; + + return &mbox->chans[id]; +} + +static const struct of_device_id exynos_mbox_match[] =3D { + { .compatible =3D "google,gs101-mbox" }, + {}, +}; +MODULE_DEVICE_TABLE(of, exynos_mbox_match); + +static int exynos_mbox_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct exynos_mbox *exynos_mbox; + struct mbox_controller *mbox; + struct mbox_chan *chans; + int i; + + exynos_mbox =3D devm_kzalloc(dev, sizeof(*exynos_mbox), GFP_KERNEL); + if (!exynos_mbox) + return -ENOMEM; + + mbox =3D devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); + if (!mbox) + return -ENOMEM; + + chans =3D devm_kcalloc(dev, EXYNOS_MBOX_CHAN_COUNT, sizeof(*chans), + GFP_KERNEL); + if (!chans) + return -ENOMEM; + + exynos_mbox->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(exynos_mbox->regs)) + return PTR_ERR(exynos_mbox->regs); + + exynos_mbox->pclk =3D devm_clk_get_enabled(dev, "pclk"); + if (IS_ERR(exynos_mbox->pclk)) + return dev_err_probe(dev, PTR_ERR(exynos_mbox->pclk), + "Failed to enable clock.\n"); + + mbox->num_chans =3D EXYNOS_MBOX_CHAN_COUNT; + mbox->chans =3D chans; + mbox->dev =3D dev; + mbox->ops =3D &exynos_mbox_chan_ops; + mbox->xlate =3D exynos_mbox_xlate; + + for (i =3D 0; i < EXYNOS_MBOX_CHAN_COUNT; i++) + chans[i].mbox =3D mbox; + + exynos_mbox->dev =3D dev; + exynos_mbox->mbox =3D mbox; + + platform_set_drvdata(pdev, exynos_mbox); + + /* Mask out all interrupts. We support just polling channels for now. */ + writel(EXYNOS_MBOX_INTMR0_MASK, exynos_mbox->regs + EXYNOS_MBOX_INTMR0); + + return devm_mbox_controller_register(dev, mbox); +} + +static struct platform_driver exynos_mbox_driver =3D { + .probe =3D exynos_mbox_probe, + .driver =3D { + .name =3D "exynos-acpm-mbox", + .of_match_table =3D exynos_mbox_match, + }, +}; +module_platform_driver(exynos_mbox_driver); + +MODULE_AUTHOR("Tudor Ambarus "); +MODULE_DESCRIPTION("Samsung Exynos mailbox driver"); +MODULE_LICENSE("GPL"); --=20 2.47.1.613.gc27f4b7a9f-goog From nobody Fri Dec 19 06:37:29 2025 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6834B21A45B for ; Fri, 20 Dec 2024 13:50:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734702608; cv=none; b=EGitbfActLG5mtKZDY+/vSZv1vcgP1PvVa8Vmww/iuoUYLyf/XSCyp5NNRUVB51w1m9W1ftVb0EMWG7h8hZ42VEmCkbJhtyU2VHkJly2CvLsgeEu805Z/YyeUunMFWWJ+VLcWTD0HH9Xs7IiJVDkDKbiTM/KsYTIUxRhX3mAHb0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734702608; c=relaxed/simple; bh=FADFf9WfzjcMmisKrO8yY+HCWLXOPKs8H/SA2SqLMyQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=j9PtxGsnhogqew7ItxXhq1NAux9il2rKULbcsfayde501gExz+5jMxwujMCM0po3cr3wQQwaurH0UVtqjCmCfTxo878FWfbRYvEzOU2avJQuuk2IUmQ3WvM/gDUn6ImKft3XMa1zxHtlIWtdsDL60RLXu2E9uSbBdHm+FfuFaCo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=OGKP9bCI; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="OGKP9bCI" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-436249df846so13305205e9.3 for ; Fri, 20 Dec 2024 05:50:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1734702605; x=1735307405; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=2h6pKpWNyOGCaw3yTYwiqZcJCt91K/pLDCAKswGUtgU=; b=OGKP9bCIfBgldblNmXgampEHN0kkPbvM7oZvzQpX83YC+QlbREAa6SnxIinB5kNtZZ 7UGRjlHpHJyvWj9eU0CrBAcib28Sq54cZKihAG4I8d83daDpYMvVvskdnnDEHtx1tZnG nSZrGvY1e1455hsUSwd1sJQlm1T9Yx1dg2Oan1YhLRhGbXh87ggynItHxSl6oVxeKec/ gb7TuwhAwL4IdiZk4lyVsvPfbVxlvNm3gvIltASm+XeF8iWP9FDYSTlPdmGqKhHwC7b2 owneHQT0jz0ei/Va65oVNp2MYm4KncyXDoDwVqMOPXMdLi106SHasDB0uOg8J8BZb0gv ksQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734702605; x=1735307405; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2h6pKpWNyOGCaw3yTYwiqZcJCt91K/pLDCAKswGUtgU=; b=DVETrc/nir0ZiaXL1OysgHCXcsuwX38AubcAgdawyISoZu3DMhrYRvCIfbpmbv4mVn 76Mc+svvE4fquAYVDVTsAnhgaHLrNbYXvDkEEqnirwGH7fsogxMrB6NIV53x8zAGP8Dz slYUnFyTI4TQYs73eXUMfy3QnB7xgEodxHPkkbRR82DTtpSqz9AvZZnfnAFX+xwj6TqM eqVMouYC+anwqqz3zX1/oDcZgZNSnK1Oj8HpTPNwuPWiEoKP6X0XoTL4TdwXVkVT5h8J lr9EYBoeQWsQgzYn2yCD9EjFgotLbXAedJK23lwaV88gcaBXnje+dmsena5uLZ0BfWOe xt7Q== X-Gm-Message-State: AOJu0YyraQw9tR4js5IZRfrFmYf9Nc6bZ6m+C2BJjKUhdwsDNlOR7RdR 9XspUYkJ3PMdro6d8jEu4NkG4c2xD84XJ3sE0In8+7MP9NS0VGG1uizrSqCH8pU= X-Gm-Gg: ASbGncvBKc/GMPu/SZqoJRIwNmnxofZgF3RTIk02KEmnLcixnVpG3LfJKpWdzYUddlv RDl+cf3sVfqq9aG7ooYfcFVKKMDda9HCGOrgkznwxexkMAKFvzC9VpLKrdy1Zt++ckhVRTkLDc8 9QQESInKerKdoMzHLctazlse73ifzFn/z297Ml6XvQDYyQfU0Qfa76o3d9xy8YZRKjR3z3hRLtK d79xdWzY1k/fBNHH15P0jecyql5Sz56ojIc0kaOqTMLWx2eKAV6XeHskYZVEPVwHbgobJtn4fpU VNJODWmyW8abVfrY1iPIDLSkoCajKnWxz684 X-Google-Smtp-Source: AGHT+IEzk3FDr4mxRi9pcg64L4EH36p/AQ921KSU720SqVRUCT5e6SMqARYYJAMs7JhmbOKgemYFdQ== X-Received: by 2002:a5d:648a:0:b0:386:36e7:f44f with SMTP id ffacd0b85a97d-38a221fb038mr2515751f8f.18.1734702604753; Fri, 20 Dec 2024 05:50:04 -0800 (PST) Received: from ta2.c.googlers.com (130.173.34.34.bc.googleusercontent.com. [34.34.173.130]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c832e74sm4044313f8f.30.2024.12.20.05.50.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2024 05:50:03 -0800 (PST) From: Tudor Ambarus Date: Fri, 20 Dec 2024 13:50:00 +0000 Subject: [PATCH v6 5/5] MAINTAINERS: add entry for Samsung Exynos mailbox driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241220-acpm-v4-upstream-mbox-v6-5-a6942806e52a@linaro.org> References: <20241220-acpm-v4-upstream-mbox-v6-0-a6942806e52a@linaro.org> In-Reply-To: <20241220-acpm-v4-upstream-mbox-v6-0-a6942806e52a@linaro.org> To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Alim Akhtar Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, daniel.lezcano@linaro.org, vincent.guittot@linaro.org, ulf.hansson@linaro.org, arnd@arndb.de, Tudor Ambarus , Krzysztof Kozlowski X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734702598; l=1338; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=FADFf9WfzjcMmisKrO8yY+HCWLXOPKs8H/SA2SqLMyQ=; b=R/NhwDpi95hfet9uVWKydOIL9KS/J5QAVtPKjGibId5k5o46YPFi74GbUfbFSSKG+goXQpBoD DO8znrl5OuxCXJUd1qUWRkIqdil5rImUGzsy1AcnYVz0s/L8+wAW5B7 X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add entry for the Samsung Exynos mailbox driver. Signed-off-by: Tudor Ambarus Reviewed-by: Krzysztof Kozlowski Reviewed-by: Peter Griffin --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index baf0eeb9a355..6bef5fc5e4ee 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3023,6 +3023,7 @@ F: drivers/*/*s3c24* F: drivers/*/*s3c64xx* F: drivers/*/*s5pv210* F: drivers/clocksource/samsung_pwm_timer.c +F: drivers/mailbox/exynos-mailbox.c F: drivers/memory/samsung/ F: drivers/pwm/pwm-samsung.c F: drivers/soc/samsung/ @@ -20717,6 +20718,15 @@ F: arch/arm64/boot/dts/exynos/exynos850* F: drivers/clk/samsung/clk-exynos850.c F: include/dt-bindings/clock/exynos850.h =20 +SAMSUNG EXYNOS MAILBOX DRIVER +M: Tudor Ambarus +L: linux-kernel@vger.kernel.org +L: linux-samsung-soc@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml +F: drivers/mailbox/exynos-mailbox.c +F: include/dt-bindings/mailbox/google,gs101.h + SAMSUNG EXYNOS PSEUDO RANDOM NUMBER GENERATOR (RNG) DRIVER M: Krzysztof Kozlowski L: linux-crypto@vger.kernel.org --=20 2.47.1.613.gc27f4b7a9f-goog