From nobody Fri Dec 19 04:55:16 2025 Received: from mail.steuer-voss.de (mail.steuer-voss.de [85.183.69.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF87D13AA38 for ; Thu, 19 Dec 2024 11:02:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=85.183.69.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734606125; cv=none; b=gEyxmJArAB35K5eWViVDvWpnzjn/x6SNPEwtJp4U564reYMnV1nTEiFIUHMVFN8EcLJAIBM2YWZldHi5suaJ5PlAvBCDbbah32+YdKkb1qbqtScypSjRFrrhQ2jHlV7Mtc8FmcStyrfPPafzimS0uC6+LOgvDnWuK+vKI2QHe5I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734606125; c=relaxed/simple; bh=ej8fYEOhdcIiz4DclqtuEmqgKs2V/zNXGVZQAsCMvy0=; h=From:Date:Subject:To:Cc:Message-Id; b=cIrs11Ukh0zvqrQrlYOnfYJitAASLPnFspKulL8GvHTfScjnngq82cY0v2UT4/+B4rshNbNBy3J/l2t8WMVFLryC0aNMZc3zTIDBKRGFsniD/jAmrW9noc0stNMrhgbxU+Oxk9ELvgWPfFEE3E9ILcuNZCBrZUwcc80m3ngQ2qc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=vosn.de; spf=pass smtp.mailfrom=vosn.de; arc=none smtp.client-ip=85.183.69.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=vosn.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=vosn.de X-Virus-Scanned: Debian amavisd-new at mail.steuer-voss.de Received: by mail.steuer-voss.de (Postfix, from userid 1000) id 4AE0D1201; Thu, 19 Dec 2024 11:54:16 +0100 (CET) From: Nikolaus Voss Date: Thur, 19 Dec 2024 11:54:01 +0100 Subject: [PATCH v4] drm: bridge: fsl-ldb: fixup mode on freq mismatch To: Alexander Stein , Liu Ying , Luca Ceresoli , Fabio Estevam , Marek Vasut , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , miquel.raynal@bootlin.com, nikolaus.voss@haag-streit.com Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Message-Id: <20241219105416.4AE0D1201@mail.steuer-voss.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" LDB clock has to be a fixed multiple of the pixel clock. Although LDB and pixel clock have a common source, this constraint cannot be satisfied for any pixel clock at a fixed source clock. Violating this constraint leads to flickering and distorted lines on the attached display. To overcome this, there are these approches: 1. Modify the base PLL clock statically by changing the device tree, implies calculating the PLL clock by hand, e.g. commit 4fbb73416b10 ("arm64: dts: imx8mp-phyboard-pollux: Set Video PLL1 frequency to 506.8 MHz") 2. Walk down the clock tree and modify the source clock. Proposed patch series by Miquel Raynal: [PATCH 0/5] clk: Fix simple video pipelines on i.MX8 3. This patch: check constraint violation in drm_bridge_funcs.atomic_check() and adapt the pixel clock in drm_display_mode.adjusted_mode accordingly. Fixes: 463db5c2ed4a ("drm: bridge: ldb: Implement simple Freescale i.MX8MP = LDB bridge") Cc: # 6.12.x, 6.6.x Signed-off-by: Nikolaus Voss Tested-by: Martin Kepplinger --- v2: - use .atomic_check() instead of .mode_fixup() (Dmitry Baryshkov) - add Fixes tag (Liu Ying) - use fsl_ldb_link_frequency() and drop const qualifier for struct fsl_ldb* (Liu Ying) v3: - fix kernel test robot warning: fsl-ldb.c:125:30: warning: omitting the parameter name in a function definition is a C23 extension [-Wc23-extensions] - fix/rephrase commit text due to discussion with Marek Vasut, Liu Ying and Miquel Raynal - only calculate and set pixel clock if ldb is not already configured to the matching frequency v4: - handle mode changes correctly: recalculate pixel clock when mode changes occur - tested on 6.12.x and 6.6.x stable branches drivers/gpu/drm/bridge/fsl-ldb.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-= ldb.c index 0e4bac7dd04ff..97ca522556718 100644 --- a/drivers/gpu/drm/bridge/fsl-ldb.c +++ b/drivers/gpu/drm/bridge/fsl-ldb.c @@ -121,6 +121,36 @@ static int fsl_ldb_attach(struct drm_bridge *bridge, bridge, flags); } =20 +static int fsl_ldb_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *connector_state) +{ + struct fsl_ldb *fsl_ldb =3D to_fsl_ldb(bridge); + const struct drm_display_mode *mode =3D &crtc_state->mode; + unsigned long requested_freq =3D + fsl_ldb_link_frequency(fsl_ldb, mode->clock); + unsigned long freq =3D clk_round_rate(fsl_ldb->clk, requested_freq); + + if (crtc_state->mode_changed && (freq !=3D requested_freq)) { + /* + * this will lead to flicker and incomplete lines on + * the attached display, adjust the CRTC clock + * accordingly. + */ + struct drm_display_mode *adjusted_mode =3D &crtc_state->adjusted_mode; + int pclk =3D freq / fsl_ldb_link_frequency(fsl_ldb, 1); + + dev_warn(fsl_ldb->dev, "Adjusted pixel clk to match LDB clk (%d kHz -> %= d kHz)!\n", + adjusted_mode->clock, pclk); + + adjusted_mode->clock =3D pclk; + adjusted_mode->crtc_clock =3D pclk; + } + + return 0; +} + static void fsl_ldb_atomic_enable(struct drm_bridge *bridge, struct drm_bridge_state *old_bridge_state) { @@ -280,6 +310,7 @@ fsl_ldb_mode_valid(struct drm_bridge *bridge, =20 static const struct drm_bridge_funcs funcs =3D { .attach =3D fsl_ldb_attach, + .atomic_check =3D fsl_ldb_atomic_check, .atomic_enable =3D fsl_ldb_atomic_enable, .atomic_disable =3D fsl_ldb_atomic_disable, .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, --=20 2.43.0