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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-6-92c7c0a228e3@linaro.org> References: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> In-Reply-To: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734594568; l=27903; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=QU4PG4xOK4PMc09kz7jvmloOreDs7Th8a7KQFCA6X24=; b=7b9QFiaZvDoV9hE7CUCBE+SyP0/q+35dY7qlBK/W0ImwsyXj3SNFSSskErgIpCi1VNWtsv9bC Syd3X4j/glQD1IXxnH1av8tVT8UoR8c+bdMut5vTE3Y2Iug+0l1iceq X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Up to now the driver has been using encoder to allocate hardware resources. Switch it to use CRTC id so that mixer number can be known in dpu_plane_virtual_assign_resources() via CRTC id for sspp alloation. Because the mixer allocation is done in drm_atomic_helper_check_modeset() as part of CRTC operation. While the sspp assignment is in drm_atomic_helper_check_planes() call tree. So CRTC is more central than encoder. Siwtching the id achieves above goal. Co-developed-by: Dmitry Baryshkov Signed-off-by: Dmitry Baryshkov Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 20 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 12 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 198 ++++++++++++++----------= ---- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 32 ++++- 4 files changed, 139 insertions(+), 123 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index cc23f364dd080..fd32ef468d5f9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -716,11 +716,11 @@ static void dpu_encoder_assign_crtc_resources(struct = dpu_kms *dpu_kms, memset(cstate->mixers, 0, sizeof(cstate->mixers)); =20 num_ctl =3D dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); + crtc_state->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); num_lm =3D dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); + crtc_state->crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); num_dspp =3D dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp, + crtc_state->crtc, DPU_HW_BLK_DSPP, hw_dspp, ARRAY_SIZE(hw_dspp)); =20 for (i =3D 0; i < num_lm; i++) { @@ -797,11 +797,11 @@ static int dpu_encoder_virt_atomic_check( * Dont allocate when active is false. */ if (drm_atomic_crtc_needs_modeset(crtc_state)) { - dpu_rm_release(global_state, drm_enc); + dpu_rm_release(global_state, crtc_state->crtc); =20 if (!crtc_state->active_changed || crtc_state->enable) ret =3D dpu_rm_reserve(&dpu_kms->rm, global_state, - drm_enc, crtc_state, topology); + crtc_state->crtc, topology); if (!ret) dpu_encoder_assign_crtc_resources(dpu_kms, drm_enc, global_state, crtc_state); @@ -1245,17 +1245,17 @@ static void dpu_encoder_virt_atomic_mode_set(struct= drm_encoder *drm_enc, =20 /* Query resource that have been reserved in atomic check step. */ num_pp =3D dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp, + drm_enc->crtc, DPU_HW_BLK_PINGPONG, hw_pp, ARRAY_SIZE(hw_pp)); num_ctl =3D dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); + drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); =20 for (i =3D 0; i < MAX_CHANNELS_PER_ENC; i++) dpu_enc->hw_pp[i] =3D i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) : NULL; =20 num_dsc =3D dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_DSC, + drm_enc->crtc, DPU_HW_BLK_DSC, hw_dsc, ARRAY_SIZE(hw_dsc)); for (i =3D 0; i < num_dsc; i++) { dpu_enc->hw_dsc[i] =3D to_dpu_hw_dsc(hw_dsc[i]); @@ -1270,7 +1270,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct d= rm_encoder *drm_enc, struct dpu_hw_blk *hw_cdm =3D NULL; =20 dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_CDM, + drm_enc->crtc, DPU_HW_BLK_CDM, &hw_cdm, 1); dpu_enc->cur_master->hw_cdm =3D hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL; } @@ -2197,7 +2197,7 @@ static void dpu_encoder_helper_reset_mixers(struct dp= u_encoder_phys *phys_enc) global_state =3D dpu_kms_get_existing_global_state(phys_enc->dpu_kms); =20 num_lm =3D dpu_rm_get_assigned_resources(&phys_enc->dpu_kms->rm, global_s= tate, - phys_enc->parent->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); + phys_enc->parent->crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); =20 for (i =3D 0; i < num_lm; i++) { hw_mixer[i] =3D to_dpu_hw_mixer(hw_lm[i]); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.h index 547cdb2c0c788..54ef6cfa2485a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -124,12 +124,12 @@ struct dpu_global_state { =20 struct dpu_rm *rm; =20 - uint32_t pingpong_to_enc_id[PINGPONG_MAX - PINGPONG_0]; - uint32_t mixer_to_enc_id[LM_MAX - LM_0]; - uint32_t ctl_to_enc_id[CTL_MAX - CTL_0]; - uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0]; - uint32_t dsc_to_enc_id[DSC_MAX - DSC_0]; - uint32_t cdm_to_enc_id; + uint32_t pingpong_to_crtc_id[PINGPONG_MAX - PINGPONG_0]; + uint32_t mixer_to_crtc_id[LM_MAX - LM_0]; + uint32_t ctl_to_crtc_id[CTL_MAX - CTL_0]; + uint32_t dspp_to_crtc_id[DSPP_MAX - DSPP_0]; + uint32_t dsc_to_crtc_id[DSC_MAX - DSC_0]; + uint32_t cdm_to_crtc_id; =20 uint32_t sspp_to_crtc_id[SSPP_MAX - SSPP_NONE]; }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index a8b01b78c02c7..a6a410e301abd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -21,9 +21,9 @@ =20 =20 static inline bool reserved_by_other(uint32_t *res_map, int idx, - uint32_t enc_id) + uint32_t crtc_id) { - return res_map[idx] && res_map[idx] !=3D enc_id; + return res_map[idx] && res_map[idx] !=3D crtc_id; } =20 /** @@ -235,7 +235,7 @@ static int _dpu_rm_get_lm_peer(struct dpu_rm *rm, int p= rimary_idx) * pingpong * @rm: dpu resource manager handle * @global_state: resources shared across multiple kms objects - * @enc_id: encoder id requesting for allocation + * @crtc_id: crtc id requesting for allocation * @lm_idx: index of proposed layer mixer in rm->mixer_blks[], function ch= ecks * if lm, and all other hardwired blocks connected to the lm (pp) is * available and appropriate @@ -249,14 +249,14 @@ static int _dpu_rm_get_lm_peer(struct dpu_rm *rm, int= primary_idx) */ static bool _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, int lm_idx, int *pp_idx, int *dspp_idx, + uint32_t crtc_id, int lm_idx, int *pp_idx, int *dspp_idx, struct dpu_rm_requirements *reqs) { const struct dpu_lm_cfg *lm_cfg; int idx; =20 /* Already reserved? */ - if (reserved_by_other(global_state->mixer_to_enc_id, lm_idx, enc_id)) { + if (reserved_by_other(global_state->mixer_to_crtc_id, lm_idx, crtc_id)) { DPU_DEBUG("lm %d already reserved\n", lm_idx + LM_0); return false; } @@ -268,7 +268,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(str= uct dpu_rm *rm, return false; } =20 - if (reserved_by_other(global_state->pingpong_to_enc_id, idx, enc_id)) { + if (reserved_by_other(global_state->pingpong_to_crtc_id, idx, crtc_id)) { DPU_DEBUG("lm %d pp %d already reserved\n", lm_cfg->id, lm_cfg->pingpong); return false; @@ -284,7 +284,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(str= uct dpu_rm *rm, return false; } =20 - if (reserved_by_other(global_state->dspp_to_enc_id, idx, enc_id)) { + if (reserved_by_other(global_state->dspp_to_crtc_id, idx, crtc_id)) { DPU_DEBUG("lm %d dspp %d already reserved\n", lm_cfg->id, lm_cfg->dspp); return false; @@ -296,7 +296,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(str= uct dpu_rm *rm, =20 static int _dpu_rm_reserve_lms(struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, + uint32_t crtc_id, struct dpu_rm_requirements *reqs) =20 { @@ -324,7 +324,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, lm_idx[lm_count] =3D i; =20 if (!_dpu_rm_check_lm_and_get_connected_blks(rm, global_state, - enc_id, i, &pp_idx[lm_count], + crtc_id, i, &pp_idx[lm_count], &dspp_idx[lm_count], reqs)) { continue; } @@ -343,7 +343,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, continue; =20 if (!_dpu_rm_check_lm_and_get_connected_blks(rm, - global_state, enc_id, j, + global_state, crtc_id, j, &pp_idx[lm_count], &dspp_idx[lm_count], reqs)) { continue; @@ -360,13 +360,16 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, } =20 for (i =3D 0; i < lm_count; i++) { - global_state->mixer_to_enc_id[lm_idx[i]] =3D enc_id; - global_state->pingpong_to_enc_id[pp_idx[i]] =3D enc_id; - global_state->dspp_to_enc_id[dspp_idx[i]] =3D - reqs->topology.num_dspp ? enc_id : 0; + global_state->mixer_to_crtc_id[lm_idx[i]] =3D crtc_id; + global_state->pingpong_to_crtc_id[pp_idx[i]] =3D crtc_id; + global_state->dspp_to_crtc_id[dspp_idx[i]] =3D + reqs->topology.num_dspp ? crtc_id : 0; =20 - trace_dpu_rm_reserve_lms(lm_idx[i] + LM_0, enc_id, + trace_dpu_rm_reserve_lms(lm_idx[i] + LM_0, crtc_id, pp_idx[i] + PINGPONG_0); + + DPU_DEBUG("reserve lm[%d]:%d, pp_idx[%d]:%d, dspp[%d]:%d for crtc_id %d\= n", + i, lm_idx[i], i, pp_idx[i], i, dspp_idx[i], crtc_id); } =20 return 0; @@ -375,7 +378,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, static int _dpu_rm_reserve_ctls( struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, + uint32_t crtc_id, const struct msm_display_topology *top) { int ctl_idx[MAX_BLOCKS]; @@ -399,7 +402,7 @@ static int _dpu_rm_reserve_ctls( =20 if (!rm->ctl_blks[j]) continue; - if (reserved_by_other(global_state->ctl_to_enc_id, j, enc_id)) + if (reserved_by_other(global_state->ctl_to_crtc_id, j, crtc_id)) continue; =20 ctl =3D to_dpu_hw_ctl(rm->ctl_blks[j]); @@ -423,8 +426,8 @@ static int _dpu_rm_reserve_ctls( return -ENAVAIL; =20 for (i =3D 0; i < ARRAY_SIZE(ctl_idx) && i < num_ctls; i++) { - global_state->ctl_to_enc_id[ctl_idx[i]] =3D enc_id; - trace_dpu_rm_reserve_ctls(i + CTL_0, enc_id); + global_state->ctl_to_crtc_id[ctl_idx[i]] =3D crtc_id; + trace_dpu_rm_reserve_ctls(i + CTL_0, crtc_id); } =20 return 0; @@ -432,12 +435,12 @@ static int _dpu_rm_reserve_ctls( =20 static int _dpu_rm_pingpong_next_index(struct dpu_global_state *global_sta= te, int start, - uint32_t enc_id) + uint32_t crtc_id) { int i; =20 for (i =3D start; i < (PINGPONG_MAX - PINGPONG_0); i++) { - if (global_state->pingpong_to_enc_id[i] =3D=3D enc_id) + if (global_state->pingpong_to_crtc_id[i] =3D=3D crtc_id) return i; } =20 @@ -458,7 +461,7 @@ static int _dpu_rm_pingpong_dsc_check(int dsc_idx, int = pp_idx) =20 static int _dpu_rm_dsc_alloc(struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, + uint32_t crtc_id, const struct msm_display_topology *top) { int num_dsc =3D 0; @@ -471,10 +474,10 @@ static int _dpu_rm_dsc_alloc(struct dpu_rm *rm, if (!rm->dsc_blks[dsc_idx]) continue; =20 - if (reserved_by_other(global_state->dsc_to_enc_id, dsc_idx, enc_id)) + if (reserved_by_other(global_state->dsc_to_crtc_id, dsc_idx, crtc_id)) continue; =20 - pp_idx =3D _dpu_rm_pingpong_next_index(global_state, pp_idx, enc_id); + pp_idx =3D _dpu_rm_pingpong_next_index(global_state, pp_idx, crtc_id); if (pp_idx < 0) return -ENAVAIL; =20 @@ -482,7 +485,7 @@ static int _dpu_rm_dsc_alloc(struct dpu_rm *rm, if (ret) return -ENAVAIL; =20 - global_state->dsc_to_enc_id[dsc_idx] =3D enc_id; + global_state->dsc_to_crtc_id[dsc_idx] =3D crtc_id; num_dsc++; pp_idx++; } @@ -498,7 +501,7 @@ static int _dpu_rm_dsc_alloc(struct dpu_rm *rm, =20 static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, + uint32_t crtc_id, const struct msm_display_topology *top) { int num_dsc =3D 0; @@ -513,11 +516,11 @@ static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, continue; =20 /* consective dsc index to be paired */ - if (reserved_by_other(global_state->dsc_to_enc_id, dsc_idx, enc_id) || - reserved_by_other(global_state->dsc_to_enc_id, dsc_idx + 1, enc_id)) + if (reserved_by_other(global_state->dsc_to_crtc_id, dsc_idx, crtc_id) || + reserved_by_other(global_state->dsc_to_crtc_id, dsc_idx + 1, crtc_id= )) continue; =20 - pp_idx =3D _dpu_rm_pingpong_next_index(global_state, pp_idx, enc_id); + pp_idx =3D _dpu_rm_pingpong_next_index(global_state, pp_idx, crtc_id); if (pp_idx < 0) return -ENAVAIL; =20 @@ -527,7 +530,7 @@ static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, continue; } =20 - pp_idx =3D _dpu_rm_pingpong_next_index(global_state, pp_idx + 1, enc_id); + pp_idx =3D _dpu_rm_pingpong_next_index(global_state, pp_idx + 1, crtc_id= ); if (pp_idx < 0) return -ENAVAIL; =20 @@ -537,8 +540,8 @@ static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, continue; } =20 - global_state->dsc_to_enc_id[dsc_idx] =3D enc_id; - global_state->dsc_to_enc_id[dsc_idx + 1] =3D enc_id; + global_state->dsc_to_crtc_id[dsc_idx] =3D crtc_id; + global_state->dsc_to_crtc_id[dsc_idx + 1] =3D crtc_id; num_dsc +=3D 2; pp_idx++; /* start for next pair */ } @@ -554,11 +557,9 @@ static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, =20 static int _dpu_rm_reserve_dsc(struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *enc, + uint32_t crtc_id, const struct msm_display_topology *top) { - uint32_t enc_id =3D enc->base.id; - if (!top->num_dsc || !top->num_intf) return 0; =20 @@ -568,22 +569,22 @@ static int _dpu_rm_reserve_dsc(struct dpu_rm *rm, * 2) DSC pair starts from even index, such as index(0,1), (2,3), etc * 3) even PINGPONG connects to even DSC * 4) odd PINGPONG connects to odd DSC - * 5) pair: encoder +--> pp_idx_0 --> dsc_idx_0 + * 5) pair: crtc +--> pp_idx_0 --> dsc_idx_0 * +--> pp_idx_1 --> dsc_idx_1 */ =20 /* num_dsc should be either 1, 2 or 4 */ if (top->num_dsc > top->num_intf) /* merge mode */ - return _dpu_rm_dsc_alloc_pair(rm, global_state, enc_id, top); + return _dpu_rm_dsc_alloc_pair(rm, global_state, crtc_id, top); else - return _dpu_rm_dsc_alloc(rm, global_state, enc_id, top); + return _dpu_rm_dsc_alloc(rm, global_state, crtc_id, top); =20 return 0; } =20 static int _dpu_rm_reserve_cdm(struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *enc) + uint32_t crtc_id) { /* try allocating only one CDM block */ if (!rm->cdm_blk) { @@ -591,12 +592,12 @@ static int _dpu_rm_reserve_cdm(struct dpu_rm *rm, return -EIO; } =20 - if (global_state->cdm_to_enc_id) { + if (global_state->cdm_to_crtc_id) { DPU_ERROR("CDM_0 is already allocated\n"); return -EIO; } =20 - global_state->cdm_to_enc_id =3D enc->base.id; + global_state->cdm_to_crtc_id =3D crtc_id; =20 return 0; } @@ -604,30 +605,30 @@ static int _dpu_rm_reserve_cdm(struct dpu_rm *rm, static int _dpu_rm_make_reservation( struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *enc, + uint32_t crtc_id, struct dpu_rm_requirements *reqs) { int ret; =20 - ret =3D _dpu_rm_reserve_lms(rm, global_state, enc->base.id, reqs); + ret =3D _dpu_rm_reserve_lms(rm, global_state, crtc_id, reqs); if (ret) { DPU_ERROR("unable to find appropriate mixers\n"); return ret; } =20 - ret =3D _dpu_rm_reserve_ctls(rm, global_state, enc->base.id, + ret =3D _dpu_rm_reserve_ctls(rm, global_state, crtc_id, &reqs->topology); if (ret) { DPU_ERROR("unable to find appropriate CTL\n"); return ret; } =20 - ret =3D _dpu_rm_reserve_dsc(rm, global_state, enc, &reqs->topology); + ret =3D _dpu_rm_reserve_dsc(rm, global_state, crtc_id, &reqs->topology); if (ret) return ret; =20 if (reqs->topology.needs_cdm) { - ret =3D _dpu_rm_reserve_cdm(rm, global_state, enc); + ret =3D _dpu_rm_reserve_cdm(rm, global_state, crtc_id); if (ret) { DPU_ERROR("unable to find CDM blk\n"); return ret; @@ -638,7 +639,7 @@ static int _dpu_rm_make_reservation( } =20 static int _dpu_rm_populate_requirements( - struct drm_encoder *enc, + struct drm_crtc *crtc, struct dpu_rm_requirements *reqs, struct msm_display_topology req_topology) { @@ -652,12 +653,12 @@ static int _dpu_rm_populate_requirements( } =20 static void _dpu_rm_clear_mapping(uint32_t *res_mapping, int cnt, - uint32_t enc_id) + uint32_t crtc_id) { int i; =20 for (i =3D 0; i < cnt; i++) { - if (res_mapping[i] =3D=3D enc_id) + if (res_mapping[i] =3D=3D crtc_id) res_mapping[i] =3D 0; } } @@ -666,23 +667,24 @@ static void _dpu_rm_clear_mapping(uint32_t *res_mappi= ng, int cnt, * dpu_rm_release - Given the encoder for the display chain, release any * HW blocks previously reserved for that use case. * @global_state: resources shared across multiple kms objects - * @enc: DRM Encoder handle + * @crtc: DRM CRTC handle * @return: 0 on Success otherwise -ERROR */ void dpu_rm_release(struct dpu_global_state *global_state, - struct drm_encoder *enc) + struct drm_crtc *crtc) { - _dpu_rm_clear_mapping(global_state->pingpong_to_enc_id, - ARRAY_SIZE(global_state->pingpong_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(global_state->mixer_to_enc_id, - ARRAY_SIZE(global_state->mixer_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(global_state->ctl_to_enc_id, - ARRAY_SIZE(global_state->ctl_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(global_state->dsc_to_enc_id, - ARRAY_SIZE(global_state->dsc_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(global_state->dspp_to_enc_id, - ARRAY_SIZE(global_state->dspp_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(&global_state->cdm_to_enc_id, 1, enc->base.id); + uint32_t crtc_id =3D crtc->base.id; + + _dpu_rm_clear_mapping(global_state->pingpong_to_crtc_id, + ARRAY_SIZE(global_state->pingpong_to_crtc_id), crtc_id); + _dpu_rm_clear_mapping(global_state->mixer_to_crtc_id, + ARRAY_SIZE(global_state->mixer_to_crtc_id), crtc_id); + _dpu_rm_clear_mapping(global_state->ctl_to_crtc_id, + ARRAY_SIZE(global_state->ctl_to_crtc_id), crtc_id); + _dpu_rm_clear_mapping(global_state->dsc_to_crtc_id, + ARRAY_SIZE(global_state->dsc_to_crtc_id), crtc_id); + _dpu_rm_clear_mapping(global_state->dspp_to_crtc_id, + ARRAY_SIZE(global_state->dspp_to_crtc_id), crtc_id); } =20 /** @@ -694,45 +696,36 @@ void dpu_rm_release(struct dpu_global_state *global_s= tate, * HW Reservations should be released via dpu_rm_release_hw. * @rm: DPU Resource Manager handle * @global_state: resources shared across multiple kms objects - * @enc: DRM Encoder handle - * @crtc_state: Proposed Atomic DRM CRTC State handle + * @crtc: DRM CRTC handle * @topology: Pointer to topology info for the display * @return: 0 on Success otherwise -ERROR */ int dpu_rm_reserve( struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *enc, - struct drm_crtc_state *crtc_state, + struct drm_crtc *crtc, struct msm_display_topology topology) { struct dpu_rm_requirements reqs; int ret; =20 - /* Check if this is just a page-flip */ - if (!drm_atomic_crtc_needs_modeset(crtc_state)) - return 0; - if (IS_ERR(global_state)) { DPU_ERROR("failed to global state\n"); return PTR_ERR(global_state); } =20 - DRM_DEBUG_KMS("reserving hw for enc %d crtc %d\n", - enc->base.id, crtc_state->crtc->base.id); + DRM_DEBUG_KMS("reserving hw for crtc %d\n", crtc->base.id); =20 - ret =3D _dpu_rm_populate_requirements(enc, &reqs, topology); + ret =3D _dpu_rm_populate_requirements(crtc, &reqs, topology); if (ret) { DPU_ERROR("failed to populate hw requirements\n"); return ret; } =20 - ret =3D _dpu_rm_make_reservation(rm, global_state, enc, &reqs); + ret =3D _dpu_rm_make_reservation(rm, global_state, crtc->base.id, &reqs); if (ret) DPU_ERROR("failed to reserve hw resources: %d\n", ret); =20 - - return ret; } =20 @@ -806,7 +799,7 @@ struct dpu_hw_sspp *dpu_rm_reserve_sspp(struct dpu_rm *= rm, /** * dpu_rm_release_all_sspp - Given the CRTC, release all SSPP * blocks previously reserved for that use case. - * @rm: DPU Resource Manager handle + * @global_state: resources shared across multiple kms objects * @crtc: DRM CRTC handle */ void dpu_rm_release_all_sspp(struct dpu_global_state *global_state, @@ -838,48 +831,49 @@ static char *dpu_hw_blk_type_name[] =3D { * assigned to this encoder * @rm: DPU Resource Manager handle * @global_state: resources shared across multiple kms objects - * @enc_id: encoder id requesting for allocation + * @crtc: DRM CRTC handle * @type: resource type to return data for * @blks: pointer to the array to be filled by HW resources * @blks_size: size of the @blks array */ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, - struct dpu_global_state *global_state, uint32_t enc_id, + struct dpu_global_state *global_state, struct drm_crtc *crtc, enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size) { + uint32_t crtc_id =3D crtc->base.id; struct dpu_hw_blk **hw_blks; - uint32_t *hw_to_enc_id; + uint32_t *hw_to_crtc_id; int i, num_blks, max_blks; =20 switch (type) { case DPU_HW_BLK_PINGPONG: hw_blks =3D rm->pingpong_blks; - hw_to_enc_id =3D global_state->pingpong_to_enc_id; + hw_to_crtc_id =3D global_state->pingpong_to_crtc_id; max_blks =3D ARRAY_SIZE(rm->pingpong_blks); break; case DPU_HW_BLK_LM: hw_blks =3D rm->mixer_blks; - hw_to_enc_id =3D global_state->mixer_to_enc_id; + hw_to_crtc_id =3D global_state->mixer_to_crtc_id; max_blks =3D ARRAY_SIZE(rm->mixer_blks); break; case DPU_HW_BLK_CTL: hw_blks =3D rm->ctl_blks; - hw_to_enc_id =3D global_state->ctl_to_enc_id; + hw_to_crtc_id =3D global_state->ctl_to_crtc_id; max_blks =3D ARRAY_SIZE(rm->ctl_blks); break; case DPU_HW_BLK_DSPP: hw_blks =3D rm->dspp_blks; - hw_to_enc_id =3D global_state->dspp_to_enc_id; + hw_to_crtc_id =3D global_state->dspp_to_crtc_id; max_blks =3D ARRAY_SIZE(rm->dspp_blks); break; case DPU_HW_BLK_DSC: hw_blks =3D rm->dsc_blks; - hw_to_enc_id =3D global_state->dsc_to_enc_id; + hw_to_crtc_id =3D global_state->dsc_to_crtc_id; max_blks =3D ARRAY_SIZE(rm->dsc_blks); break; case DPU_HW_BLK_CDM: hw_blks =3D &rm->cdm_blk; - hw_to_enc_id =3D &global_state->cdm_to_enc_id; + hw_to_crtc_id =3D &global_state->cdm_to_crtc_id; max_blks =3D 1; break; default: @@ -889,17 +883,17 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, =20 num_blks =3D 0; for (i =3D 0; i < max_blks; i++) { - if (hw_to_enc_id[i] !=3D enc_id) + if (hw_to_crtc_id[i] !=3D crtc_id) continue; =20 if (num_blks =3D=3D blks_size) { - DPU_ERROR("More than %d %s assigned to enc %d\n", - blks_size, dpu_hw_blk_type_name[type], enc_id); + DPU_ERROR("More than %d resources assigned to crtc %d\n", + blks_size, crtc_id); break; } if (!hw_blks[i]) { - DPU_ERROR("%s unavailable to assign to enc %d\n", - dpu_hw_blk_type_name[type], enc_id); + DPU_ERROR("%s unavailable to assign to crtc %d\n", + dpu_hw_blk_type_name[type], crtc_id); break; } blks[num_blks++] =3D hw_blks[i]; @@ -934,38 +928,38 @@ void dpu_rm_print_state(struct drm_printer *p, =20 drm_puts(p, "resource mapping:\n"); drm_puts(p, "\tpingpong=3D"); - for (i =3D 0; i < ARRAY_SIZE(global_state->pingpong_to_enc_id); i++) + for (i =3D 0; i < ARRAY_SIZE(global_state->pingpong_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->pingpong_blks[i], - global_state->pingpong_to_enc_id[i]); + global_state->pingpong_to_crtc_id[i]); drm_puts(p, "\n"); =20 drm_puts(p, "\tmixer=3D"); - for (i =3D 0; i < ARRAY_SIZE(global_state->mixer_to_enc_id); i++) + for (i =3D 0; i < ARRAY_SIZE(global_state->mixer_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->mixer_blks[i], - global_state->mixer_to_enc_id[i]); + global_state->mixer_to_crtc_id[i]); drm_puts(p, "\n"); =20 drm_puts(p, "\tctl=3D"); - for (i =3D 0; i < ARRAY_SIZE(global_state->ctl_to_enc_id); i++) + for (i =3D 0; i < ARRAY_SIZE(global_state->ctl_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->ctl_blks[i], - global_state->ctl_to_enc_id[i]); + global_state->ctl_to_crtc_id[i]); drm_puts(p, "\n"); =20 drm_puts(p, "\tdspp=3D"); - for (i =3D 0; i < ARRAY_SIZE(global_state->dspp_to_enc_id); i++) + for (i =3D 0; i < ARRAY_SIZE(global_state->dspp_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->dspp_blks[i], - global_state->dspp_to_enc_id[i]); + global_state->dspp_to_crtc_id[i]); drm_puts(p, "\n"); =20 drm_puts(p, "\tdsc=3D"); - for (i =3D 0; i < ARRAY_SIZE(global_state->dsc_to_enc_id); i++) + for (i =3D 0; i < ARRAY_SIZE(global_state->dsc_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->dsc_blks[i], - global_state->dsc_to_enc_id[i]); + global_state->dsc_to_crtc_id[i]); drm_puts(p, "\n"); =20 drm_puts(p, "\tcdm=3D"); dpu_rm_print_state_helper(p, rm->cdm_blk, - global_state->cdm_to_enc_id); + global_state->cdm_to_crtc_id); drm_puts(p, "\n"); =20 drm_puts(p, "\tsspp=3D"); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.h index 227a486b2b83a..ba2d9bc1cc687 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -66,14 +66,33 @@ int dpu_rm_init(struct drm_device *dev, const struct msm_mdss_data *mdss_data, void __iomem *mmio); =20 -int dpu_rm_reserve(struct dpu_rm *rm, +/** + * dpu_rm_reserve - Given a CRTC->Encoder->Connector display chain, analyze + * the use connections and user requirements, specified through related + * topology control properties, and reserve hardware blocks to that + * display chain. + * HW blocks can then be accessed through dpu_rm_get_* functions. + * HW Reservations should be released via dpu_rm_release_hw. + * @rm: DPU Resource Manager handle + * @crtc: DRM CRTC handle + * @topology: Pointer to topology info for the display + * @Return: 0 on Success otherwise -ERROR + */ +int dpu_rm_reserve( + struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *drm_enc, - struct drm_crtc_state *crtc_state, + struct drm_crtc *crtc, struct msm_display_topology topology); =20 +/** + * dpu_rm_release - Given the crtc for the display chain, release any + * HW blocks previously reserved for that use case. + * @rm: DPU Resource Manager handle + * @crtc: DRM CRTC handle + * @Return: 0 on Success otherwise -ERROR + */ void dpu_rm_release(struct dpu_global_state *global_state, - struct drm_encoder *enc); + struct drm_crtc *crtc); =20 struct dpu_hw_sspp *dpu_rm_reserve_sspp(struct dpu_rm *rm, struct dpu_global_state *global_state, @@ -83,8 +102,11 @@ struct dpu_hw_sspp *dpu_rm_reserve_sspp(struct dpu_rm *= rm, void dpu_rm_release_all_sspp(struct dpu_global_state *global_state, struct drm_crtc *crtc); =20 +/** + * Get hw resources of the given type that are assigned to this crtc. + */ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, - struct dpu_global_state *global_state, uint32_t enc_id, + struct dpu_global_state *global_state, struct drm_crtc *crtc, enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size); =20 void dpu_rm_print_state(struct drm_printer *p, --=20 2.34.1