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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-1-92c7c0a228e3@linaro.org> References: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> In-Reply-To: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734594567; l=1800; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=H71UugjG5IQJFjXijgWx29ezewCBoV9AAKOOrWRKHwk=; b=dUzlSdGY5e36I0gVxFwpQEvjNoLa0A1wdKlZECUaxHkjySXlll3b9Uyws+NzCj8x2f+Y9BgKm sggNoaJFPFdAts/tP1G4bwB5pARZ8tdxN6l7vnKa8WC8Acwxaq2KQoZ X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= If DSC is enabled, the only case is with 2 DSC engines so far. More usage case will be added, such as 4 DSC in 4:4:2 topoplogy. So get real number of DSCs to decide whether DSC merge is needed. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index ddc60e658d63f..650df585138cd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -164,6 +164,7 @@ enum dpu_enc_rc_states { * clks and resources after IDLE_TIMEOUT time. * @topology: topology of the display * @idle_timeout: idle timeout duration in milliseconds + * @num_dscs: Number of DSCs in use * @wide_bus_en: wide bus is enabled on this interface * @dsc: drm_dsc_config pointer, for DSC-enabled encoders */ @@ -204,6 +205,7 @@ struct dpu_encoder_virt { struct msm_display_topology topology; =20 u32 idle_timeout; + u32 num_dscs; =20 bool wide_bus_en; =20 @@ -622,9 +624,8 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_= enc) if (dpu_enc->phys_encs[i]) intf_count++; =20 - /* See dpu_encoder_get_topology, we only support 2:2:1 topology */ if (dpu_enc->dsc) - num_dsc =3D 2; + num_dsc =3D dpu_enc->num_dscs; =20 return (num_dsc > 0) && (num_dsc > intf_count); } @@ -1261,6 +1262,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct d= rm_encoder *drm_enc, dsc_mask |=3D BIT(dpu_enc->hw_dsc[i]->idx - DSC_0); } =20 + dpu_enc->num_dscs =3D num_dsc; dpu_enc->dsc_mask =3D dsc_mask; =20 if ((dpu_enc->disp_info.intf_type =3D=3D INTF_WB && conn_state->writeback= _job) || --=20 2.34.1