From nobody Thu Dec 18 20:22:07 2025 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9460721767F for ; Thu, 19 Dec 2024 07:49:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594583; cv=none; b=uyeTwMqhRYxI8v073rXboLmARIJbcMriaVN6jLNZ1F9LpGKUhWj4NPBg1m0tuO657HdsQCpwJzgEqCjxe3a2HeCeMom43bGrrfOY0gOa/6LDfVtRn3CNPXbTiDL2y0xCNmCizjkAC6XbfZ4IDpHGSoa8aoi1q7d4zwo26EyFESY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594583; c=relaxed/simple; bh=H71UugjG5IQJFjXijgWx29ezewCBoV9AAKOOrWRKHwk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RKlIkEdj9Xs+XuOfE1lvzOsvKk0f1FNi9W56r6sWyJ3W+3X6waiRirjG1bB7QG/IEOh7wQD6IMrNime+D1rDSfNRj5Sa6PVKx74iaIg/n73el17XTzSMHMBejNduZxxWWozL9/h8fWSz4y+ruECHjupLs9NjVbn94g9gcYmmsyU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=QOoDAwa9; arc=none smtp.client-ip=209.85.214.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="QOoDAwa9" Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-21670dce0a7so5440425ad.1 for ; Wed, 18 Dec 2024 23:49:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1734594580; x=1735199380; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=4KnECnBShXY3h8fLirhSC2vujN3PJRN+mScj8HCQ30M=; b=QOoDAwa9OoC64KDYxt5fBism4rBuNNGg+MO3vRnBZ8+rDwvvgj1QGqoM48MLAEFbHn k5CRkm8mzRddXYSt4NZFqlGPxFu6fNP5loCqpXF+rbOTXb8SJzkQ4mtVu8D1ElInp82v FMoLP9XckmAZAlYw173D1vm+8lG9FxPc8ofmRbbT1RPuf2XVXbOSJTZHndual1QP5yKd qB8/AhOazsMXiXAtr1qfgFchhgFFH4MfLwllLZ7+GrqlmUgh093m5/6nDfaM8+7ZqzlJ p4tGLL8XxtXYgXowdZ1PnzOniSsGgvP7BhIDG/zHChSWSbIWJttXnDMovFPHw2CP5lFC 0Ujw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734594580; x=1735199380; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4KnECnBShXY3h8fLirhSC2vujN3PJRN+mScj8HCQ30M=; b=V8MQcvKnyF2lpkQJo1+isk66grqgH2j/bN6WjIqvjOqboSJxgeTlg9qXjf+SWIvwXu R8puoIuG6X+eCxIFQAfE56/knez+K9p4dN2+IJ17nZEqGLekLbz7geJ9y/FCKfDRYLRF bTLDXr4kwCJDMlpxBz6VwaXn1Ql5H9ju2jQf2OZLqMo7TaeWKXLC8dqy1uiPCeDCe1Up Ztbipgn2quJPNKiWgd289S1mKGCozNw7U4tXifhVbE9HQVBZxKtvIP0zN7bUKQeTzxm0 aNy8pS2fC38NfShQRG2iu2DNnJJMYzmLc0thup+aEkrl7vrBHp+fDwQgsU9wqRXppQUk 8anw== X-Forwarded-Encrypted: i=1; AJvYcCX4/ji5qlRqMp7B5uoFLuCz0IHWZt8hEMLf4uDhCNT2P1CsDAZgm5FMY9QsZQ2RLgwCCLjEP6Woad4UJp4=@vger.kernel.org X-Gm-Message-State: AOJu0YwY097L7w0C9pJDPl+3lWQYIcUhGL2K7ZRiGb7fVMWYDawQyoL2 PbHASDZZSHTiHjE4cdlMYogT+b+a6C9djKLTs7L4P8/TkCzXhUem5tb+qDeqrk0= X-Gm-Gg: ASbGnctT1m6gfxFtyakFRkyQkG5osdNFai9grqo9j87mEEojz5iClf9FPYNV00+uBND nghhf+K7o5gPnEdjEn2kCke3lTi/rCPvj441R3/yENQBSrfkAsWWbAWk00X+Kz/2Mvq+R7GVIGW orOm7LwYkwk8NNubfjMnbsLW163GIHShp9t71Htspr4+vIp8hnNtEtXz1qfE1shYrnq+8365K0r FxC7OIUQvmMIOqOzT3c5dO1aaNuRdOi2qvi8wzwhKtEdPpsZra50w== X-Google-Smtp-Source: AGHT+IEabF9aXtQp3aenhR64WxS1g9cOj/1L2FSLUAESIqxrn8JkRWX1Txmn+76M6Wb3sexpEyps+Q== X-Received: by 2002:a17:902:d483:b0:216:3c36:69a7 with SMTP id d9443c01a7336-219d96e8fb1mr29034205ad.45.1734594579793; Wed, 18 Dec 2024 23:49:39 -0800 (PST) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc97432dsm6784445ad.110.2024.12.18.23.49.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2024 23:49:39 -0800 (PST) From: Jun Nie Date: Thu, 19 Dec 2024 15:49:19 +0800 Subject: [PATCH v3 01/15] drm/msm/dpu: Do not fix number of DSC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-1-92c7c0a228e3@linaro.org> References: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> In-Reply-To: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734594567; l=1800; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=H71UugjG5IQJFjXijgWx29ezewCBoV9AAKOOrWRKHwk=; b=dUzlSdGY5e36I0gVxFwpQEvjNoLa0A1wdKlZECUaxHkjySXlll3b9Uyws+NzCj8x2f+Y9BgKm sggNoaJFPFdAts/tP1G4bwB5pARZ8tdxN6l7vnKa8WC8Acwxaq2KQoZ X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= If DSC is enabled, the only case is with 2 DSC engines so far. More usage case will be added, such as 4 DSC in 4:4:2 topoplogy. So get real number of DSCs to decide whether DSC merge is needed. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index ddc60e658d63f..650df585138cd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -164,6 +164,7 @@ enum dpu_enc_rc_states { * clks and resources after IDLE_TIMEOUT time. * @topology: topology of the display * @idle_timeout: idle timeout duration in milliseconds + * @num_dscs: Number of DSCs in use * @wide_bus_en: wide bus is enabled on this interface * @dsc: drm_dsc_config pointer, for DSC-enabled encoders */ @@ -204,6 +205,7 @@ struct dpu_encoder_virt { struct msm_display_topology topology; =20 u32 idle_timeout; + u32 num_dscs; =20 bool wide_bus_en; =20 @@ -622,9 +624,8 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_= enc) if (dpu_enc->phys_encs[i]) intf_count++; =20 - /* See dpu_encoder_get_topology, we only support 2:2:1 topology */ if (dpu_enc->dsc) - num_dsc =3D 2; + num_dsc =3D dpu_enc->num_dscs; =20 return (num_dsc > 0) && (num_dsc > intf_count); } @@ -1261,6 +1262,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct d= rm_encoder *drm_enc, dsc_mask |=3D BIT(dpu_enc->hw_dsc[i]->idx - DSC_0); } =20 + dpu_enc->num_dscs =3D num_dsc; dpu_enc->dsc_mask =3D dsc_mask; =20 if ((dpu_enc->disp_info.intf_type =3D=3D INTF_WB && conn_state->writeback= _job) || --=20 2.34.1 From nobody Thu Dec 18 20:22:07 2025 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F356217728 for ; Thu, 19 Dec 2024 07:49:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594587; cv=none; b=pxjiq/KiLMJhG6cuzh8+nU91P7chHnTdJzwsGSKHKQjBcUvk9xkv2dRrjDEwNre6ci5OJdlldkwx09sna4cw1CXDxkccISE9qJRWctvRE0VQ6iKUJsY0fTWLE4b/5AJj6B5eaVapXXoDYph7xr9sGrvCsx1e3wtTRCIQz+2hdzw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594587; c=relaxed/simple; bh=dEsdzF1H8mOIfM+sxcd5TqOuqI1FUZfMvRVAMT2Swjc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Rqd5Mzs+PIQ8lAooo1w6a8hUxPxB4bB4+rUPzF6SLY8qh8iE5/FB5XKVaHaYYnfPdW5NXb8h0jax4vKT6w5/xdLEzvslqtEQYi2hzHvu99mnlFptKEqzIIsTH9Rh9TYxWEHD7GlW+iGWsBO6W0sbNOGX3w0FIumTmLbo6B2b5PM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=hfA1B3rB; arc=none smtp.client-ip=209.85.214.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="hfA1B3rB" Received: by mail-pl1-f181.google.com with SMTP id d9443c01a7336-2164b1f05caso4291615ad.3 for ; Wed, 18 Dec 2024 23:49:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1734594585; x=1735199385; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=YL0eJAJsn+bF1xqyLJhetwK7icVAiboBpbquincLAUk=; b=hfA1B3rBgjRBWHj5npffCQxT5B0pvthpX/iIycifs5aNZQStpZ7Sl53pTnIg3mSS2L grECRfQEHPQhixIo2WPEDDhyuKIvs155rI4+eRMiFMG6g4lp/yE9OkkIA6IIsJHIVA2i MXyau5AS1cdMvFIYvcAXC2JexGU4zYirRE65vQ+m15zD6Qnh1yxLkvo0iWUE6IObvaBO TKXOJTwKz9l+E/VFnKmBP93aSK34mBq6tonNe9+c8XaW/CvZyCFSY/U5T0euhwKR5iaY yKxSwZ4cpfZ8GRLV9Y6TZ9M4ZRjDlB0Lh+98ikwB0HMYRf7J9IlFXESmGlKlUonsiXjy RlFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734594585; x=1735199385; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YL0eJAJsn+bF1xqyLJhetwK7icVAiboBpbquincLAUk=; b=J5WFjEx03WGxodjLMnE1ivG5KsJgil/O/nbh5P/uYCj6SNJd3vgpKq5Oco2bMtugf6 6PRVYQM9Wh6t2vT4sg8gYkJ/xjosO7lDdL79CbaUvjqzD0zN6CjnMvSBP27K9wNf+jks GLilnLx9uoZ2g1jbBEyOR0+0LQxc8JoeKKINV3Yd9UZVQGViu2G0h0etNUFw6XXK0ysk AM57BnDZLnOMWWSgrWw+hQlcDapprtl/JUaBnsmCFF1SsqJT5HLpaUAyT+Xz/R+Wq5IR kV4nELtxrlkD+ICBii47yA0aiyreuzJLSWlI1rI13tBurGaAYLVqkavCLRgRfTywnBBO U3Lw== X-Forwarded-Encrypted: i=1; AJvYcCXWDa6/w6PamQRgGwA34TKiTQcydBpMYeg3DYTCCUN6JemJJrCMYPZJG47IyUd7Q/78Vd0DTB/L9lBLyHU=@vger.kernel.org X-Gm-Message-State: AOJu0YysbsczZ3BdqqiQBpfGG4Pz3/5YoWscMRY7O8cZvcLG3QJHXG2+ LLWkA4sNqETCWf0lf0YxegJoScrH8m2F51W65gMPHF742MCGOCkdx7y1JLFW0vg= X-Gm-Gg: ASbGncsIgJFWrJ6HJkF8EpEIpQeSbKSY3bDeOnlkZnCsbn9xBEiQXgQ56s34rKkZ45Y r+L344Q5u6SPu0OgKH55/IiB80MbAJHctPaW6t1pzx94XTfQkhq/EIGPFOIjqs86dzd/gnXmXhM a70AG20M65PYvV4IEQK/PBwISA28Pto0U+HxtdeY8I8qH2zgdREFsA6vZgdjHqjsnFmrgQrECCa 4zIqPV8yZsDoDwJVSD3KtXvk54lNL87Tu3xu9pOdJIJ32O3iprzEg== X-Google-Smtp-Source: AGHT+IG8rv5UfI7SqBNEnpsP6TqIUeKqwCRsTWaZTqEBm7avzTjZMTdrTbSgeuVwf1Up9AP+9yofcg== X-Received: by 2002:a17:902:f542:b0:216:554a:212c with SMTP id d9443c01a7336-218d725b78dmr84056735ad.46.1734594585506; Wed, 18 Dec 2024 23:49:45 -0800 (PST) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc97432dsm6784445ad.110.2024.12.18.23.49.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2024 23:49:45 -0800 (PST) From: Jun Nie Date: Thu, 19 Dec 2024 15:49:20 +0800 Subject: [PATCH v3 02/15] drm/msm/dpu: configure DSC per number in use Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-2-92c7c0a228e3@linaro.org> References: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> In-Reply-To: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734594567; l=1681; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=dEsdzF1H8mOIfM+sxcd5TqOuqI1FUZfMvRVAMT2Swjc=; b=rrqwTWpMtEAIaU36uDB76/XIvHkIBNMil6khUbR4tZDKfFmCUSldk1LyQIc7lN+lIjC8yU/yR uHMpx/08OwiCFgHnHxKMoea7xtwZyW5YCHEUxhMwkxJ2WVoHoyjsUse X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Currently if DSC support is requested, the driver only supports using 2 DSC blocks. We need 4 DSC in quad-pipe topology in future. So let's only configure DSC engines in use, instead of the maximum number of DSC engines. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index 650df585138cd..cc23f364dd080 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2028,6 +2028,7 @@ static void dpu_encoder_prep_dsc(struct dpu_encoder_v= irt *dpu_enc, struct drm_dsc_config *dsc) { /* coding only for 2LM, 2enc, 1 dsc config */ + int num_dsc =3D dpu_enc->num_dscs; struct dpu_encoder_phys *enc_master =3D dpu_enc->cur_master; struct dpu_hw_ctl *ctl =3D enc_master->hw_ctl; struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; @@ -2039,7 +2040,7 @@ static void dpu_encoder_prep_dsc(struct dpu_encoder_v= irt *dpu_enc, u32 initial_lines; int i; =20 - for (i =3D 0; i < MAX_CHANNELS_PER_ENC; i++) { + for (i =3D 0; i < num_dsc; i++) { hw_pp[i] =3D dpu_enc->hw_pp[i]; hw_dsc[i] =3D dpu_enc->hw_dsc[i]; =20 @@ -2068,7 +2069,7 @@ static void dpu_encoder_prep_dsc(struct dpu_encoder_v= irt *dpu_enc, enc_ip_w =3D intf_ip_w / 2; initial_lines =3D dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w); =20 - for (i =3D 0; i < MAX_CHANNELS_PER_ENC; i++) + for (i =3D 0; i < num_dsc; i++) dpu_encoder_dsc_pipe_cfg(ctl, hw_dsc[i], hw_pp[i], dsc, dsc_common_mode, initial_lines); } --=20 2.34.1 From nobody Thu Dec 18 20:22:07 2025 Received: from mail-pj1-f52.google.com (mail-pj1-f52.google.com [209.85.216.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4469217F2F for ; Thu, 19 Dec 2024 07:49:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594593; cv=none; b=UoLAZXC0Dfr1o7OCoRvJYLIl5eKs01x8gvyAJKVqhUF6Wk2SRdRHmI78khtgvMcbzfREOaBOzHW+tgrPTEYJJhX2LlUG/QieByk2uIxQU2UsUJp693M53Op/S5r7Cb5h6VdWRRhVxaewmvslR6p+92jKhZwCkj+H8/ys9s7ogIQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594593; c=relaxed/simple; bh=OspW4wNM9FswzvS293zm/N/Rth99PB/cv63qlI1/JXU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iqAQz+Dy7pR7yxBDFEn+bcF5lIyy5J5zuJlyGSWaacDGhSFO+OhTfpVnIOZEnS44lCQyPg8K77gT0O1w91J4vRvJ3+sttKjTx+8/VUEtTNyB2/8dUkJCuhQfpC9HyNBf6MhGmJmqyhx8f9/uG4OirdPgd2G8KyLdKddkQKfubAY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=JEv/+NqW; arc=none smtp.client-ip=209.85.216.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="JEv/+NqW" Received: by mail-pj1-f52.google.com with SMTP id 98e67ed59e1d1-2ee397a82f6so451935a91.2 for ; Wed, 18 Dec 2024 23:49:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1734594591; x=1735199391; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ntwyeNHAM8vdoBllqLbul3GM7LuDoqcfQURQf8f/iyY=; b=JEv/+NqWy2ps6EFbVeajqDStg9Wfb4VAVlGk0irrDrYZQ0X8lx8+qd6ggPIrGqojY6 5PNofg4BM7OWshh7DTGkgWqpIXfWmp7acApALB14I2AkDD4QWi+HY4oyvmv6B8n6dmm2 dg9Pg76Z3fLPY7cgJ/Sy+Qiqi+9X88LYkIWSEoRRDgeZsw0KFa5/jgkLSX/vQJy+u3mM BpJThCafunpNmB74LkKHRYllIZRJaBpMQGUFBJCkG052DY1C4/x2qwan/tpjwsgS/Th7 mNasWrkq0r1Y9xmW/BSlqvaA0u+TO2utrMMxz+wkB/xdSmylCVBQKwqB04t55cu1LQpD 0mAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734594591; x=1735199391; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ntwyeNHAM8vdoBllqLbul3GM7LuDoqcfQURQf8f/iyY=; b=KfI6h9937INS1w5mA2WUZgxW5SqIdL8TdHVRg77AaratW7zU6sZoqBg5c2JoznPWik VAzQHZnyjA4VvK8dj8OKvDi2HcFuQZyuiVICtsjPXBBZSmx6YyAD5DSsU4ETDFvRgnVA grcuT7IE8yXOP+eiWhgHo7kICcV2lok+jjHKW6f8G0WPtLL4TIWi4AlofDV2L8rfAqVA MTtJ4fCX3ecB7wcnqbQr/nmz1bej2FPJZ84XjTNgRDpwCqG55oT/ZHWC7JCL1YXhy5ZY XenMXGOF+SyYFGm04FtsYm2PdlBfwWapVQClGi0FHZcZOQi6KaNpYdvpUNKpIB5K9hN8 WD6g== X-Forwarded-Encrypted: i=1; AJvYcCU7wNOK0cdm3u4FB+MQItRn5IvnurgiTDY6WAO+1Jzw7QOcTtkqcANOHI1KEJrhqtKrCWqMzZvKg38kiM0=@vger.kernel.org X-Gm-Message-State: AOJu0YywDSPumDt8bl6oBbueNopOeTGA3c6d99Y/ZU7Aa2BtpEG8qgon MQOA3mk08Bw0mDRKP00iRl/loJONoLdw4t/9rIoG8ov1qtnIsyzMQ0X0nTEa6N0= X-Gm-Gg: ASbGncupoRaB2xODuws7vtS3cN0gYBKRazpJganqs5WywhNmjW8Z41RRemDsZFvMRYR XG3VMIuWtaY5FeP04EjAgcoZJihgarW/25RLIXfq8NQJwil6dy8dukfpfHiv3SctCzWoizx2ff/ SBVW9Jr5QO592iaFJCVe3WeMtwaUEhC0cOf28frzDdBJJs/1snluHXsJ1Fi16AYmdn6Fb31RDPm qugx2rZ178Ws5yeeFeqWUDc9pPm2o9y3QOqYBMiLqiXqJLsN4hSuw== X-Google-Smtp-Source: AGHT+IHylhqGksguRWryHJqU/y1cSrvMKT7OODzv6gUo595Vy99rw8bFUAq9w5knvwhJEVvpdpUdWg== X-Received: by 2002:a17:90b:2c84:b0:2f2:a664:df20 with SMTP id 98e67ed59e1d1-2f443cd2db1mr3408286a91.7.1734594591238; Wed, 18 Dec 2024 23:49:51 -0800 (PST) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc97432dsm6784445ad.110.2024.12.18.23.49.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2024 23:49:50 -0800 (PST) From: Jun Nie Date: Thu, 19 Dec 2024 15:49:21 +0800 Subject: [PATCH v3 03/15] drm/msm/dpu: polish log for resource allocation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-3-92c7c0a228e3@linaro.org> References: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> In-Reply-To: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734594567; l=1781; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=OspW4wNM9FswzvS293zm/N/Rth99PB/cv63qlI1/JXU=; b=6gxzO2YImydOFCnp2SlOv3X4bZtMMSqMY8E3b6yJztQzfBRFpLy3nUYay6jc7K4FHaZ/VOBRb b9X2Qi8xVxgCxd/pUAJxWOnuN4H81YbCeer+5H49yOhoSYQvDF3bI0A X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Add resource type info on allocation failure. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index 6dc3fa79e6425..cde3c5616f9bc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -814,6 +814,21 @@ void dpu_rm_release_all_sspp(struct dpu_global_state *= global_state, ARRAY_SIZE(global_state->sspp_to_crtc_id), crtc_id); } =20 +static char *dpu_hw_blk_type_name[] =3D { + [DPU_HW_BLK_TOP] =3D "TOP", + [DPU_HW_BLK_SSPP] =3D "SSPP", + [DPU_HW_BLK_LM] =3D "LM", + [DPU_HW_BLK_CTL] =3D "CTL", + [DPU_HW_BLK_PINGPONG] =3D "pingpong", + [DPU_HW_BLK_INTF] =3D "INTF", + [DPU_HW_BLK_WB] =3D "WB", + [DPU_HW_BLK_DSPP] =3D "DSPP", + [DPU_HW_BLK_MERGE_3D] =3D "merge_3d", + [DPU_HW_BLK_DSC] =3D "DSC", + [DPU_HW_BLK_CDM] =3D "CDM", + [DPU_HW_BLK_MAX] =3D "none", +}; + /** * dpu_rm_get_assigned_resources - Get hw resources of the given type that= are * assigned to this encoder @@ -874,13 +889,13 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, continue; =20 if (num_blks =3D=3D blks_size) { - DPU_ERROR("More than %d resources assigned to enc %d\n", - blks_size, enc_id); + DPU_ERROR("More than %d %s assigned to enc %d\n", + blks_size, dpu_hw_blk_type_name[type], enc_id); break; } if (!hw_blks[i]) { - DPU_ERROR("Allocated resource %d unavailable to assign to enc %d\n", - type, enc_id); + DPU_ERROR("%s unavailable to assign to enc %d\n", + dpu_hw_blk_type_name[type], enc_id); break; } blks[num_blks++] =3D hw_blks[i]; --=20 2.34.1 From nobody Thu Dec 18 20:22:07 2025 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B92B217672 for ; Thu, 19 Dec 2024 07:49:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594599; cv=none; b=ZkBIT5k9iSlzgdFCWTA2vVUktIHnhnBZrrUEUrlO6cEsXUoINE7pYwygqlq4aCYv9cKd3nGX/+sLPA5Qu+GTWhPKmFI8wboSMz4WLm7Rjlc9F6oYk4NrX2h0O48Kuwvz8gO91Egasqss0ZJT2I9OfsAegcit29fkbL4WGwYCWvM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594599; c=relaxed/simple; bh=SPyiBgL3hfMVngEeCufF2JBzxfqk/rbHqElyh4UjDxo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VJAUd+54MLXI/fLP2kr7VibDDunUInJ64xF5F3o3+3myqL2FExxLiToOYfMztqy5xbFH6zbwN0KcixOHv+cx8MOrp9xbM2lqtLQdNNSYT6bcEF6ql856Gef7IdZszweFB3T6T5e0zaYxxZLfoj+cxpu/PZRf8YjX20JxPKuWHNI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=I6M3HU+7; arc=none smtp.client-ip=209.85.214.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="I6M3HU+7" Received: by mail-pl1-f176.google.com with SMTP id d9443c01a7336-2163bd70069so4879975ad.0 for ; Wed, 18 Dec 2024 23:49:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1734594597; x=1735199397; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Kt1DlYp93VR60ha+vWGXO3XGir76XTQggij8rAuDIM0=; b=I6M3HU+7Z1PQKTfBRUVJF23W8MsMkDYfa7Z4gYUp9jYN0ikMIknxzxs17DmhebBgH6 ar3kUveAmrlS+7QRFtsWMjZdaSvvcO2xSbA3FjzLHCnvX7prgOMwTt5fm1AUBUvIQ6Kf KW5zGkoRqZ8J//veZfaVT100wgRQvsVJ7qfyEyGoT6/5m/R4M0nOsJJw7Tti6d27qMvZ 1etw1oO2r5pmD+zpuWxtYvbK4oBWGLWD0YLjjracCgk/yii529a5YhNuFoirxOvaHhXQ hppdXEelTzKHenHVlUxeD4OUlnu3uNeayChw2c/yWlHFOLQtznQt19O4/6K/CmAenIdm qsDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734594597; x=1735199397; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Kt1DlYp93VR60ha+vWGXO3XGir76XTQggij8rAuDIM0=; b=Nr7mDmClXKdCjxyulfan7v3fcyaYpcQiUYejAHx82FZxsmWUq6j5JHFNIxsJtbPoLY 5w49ZRJLzGdbgcKJnsFufqLvFCVwamX+nAXSxdmuM63bn+o0tjb+2xjftoTubPZ42Zli cj1yc9H2VQFxjI71WTB8nlighvgsUvDKJ3ArMWd+ofFYv+q8yRii9tRrMk3kxx+rnc7x oa58CMj4w2pZv9UNclHNKcfzjSTMXZVEmdjMLk71UCaawXYLknpB8wnVlDMXKzSquXww J7yjv/4N4UpNsjNlIgg4TZv1B4KZudYf4iG2WvjpiBT7ZipB/hz+/7gbHV8B7xYWAyI6 0cMw== X-Forwarded-Encrypted: i=1; AJvYcCUpLHyLh0BxmksL+ZPhjbJaOYc+Ihm7rx6w8umr4r7JGHiRYAf6z6ft3kA+Tj8WRy/oVY/do1MndBuHAak=@vger.kernel.org X-Gm-Message-State: AOJu0Yzf+a0PtcFJRaZw1qvtMUJS8bXbVg+515O79KAh8xRtnFCDGcCI 8LdA0FEWG+rTx4OpyzycR+DDgd7vwAa65RbFGBO7gopE3AwPDQXJt2ziYBkxSr0= X-Gm-Gg: ASbGncsW+Pr0D/+TI+DPspkarYC82WuiYi71FnKAjc8dwz47bs4Hb2lj/Qs2ZTDLLdE Y5jc0iddhAxgVLxrzJJ5ZCJ+sjDT2kvr05bvzHKleqIQFUcNe6YP/W6LZZrPhN8MtvH4qTKojir UawpQ1ueeeQpY4lRrweNWi0XpY2b3o+K4D4wh+f0fHweEmkPd/HuHIfDaZzFkZgiZVKKD17pHOH oxoIjicgsfJArmQ8L6TJSBYB407WCx7/ySrqQy1dqHozCwpIQX5eQ== X-Google-Smtp-Source: AGHT+IEIuQm8BM3R5VmAdsk7F2I4BPZS0vz/z5taFEvNb6zAXkyIxwrf4C4EqP7xNztbzEzQR/bRgw== X-Received: by 2002:a17:903:2b0c:b0:205:6a9b:7e3e with SMTP id d9443c01a7336-219d9901901mr40917305ad.56.1734594597497; Wed, 18 Dec 2024 23:49:57 -0800 (PST) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc97432dsm6784445ad.110.2024.12.18.23.49.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2024 23:49:57 -0800 (PST) From: Jun Nie Date: Thu, 19 Dec 2024 15:49:22 +0800 Subject: [PATCH v3 04/15] drm/msm/dpu: decide right side per last bit Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-4-92c7c0a228e3@linaro.org> References: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> In-Reply-To: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734594568; l=1407; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=SPyiBgL3hfMVngEeCufF2JBzxfqk/rbHqElyh4UjDxo=; b=pXN0nYxNuCAd3few9qkZw0NaAGt1iWhzQs66UXTaamXatgEGLwTZGiI8Z767QZ3Inz+g1Cy5J +a46j5hy40OC+6jLhxP11YqtKClm8L+DXz2Iar2rUdv0mCjmJ+T+eZ/ X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= decide right side of a pair per last bit, in case of multiple mixer pairs. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 7191b1a6d41b3..41c9d3e3e3c7c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -369,11 +369,10 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc= _mixer *mixer, static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) { struct dpu_crtc_state *crtc_state; - int lm_idx, lm_horiz_position; + int lm_idx; =20 crtc_state =3D to_dpu_crtc_state(crtc->state); =20 - lm_horiz_position =3D 0; for (lm_idx =3D 0; lm_idx < crtc_state->num_mixers; lm_idx++) { const struct drm_rect *lm_roi =3D &crtc_state->lm_bounds[lm_idx]; struct dpu_hw_mixer *hw_lm =3D crtc_state->mixers[lm_idx].hw_lm; @@ -384,7 +383,7 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_= crtc *crtc) =20 cfg.out_width =3D drm_rect_width(lm_roi); cfg.out_height =3D drm_rect_height(lm_roi); - cfg.right_mixer =3D lm_horiz_position++; + cfg.right_mixer =3D lm_idx & 0x1; cfg.flags =3D 0; hw_lm->ops.setup_mixer_out(hw_lm, &cfg); } --=20 2.34.1 From nobody Thu Dec 18 20:22:07 2025 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7059E21770D for ; Thu, 19 Dec 2024 07:50:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594606; cv=none; b=r50muHsO7ET/c0ZUPXxkvS+9W3+4NaD82rWbRO9HUXv45WLQCR96+i9KRQG+stk1se/obVs9cQlf497j3m5FmVzH276vseiCZ7vO9a1fcicAZWN+vwqI4JJZft3uziPtb4xGsVVfFcSdQfJTZeYJXCe8lVSyoNAmwqFTuAh4p4Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594606; c=relaxed/simple; bh=sXtw14ojL1neJpubSJ95lKQnBR+uGpxyPZIo6yVfEbw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=p1+EKjp/GFE3j2XeB63T9eiOHthwIA7MSAqqdehRTQNnN/qsKpx6SRYf51i7H3xEsZg3MubPW177DUzhNsRB6RMYoMbfnCW4vSu9uL1vS4r4cu7AQjGviVpbA+9HJ8AL+nHdKwYH3e/EgD/N44OrdMEVv2h0UmuU4/q8sxDN3/M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=wOG8vsgc; arc=none smtp.client-ip=209.85.214.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="wOG8vsgc" Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-2165448243fso5501825ad.1 for ; Wed, 18 Dec 2024 23:50:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1734594605; x=1735199405; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=bLZanIqkjuT24X5eyWurXtsoG0wesos+nlrjmuUr9cs=; b=wOG8vsgcfxcBDXsdFTB1Y8XM8d5wdy7mxcIHXrEYdmuMUQPkdpMvSd3FCKGCsk0tbJ GktQ4vjpJ7XbU26yhu9KKoEVBUEn0npfzhYHo+d6QHeO0IELfzGLG6G+F5Jd5hJx3bIo Iq1pM/q5Aa+Wd3E1joUzKY2tLsS1ZtyTfoZHL1PMW1xfCA7dEd3+XZnfdPwY2tcvausM ptBQBzZtI87TGod4n7w/kd3FgJbgy9W/zKRgjiByyHK/C7vrv2fk4zKnGUGUhTnNDERk lonsUji3dXJc29myNFbD4Qti3m9YrCj1abd9lZgFwt7WCimo4pSaL9OM8Tdx88IUcdyi iPrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734594605; x=1735199405; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bLZanIqkjuT24X5eyWurXtsoG0wesos+nlrjmuUr9cs=; b=jpV1JNaKMx5szQhPTiTbheBmzD5c5iIBRkl1Zlkw/tQXo6XO+AVIlBr0sGuOsWQLfj 6mHoSA1X7+JkaK54OUUl37lgoFYnAK5PFAE8yx/yRMrla6m0x7oYZxZniiPvQIFPdo0l a3zI30L9v7ZcVSxfvf9gk3xF6T4BvoXDAJMhbGfqhjgjruZuR+F0UG2knr4spWWaG08I /AVoKxyhHwls9Fh5bYReh0rd11p5Qv64J8j9u/8yoTUshhHwB8ew1gxvVsMXk4c6fKlC XRBcM0ozAZZbzLUrFCHtYQXlaNTM2Qldu8+qBFNrR8MtBYdR7FfHLqxx6muhMfpWHkzR Nyog== X-Forwarded-Encrypted: i=1; AJvYcCVFxKf7WkyJeY1bbUH0ZBlVVNbrzjtB2/ZL2QLcJalUultHpwPfeMrnOrOyCBDQggCbvZuPyUesJ4PoDHI=@vger.kernel.org X-Gm-Message-State: AOJu0YwM1OQOvnTxsq5JJwAGdoeCGua+cVbo4s7nyPeltGyTiCKN3iW8 k4KufVa7cFWNldIWsjSIkhJtRR5gght3eq/U5ctBGpuVq/suKggV8PT79bf8gX0= X-Gm-Gg: ASbGncupLJgyRaVghWsx2DkyYW/8wvSNRvclmzBVGih3cPzo2hGE2UthUvSrR72hmhM pP7tMHaYDwgBmdODnNXpI39k3WyqbfvvoJ0EgmgfUxPQ64U3Ggk25SNa/2H1n32E5Mglqyrk/Ba 0N4+xJK+pLRmXF3driyHwFZXlweTA10hf5F59ydHsO+4TZMiOYEelqdeg+KJ2JlS3iXPhEnlrLA t5s0lEi/oOvp99yrz6F1B1k5G9pfRNsj3PpkNgaEO4i5QbpoGMCTQ== X-Google-Smtp-Source: AGHT+IFXiY8We5Q0+brfxd3GD7LjUDQdDdIurNlP5jabQPEF90oqCKt+ZSHV3YR8ACFOHfVNF5ZgXw== X-Received: by 2002:a17:903:24e:b0:216:49b1:fadc with SMTP id d9443c01a7336-218d72529e5mr89035695ad.42.1734594604804; Wed, 18 Dec 2024 23:50:04 -0800 (PST) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc97432dsm6784445ad.110.2024.12.18.23.49.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2024 23:50:04 -0800 (PST) From: Jun Nie Date: Thu, 19 Dec 2024 15:49:23 +0800 Subject: [PATCH v3 05/15] drm/msm/dpu: fix mixer number counter on allocation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-5-92c7c0a228e3@linaro.org> References: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> In-Reply-To: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734594568; l=1237; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=sXtw14ojL1neJpubSJ95lKQnBR+uGpxyPZIo6yVfEbw=; b=uhe3cG7vSVDd8zvBrsHOn6GmlwDxsTZ7AbcwvCWm81qkXmw0KR5vmjtRn9kraYnZCrlQphv3n ChKiSca7AswCjd1Ey96jMu8FwF/yTtLPcD9AvGOGL+kQiFHvYF5kx9a X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Add the case to reserve multiple pairs mixers for high resolution. Current code only supports one pair of mixer usage case. To support quad-pipe usage case, two pairs of mixers are needed. Current code resets number of mixer on failure of pair's peer test and retry on another pair. If two pairs are needed, the failure on the test of 2nd pair results clearing to the 1st pair. This patch only clear the bit for the 2nd pair allocation before retry on another pair. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index cde3c5616f9bc..a8b01b78c02c7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -316,7 +316,11 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, if (!rm->mixer_blks[i]) continue; =20 - lm_count =3D 0; + /* + * Clear the last bit to drop the previous primary mixer if + * fail to find its peer. + */ + lm_count &=3D 0xfe; lm_idx[lm_count] =3D i; =20 if (!_dpu_rm_check_lm_and_get_connected_blks(rm, global_state, --=20 2.34.1 From nobody Thu Dec 18 20:22:07 2025 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF9D621771E for ; Thu, 19 Dec 2024 07:50:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594615; cv=none; b=DfIo+RlK7qYcVunpZy0NdO7tbfnug5a1ARttbS7VJqX7L1SRt6au0lq3HduO7+/uhlIVy4aA0mwgmzTM+k4A/5wYm9qNWDylSjlWiABLFYGzPuKcWndJtQXKUAnTSpDWknLnFpOh6ijDz8/LGhwdrd8j4niJ1ciQeG1RvbkQfMc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594615; c=relaxed/simple; bh=QU4PG4xOK4PMc09kz7jvmloOreDs7Th8a7KQFCA6X24=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DUf8xw3rW75P2o3pcF79SBmSA77DHKDJZ4gDtlRNbmHScTlroHPyZkGCTS/MOuigXo78uKHDixFBxlUr8m+CwTK+KQrs6+GxI+I4AzyMc8oq62Xz7f+mLjbL2eSIjvcQr0d/WJiMlB/Rox+7mdtGCiQ1hJMBv4kGvkviCJRrAQo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=EgFz6TD4; arc=none smtp.client-ip=209.85.214.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="EgFz6TD4" Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-2161eb95317so4318185ad.1 for ; Wed, 18 Dec 2024 23:50:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1734594612; x=1735199412; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=X1AYooxfGigFVMXG/a3oYuoA58zI9vfT+nS7j53GhAk=; b=EgFz6TD4u/mwt59MXBdenpdiL7w6HD4JR4Z/LSAptyByiHMg82czw3t+u4NOnjq0J1 sGPatmOQBZDN0NVY9v7LZHTC5TwhN9/Sn7bdjLkL5fEG2MDv5XA6jYUOfQlo27cZQ0b7 VbyvuMar/ZsNRO01ckmLJDo7T4mLqu9nC8isl67wO0obcqeWNAa87bWzNjHtjlPUIPg7 GvK7rMvT2diOawjdHtB0vlkd8u7Ms6i2wv2edSJs6DbNfNWCzHvvm7FC6tLhKZFAL/oy REzhrj0l2w2HXkylPMWkfKHzAS3W0UqnKsOoxF9nEvzMxUfSrVErJ8XYLPp/sqRd9Mj6 /0PQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734594612; x=1735199412; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X1AYooxfGigFVMXG/a3oYuoA58zI9vfT+nS7j53GhAk=; b=ZOHidpMqWNq3GfjYM85WTiHkCmF/jsQqDUWb1N3rzqGTump3ZlwVRWz4EK8vbpfCna /AiUq/Oq5bU6ld/DpGHx2d4cUQq0fdAkcBr+ExBwuMs6e7zuKroWjYDabvYq3u+o8C/B sDSyNuZpb+ZtNBrNNeHICzbmSALx6m3MkL6SW6YirQgm2J937EZUpP4RVZcYIozwtu/g OMQP762reHYpyDxk05mXZZ/ivO2zEdyFlEZbYi1Obvd0K/eFRJOebPR2SBnQMY3VLDK2 /0gmzw7bqW7xAuRG3TtsplxDs/x0iH4hbs/p9zysyLHmzKngAIxYyL39kX4g6HcosYw4 WgeQ== X-Forwarded-Encrypted: i=1; AJvYcCVO7va80sKRS/mEL8l0i0hD0qDZdhlaeOZ64VX0mrEqXumnPCxA3m4ZgYPpRFeW4ajW1iaoGu1jsF7xUzI=@vger.kernel.org X-Gm-Message-State: AOJu0Yzcn5rt2dseaxa2vkCVYXdOBRCmAPvIxqBH8ovVdK7lO7FatLhJ LtlfnsNwhbVjF4B1U1Hxpl6eWdFEbE8YuhicompgUiOd7Vc8nb0SQ6XWm1jJz5k= X-Gm-Gg: ASbGncvjT12A31iBSD1oIC4lbVvZ2KBgQ4B5HPyPSxTfvhaQpzRgVfo6cVcazvawb17 HCBkBHu8MUilaPHGd6D5qHuJL4xPilPTnjTfHpx8pKnLyRQUz6RgUdB6TrAFHxMNW7NG+1KrKML HMmyjRgq0IGJMA4mfd/arcFchyf87IVPUYPZqX78w9OzfeK/gcb3hBnD3+9Vv9PXcWqXtttSI4S THJx3jtQHiydH4bW59DaoJO+Vu/aCTHHdXWJIcMikH7t8AWwZ6L+g== X-Google-Smtp-Source: AGHT+IG6DP3Pw/xbgB8d+qA4uudN+D1JEH8ZvvESLkrbkrr8GCA0YdE4fz7tc0EAEteZs5WrQVyC0A== X-Received: by 2002:a17:902:fc4e:b0:216:5268:9aab with SMTP id d9443c01a7336-219d97004f8mr41500025ad.46.1734594611818; Wed, 18 Dec 2024 23:50:11 -0800 (PST) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc97432dsm6784445ad.110.2024.12.18.23.50.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2024 23:50:11 -0800 (PST) From: Jun Nie Date: Thu, 19 Dec 2024 15:49:24 +0800 Subject: [PATCH v3 06/15] drm/msm/dpu: switch RM to use crtc_id rather than enc_id for allocation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-6-92c7c0a228e3@linaro.org> References: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> In-Reply-To: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734594568; l=27903; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=QU4PG4xOK4PMc09kz7jvmloOreDs7Th8a7KQFCA6X24=; b=7b9QFiaZvDoV9hE7CUCBE+SyP0/q+35dY7qlBK/W0ImwsyXj3SNFSSskErgIpCi1VNWtsv9bC Syd3X4j/glQD1IXxnH1av8tVT8UoR8c+bdMut5vTE3Y2Iug+0l1iceq X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Up to now the driver has been using encoder to allocate hardware resources. Switch it to use CRTC id so that mixer number can be known in dpu_plane_virtual_assign_resources() via CRTC id for sspp alloation. Because the mixer allocation is done in drm_atomic_helper_check_modeset() as part of CRTC operation. While the sspp assignment is in drm_atomic_helper_check_planes() call tree. So CRTC is more central than encoder. Siwtching the id achieves above goal. Co-developed-by: Dmitry Baryshkov Signed-off-by: Dmitry Baryshkov Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 20 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 12 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 198 ++++++++++++++----------= ---- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 32 ++++- 4 files changed, 139 insertions(+), 123 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index cc23f364dd080..fd32ef468d5f9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -716,11 +716,11 @@ static void dpu_encoder_assign_crtc_resources(struct = dpu_kms *dpu_kms, memset(cstate->mixers, 0, sizeof(cstate->mixers)); =20 num_ctl =3D dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); + crtc_state->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); num_lm =3D dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); + crtc_state->crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); num_dspp =3D dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp, + crtc_state->crtc, DPU_HW_BLK_DSPP, hw_dspp, ARRAY_SIZE(hw_dspp)); =20 for (i =3D 0; i < num_lm; i++) { @@ -797,11 +797,11 @@ static int dpu_encoder_virt_atomic_check( * Dont allocate when active is false. */ if (drm_atomic_crtc_needs_modeset(crtc_state)) { - dpu_rm_release(global_state, drm_enc); + dpu_rm_release(global_state, crtc_state->crtc); =20 if (!crtc_state->active_changed || crtc_state->enable) ret =3D dpu_rm_reserve(&dpu_kms->rm, global_state, - drm_enc, crtc_state, topology); + crtc_state->crtc, topology); if (!ret) dpu_encoder_assign_crtc_resources(dpu_kms, drm_enc, global_state, crtc_state); @@ -1245,17 +1245,17 @@ static void dpu_encoder_virt_atomic_mode_set(struct= drm_encoder *drm_enc, =20 /* Query resource that have been reserved in atomic check step. */ num_pp =3D dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp, + drm_enc->crtc, DPU_HW_BLK_PINGPONG, hw_pp, ARRAY_SIZE(hw_pp)); num_ctl =3D dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); + drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); =20 for (i =3D 0; i < MAX_CHANNELS_PER_ENC; i++) dpu_enc->hw_pp[i] =3D i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) : NULL; =20 num_dsc =3D dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_DSC, + drm_enc->crtc, DPU_HW_BLK_DSC, hw_dsc, ARRAY_SIZE(hw_dsc)); for (i =3D 0; i < num_dsc; i++) { dpu_enc->hw_dsc[i] =3D to_dpu_hw_dsc(hw_dsc[i]); @@ -1270,7 +1270,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct d= rm_encoder *drm_enc, struct dpu_hw_blk *hw_cdm =3D NULL; =20 dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_CDM, + drm_enc->crtc, DPU_HW_BLK_CDM, &hw_cdm, 1); dpu_enc->cur_master->hw_cdm =3D hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL; } @@ -2197,7 +2197,7 @@ static void dpu_encoder_helper_reset_mixers(struct dp= u_encoder_phys *phys_enc) global_state =3D dpu_kms_get_existing_global_state(phys_enc->dpu_kms); =20 num_lm =3D dpu_rm_get_assigned_resources(&phys_enc->dpu_kms->rm, global_s= tate, - phys_enc->parent->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); + phys_enc->parent->crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); =20 for (i =3D 0; i < num_lm; i++) { hw_mixer[i] =3D to_dpu_hw_mixer(hw_lm[i]); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.h index 547cdb2c0c788..54ef6cfa2485a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -124,12 +124,12 @@ struct dpu_global_state { =20 struct dpu_rm *rm; =20 - uint32_t pingpong_to_enc_id[PINGPONG_MAX - PINGPONG_0]; - uint32_t mixer_to_enc_id[LM_MAX - LM_0]; - uint32_t ctl_to_enc_id[CTL_MAX - CTL_0]; - uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0]; - uint32_t dsc_to_enc_id[DSC_MAX - DSC_0]; - uint32_t cdm_to_enc_id; + uint32_t pingpong_to_crtc_id[PINGPONG_MAX - PINGPONG_0]; + uint32_t mixer_to_crtc_id[LM_MAX - LM_0]; + uint32_t ctl_to_crtc_id[CTL_MAX - CTL_0]; + uint32_t dspp_to_crtc_id[DSPP_MAX - DSPP_0]; + uint32_t dsc_to_crtc_id[DSC_MAX - DSC_0]; + uint32_t cdm_to_crtc_id; =20 uint32_t sspp_to_crtc_id[SSPP_MAX - SSPP_NONE]; }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index a8b01b78c02c7..a6a410e301abd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -21,9 +21,9 @@ =20 =20 static inline bool reserved_by_other(uint32_t *res_map, int idx, - uint32_t enc_id) + uint32_t crtc_id) { - return res_map[idx] && res_map[idx] !=3D enc_id; + return res_map[idx] && res_map[idx] !=3D crtc_id; } =20 /** @@ -235,7 +235,7 @@ static int _dpu_rm_get_lm_peer(struct dpu_rm *rm, int p= rimary_idx) * pingpong * @rm: dpu resource manager handle * @global_state: resources shared across multiple kms objects - * @enc_id: encoder id requesting for allocation + * @crtc_id: crtc id requesting for allocation * @lm_idx: index of proposed layer mixer in rm->mixer_blks[], function ch= ecks * if lm, and all other hardwired blocks connected to the lm (pp) is * available and appropriate @@ -249,14 +249,14 @@ static int _dpu_rm_get_lm_peer(struct dpu_rm *rm, int= primary_idx) */ static bool _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, int lm_idx, int *pp_idx, int *dspp_idx, + uint32_t crtc_id, int lm_idx, int *pp_idx, int *dspp_idx, struct dpu_rm_requirements *reqs) { const struct dpu_lm_cfg *lm_cfg; int idx; =20 /* Already reserved? */ - if (reserved_by_other(global_state->mixer_to_enc_id, lm_idx, enc_id)) { + if (reserved_by_other(global_state->mixer_to_crtc_id, lm_idx, crtc_id)) { DPU_DEBUG("lm %d already reserved\n", lm_idx + LM_0); return false; } @@ -268,7 +268,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(str= uct dpu_rm *rm, return false; } =20 - if (reserved_by_other(global_state->pingpong_to_enc_id, idx, enc_id)) { + if (reserved_by_other(global_state->pingpong_to_crtc_id, idx, crtc_id)) { DPU_DEBUG("lm %d pp %d already reserved\n", lm_cfg->id, lm_cfg->pingpong); return false; @@ -284,7 +284,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(str= uct dpu_rm *rm, return false; } =20 - if (reserved_by_other(global_state->dspp_to_enc_id, idx, enc_id)) { + if (reserved_by_other(global_state->dspp_to_crtc_id, idx, crtc_id)) { DPU_DEBUG("lm %d dspp %d already reserved\n", lm_cfg->id, lm_cfg->dspp); return false; @@ -296,7 +296,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(str= uct dpu_rm *rm, =20 static int _dpu_rm_reserve_lms(struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, + uint32_t crtc_id, struct dpu_rm_requirements *reqs) =20 { @@ -324,7 +324,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, lm_idx[lm_count] =3D i; =20 if (!_dpu_rm_check_lm_and_get_connected_blks(rm, global_state, - enc_id, i, &pp_idx[lm_count], + crtc_id, i, &pp_idx[lm_count], &dspp_idx[lm_count], reqs)) { continue; } @@ -343,7 +343,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, continue; =20 if (!_dpu_rm_check_lm_and_get_connected_blks(rm, - global_state, enc_id, j, + global_state, crtc_id, j, &pp_idx[lm_count], &dspp_idx[lm_count], reqs)) { continue; @@ -360,13 +360,16 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, } =20 for (i =3D 0; i < lm_count; i++) { - global_state->mixer_to_enc_id[lm_idx[i]] =3D enc_id; - global_state->pingpong_to_enc_id[pp_idx[i]] =3D enc_id; - global_state->dspp_to_enc_id[dspp_idx[i]] =3D - reqs->topology.num_dspp ? enc_id : 0; + global_state->mixer_to_crtc_id[lm_idx[i]] =3D crtc_id; + global_state->pingpong_to_crtc_id[pp_idx[i]] =3D crtc_id; + global_state->dspp_to_crtc_id[dspp_idx[i]] =3D + reqs->topology.num_dspp ? crtc_id : 0; =20 - trace_dpu_rm_reserve_lms(lm_idx[i] + LM_0, enc_id, + trace_dpu_rm_reserve_lms(lm_idx[i] + LM_0, crtc_id, pp_idx[i] + PINGPONG_0); + + DPU_DEBUG("reserve lm[%d]:%d, pp_idx[%d]:%d, dspp[%d]:%d for crtc_id %d\= n", + i, lm_idx[i], i, pp_idx[i], i, dspp_idx[i], crtc_id); } =20 return 0; @@ -375,7 +378,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, static int _dpu_rm_reserve_ctls( struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, + uint32_t crtc_id, const struct msm_display_topology *top) { int ctl_idx[MAX_BLOCKS]; @@ -399,7 +402,7 @@ static int _dpu_rm_reserve_ctls( =20 if (!rm->ctl_blks[j]) continue; - if (reserved_by_other(global_state->ctl_to_enc_id, j, enc_id)) + if (reserved_by_other(global_state->ctl_to_crtc_id, j, crtc_id)) continue; =20 ctl =3D to_dpu_hw_ctl(rm->ctl_blks[j]); @@ -423,8 +426,8 @@ static int _dpu_rm_reserve_ctls( return -ENAVAIL; =20 for (i =3D 0; i < ARRAY_SIZE(ctl_idx) && i < num_ctls; i++) { - global_state->ctl_to_enc_id[ctl_idx[i]] =3D enc_id; - trace_dpu_rm_reserve_ctls(i + CTL_0, enc_id); + global_state->ctl_to_crtc_id[ctl_idx[i]] =3D crtc_id; + trace_dpu_rm_reserve_ctls(i + CTL_0, crtc_id); } =20 return 0; @@ -432,12 +435,12 @@ static int _dpu_rm_reserve_ctls( =20 static int _dpu_rm_pingpong_next_index(struct dpu_global_state *global_sta= te, int start, - uint32_t enc_id) + uint32_t crtc_id) { int i; =20 for (i =3D start; i < (PINGPONG_MAX - PINGPONG_0); i++) { - if (global_state->pingpong_to_enc_id[i] =3D=3D enc_id) + if (global_state->pingpong_to_crtc_id[i] =3D=3D crtc_id) return i; } =20 @@ -458,7 +461,7 @@ static int _dpu_rm_pingpong_dsc_check(int dsc_idx, int = pp_idx) =20 static int _dpu_rm_dsc_alloc(struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, + uint32_t crtc_id, const struct msm_display_topology *top) { int num_dsc =3D 0; @@ -471,10 +474,10 @@ static int _dpu_rm_dsc_alloc(struct dpu_rm *rm, if (!rm->dsc_blks[dsc_idx]) continue; =20 - if (reserved_by_other(global_state->dsc_to_enc_id, dsc_idx, enc_id)) + if (reserved_by_other(global_state->dsc_to_crtc_id, dsc_idx, crtc_id)) continue; =20 - pp_idx =3D _dpu_rm_pingpong_next_index(global_state, pp_idx, enc_id); + pp_idx =3D _dpu_rm_pingpong_next_index(global_state, pp_idx, crtc_id); if (pp_idx < 0) return -ENAVAIL; =20 @@ -482,7 +485,7 @@ static int _dpu_rm_dsc_alloc(struct dpu_rm *rm, if (ret) return -ENAVAIL; =20 - global_state->dsc_to_enc_id[dsc_idx] =3D enc_id; + global_state->dsc_to_crtc_id[dsc_idx] =3D crtc_id; num_dsc++; pp_idx++; } @@ -498,7 +501,7 @@ static int _dpu_rm_dsc_alloc(struct dpu_rm *rm, =20 static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, + uint32_t crtc_id, const struct msm_display_topology *top) { int num_dsc =3D 0; @@ -513,11 +516,11 @@ static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, continue; =20 /* consective dsc index to be paired */ - if (reserved_by_other(global_state->dsc_to_enc_id, dsc_idx, enc_id) || - reserved_by_other(global_state->dsc_to_enc_id, dsc_idx + 1, enc_id)) + if (reserved_by_other(global_state->dsc_to_crtc_id, dsc_idx, crtc_id) || + reserved_by_other(global_state->dsc_to_crtc_id, dsc_idx + 1, crtc_id= )) continue; =20 - pp_idx =3D _dpu_rm_pingpong_next_index(global_state, pp_idx, enc_id); + pp_idx =3D _dpu_rm_pingpong_next_index(global_state, pp_idx, crtc_id); if (pp_idx < 0) return -ENAVAIL; =20 @@ -527,7 +530,7 @@ static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, continue; } =20 - pp_idx =3D _dpu_rm_pingpong_next_index(global_state, pp_idx + 1, enc_id); + pp_idx =3D _dpu_rm_pingpong_next_index(global_state, pp_idx + 1, crtc_id= ); if (pp_idx < 0) return -ENAVAIL; =20 @@ -537,8 +540,8 @@ static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, continue; } =20 - global_state->dsc_to_enc_id[dsc_idx] =3D enc_id; - global_state->dsc_to_enc_id[dsc_idx + 1] =3D enc_id; + global_state->dsc_to_crtc_id[dsc_idx] =3D crtc_id; + global_state->dsc_to_crtc_id[dsc_idx + 1] =3D crtc_id; num_dsc +=3D 2; pp_idx++; /* start for next pair */ } @@ -554,11 +557,9 @@ static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, =20 static int _dpu_rm_reserve_dsc(struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *enc, + uint32_t crtc_id, const struct msm_display_topology *top) { - uint32_t enc_id =3D enc->base.id; - if (!top->num_dsc || !top->num_intf) return 0; =20 @@ -568,22 +569,22 @@ static int _dpu_rm_reserve_dsc(struct dpu_rm *rm, * 2) DSC pair starts from even index, such as index(0,1), (2,3), etc * 3) even PINGPONG connects to even DSC * 4) odd PINGPONG connects to odd DSC - * 5) pair: encoder +--> pp_idx_0 --> dsc_idx_0 + * 5) pair: crtc +--> pp_idx_0 --> dsc_idx_0 * +--> pp_idx_1 --> dsc_idx_1 */ =20 /* num_dsc should be either 1, 2 or 4 */ if (top->num_dsc > top->num_intf) /* merge mode */ - return _dpu_rm_dsc_alloc_pair(rm, global_state, enc_id, top); + return _dpu_rm_dsc_alloc_pair(rm, global_state, crtc_id, top); else - return _dpu_rm_dsc_alloc(rm, global_state, enc_id, top); + return _dpu_rm_dsc_alloc(rm, global_state, crtc_id, top); =20 return 0; } =20 static int _dpu_rm_reserve_cdm(struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *enc) + uint32_t crtc_id) { /* try allocating only one CDM block */ if (!rm->cdm_blk) { @@ -591,12 +592,12 @@ static int _dpu_rm_reserve_cdm(struct dpu_rm *rm, return -EIO; } =20 - if (global_state->cdm_to_enc_id) { + if (global_state->cdm_to_crtc_id) { DPU_ERROR("CDM_0 is already allocated\n"); return -EIO; } =20 - global_state->cdm_to_enc_id =3D enc->base.id; + global_state->cdm_to_crtc_id =3D crtc_id; =20 return 0; } @@ -604,30 +605,30 @@ static int _dpu_rm_reserve_cdm(struct dpu_rm *rm, static int _dpu_rm_make_reservation( struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *enc, + uint32_t crtc_id, struct dpu_rm_requirements *reqs) { int ret; =20 - ret =3D _dpu_rm_reserve_lms(rm, global_state, enc->base.id, reqs); + ret =3D _dpu_rm_reserve_lms(rm, global_state, crtc_id, reqs); if (ret) { DPU_ERROR("unable to find appropriate mixers\n"); return ret; } =20 - ret =3D _dpu_rm_reserve_ctls(rm, global_state, enc->base.id, + ret =3D _dpu_rm_reserve_ctls(rm, global_state, crtc_id, &reqs->topology); if (ret) { DPU_ERROR("unable to find appropriate CTL\n"); return ret; } =20 - ret =3D _dpu_rm_reserve_dsc(rm, global_state, enc, &reqs->topology); + ret =3D _dpu_rm_reserve_dsc(rm, global_state, crtc_id, &reqs->topology); if (ret) return ret; =20 if (reqs->topology.needs_cdm) { - ret =3D _dpu_rm_reserve_cdm(rm, global_state, enc); + ret =3D _dpu_rm_reserve_cdm(rm, global_state, crtc_id); if (ret) { DPU_ERROR("unable to find CDM blk\n"); return ret; @@ -638,7 +639,7 @@ static int _dpu_rm_make_reservation( } =20 static int _dpu_rm_populate_requirements( - struct drm_encoder *enc, + struct drm_crtc *crtc, struct dpu_rm_requirements *reqs, struct msm_display_topology req_topology) { @@ -652,12 +653,12 @@ static int _dpu_rm_populate_requirements( } =20 static void _dpu_rm_clear_mapping(uint32_t *res_mapping, int cnt, - uint32_t enc_id) + uint32_t crtc_id) { int i; =20 for (i =3D 0; i < cnt; i++) { - if (res_mapping[i] =3D=3D enc_id) + if (res_mapping[i] =3D=3D crtc_id) res_mapping[i] =3D 0; } } @@ -666,23 +667,24 @@ static void _dpu_rm_clear_mapping(uint32_t *res_mappi= ng, int cnt, * dpu_rm_release - Given the encoder for the display chain, release any * HW blocks previously reserved for that use case. * @global_state: resources shared across multiple kms objects - * @enc: DRM Encoder handle + * @crtc: DRM CRTC handle * @return: 0 on Success otherwise -ERROR */ void dpu_rm_release(struct dpu_global_state *global_state, - struct drm_encoder *enc) + struct drm_crtc *crtc) { - _dpu_rm_clear_mapping(global_state->pingpong_to_enc_id, - ARRAY_SIZE(global_state->pingpong_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(global_state->mixer_to_enc_id, - ARRAY_SIZE(global_state->mixer_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(global_state->ctl_to_enc_id, - ARRAY_SIZE(global_state->ctl_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(global_state->dsc_to_enc_id, - ARRAY_SIZE(global_state->dsc_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(global_state->dspp_to_enc_id, - ARRAY_SIZE(global_state->dspp_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(&global_state->cdm_to_enc_id, 1, enc->base.id); + uint32_t crtc_id =3D crtc->base.id; + + _dpu_rm_clear_mapping(global_state->pingpong_to_crtc_id, + ARRAY_SIZE(global_state->pingpong_to_crtc_id), crtc_id); + _dpu_rm_clear_mapping(global_state->mixer_to_crtc_id, + ARRAY_SIZE(global_state->mixer_to_crtc_id), crtc_id); + _dpu_rm_clear_mapping(global_state->ctl_to_crtc_id, + ARRAY_SIZE(global_state->ctl_to_crtc_id), crtc_id); + _dpu_rm_clear_mapping(global_state->dsc_to_crtc_id, + ARRAY_SIZE(global_state->dsc_to_crtc_id), crtc_id); + _dpu_rm_clear_mapping(global_state->dspp_to_crtc_id, + ARRAY_SIZE(global_state->dspp_to_crtc_id), crtc_id); } =20 /** @@ -694,45 +696,36 @@ void dpu_rm_release(struct dpu_global_state *global_s= tate, * HW Reservations should be released via dpu_rm_release_hw. * @rm: DPU Resource Manager handle * @global_state: resources shared across multiple kms objects - * @enc: DRM Encoder handle - * @crtc_state: Proposed Atomic DRM CRTC State handle + * @crtc: DRM CRTC handle * @topology: Pointer to topology info for the display * @return: 0 on Success otherwise -ERROR */ int dpu_rm_reserve( struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *enc, - struct drm_crtc_state *crtc_state, + struct drm_crtc *crtc, struct msm_display_topology topology) { struct dpu_rm_requirements reqs; int ret; =20 - /* Check if this is just a page-flip */ - if (!drm_atomic_crtc_needs_modeset(crtc_state)) - return 0; - if (IS_ERR(global_state)) { DPU_ERROR("failed to global state\n"); return PTR_ERR(global_state); } =20 - DRM_DEBUG_KMS("reserving hw for enc %d crtc %d\n", - enc->base.id, crtc_state->crtc->base.id); + DRM_DEBUG_KMS("reserving hw for crtc %d\n", crtc->base.id); =20 - ret =3D _dpu_rm_populate_requirements(enc, &reqs, topology); + ret =3D _dpu_rm_populate_requirements(crtc, &reqs, topology); if (ret) { DPU_ERROR("failed to populate hw requirements\n"); return ret; } =20 - ret =3D _dpu_rm_make_reservation(rm, global_state, enc, &reqs); + ret =3D _dpu_rm_make_reservation(rm, global_state, crtc->base.id, &reqs); if (ret) DPU_ERROR("failed to reserve hw resources: %d\n", ret); =20 - - return ret; } =20 @@ -806,7 +799,7 @@ struct dpu_hw_sspp *dpu_rm_reserve_sspp(struct dpu_rm *= rm, /** * dpu_rm_release_all_sspp - Given the CRTC, release all SSPP * blocks previously reserved for that use case. - * @rm: DPU Resource Manager handle + * @global_state: resources shared across multiple kms objects * @crtc: DRM CRTC handle */ void dpu_rm_release_all_sspp(struct dpu_global_state *global_state, @@ -838,48 +831,49 @@ static char *dpu_hw_blk_type_name[] =3D { * assigned to this encoder * @rm: DPU Resource Manager handle * @global_state: resources shared across multiple kms objects - * @enc_id: encoder id requesting for allocation + * @crtc: DRM CRTC handle * @type: resource type to return data for * @blks: pointer to the array to be filled by HW resources * @blks_size: size of the @blks array */ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, - struct dpu_global_state *global_state, uint32_t enc_id, + struct dpu_global_state *global_state, struct drm_crtc *crtc, enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size) { + uint32_t crtc_id =3D crtc->base.id; struct dpu_hw_blk **hw_blks; - uint32_t *hw_to_enc_id; + uint32_t *hw_to_crtc_id; int i, num_blks, max_blks; =20 switch (type) { case DPU_HW_BLK_PINGPONG: hw_blks =3D rm->pingpong_blks; - hw_to_enc_id =3D global_state->pingpong_to_enc_id; + hw_to_crtc_id =3D global_state->pingpong_to_crtc_id; max_blks =3D ARRAY_SIZE(rm->pingpong_blks); break; case DPU_HW_BLK_LM: hw_blks =3D rm->mixer_blks; - hw_to_enc_id =3D global_state->mixer_to_enc_id; + hw_to_crtc_id =3D global_state->mixer_to_crtc_id; max_blks =3D ARRAY_SIZE(rm->mixer_blks); break; case DPU_HW_BLK_CTL: hw_blks =3D rm->ctl_blks; - hw_to_enc_id =3D global_state->ctl_to_enc_id; + hw_to_crtc_id =3D global_state->ctl_to_crtc_id; max_blks =3D ARRAY_SIZE(rm->ctl_blks); break; case DPU_HW_BLK_DSPP: hw_blks =3D rm->dspp_blks; - hw_to_enc_id =3D global_state->dspp_to_enc_id; + hw_to_crtc_id =3D global_state->dspp_to_crtc_id; max_blks =3D ARRAY_SIZE(rm->dspp_blks); break; case DPU_HW_BLK_DSC: hw_blks =3D rm->dsc_blks; - hw_to_enc_id =3D global_state->dsc_to_enc_id; + hw_to_crtc_id =3D global_state->dsc_to_crtc_id; max_blks =3D ARRAY_SIZE(rm->dsc_blks); break; case DPU_HW_BLK_CDM: hw_blks =3D &rm->cdm_blk; - hw_to_enc_id =3D &global_state->cdm_to_enc_id; + hw_to_crtc_id =3D &global_state->cdm_to_crtc_id; max_blks =3D 1; break; default: @@ -889,17 +883,17 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, =20 num_blks =3D 0; for (i =3D 0; i < max_blks; i++) { - if (hw_to_enc_id[i] !=3D enc_id) + if (hw_to_crtc_id[i] !=3D crtc_id) continue; =20 if (num_blks =3D=3D blks_size) { - DPU_ERROR("More than %d %s assigned to enc %d\n", - blks_size, dpu_hw_blk_type_name[type], enc_id); + DPU_ERROR("More than %d resources assigned to crtc %d\n", + blks_size, crtc_id); break; } if (!hw_blks[i]) { - DPU_ERROR("%s unavailable to assign to enc %d\n", - dpu_hw_blk_type_name[type], enc_id); + DPU_ERROR("%s unavailable to assign to crtc %d\n", + dpu_hw_blk_type_name[type], crtc_id); break; } blks[num_blks++] =3D hw_blks[i]; @@ -934,38 +928,38 @@ void dpu_rm_print_state(struct drm_printer *p, =20 drm_puts(p, "resource mapping:\n"); drm_puts(p, "\tpingpong=3D"); - for (i =3D 0; i < ARRAY_SIZE(global_state->pingpong_to_enc_id); i++) + for (i =3D 0; i < ARRAY_SIZE(global_state->pingpong_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->pingpong_blks[i], - global_state->pingpong_to_enc_id[i]); + global_state->pingpong_to_crtc_id[i]); drm_puts(p, "\n"); =20 drm_puts(p, "\tmixer=3D"); - for (i =3D 0; i < ARRAY_SIZE(global_state->mixer_to_enc_id); i++) + for (i =3D 0; i < ARRAY_SIZE(global_state->mixer_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->mixer_blks[i], - global_state->mixer_to_enc_id[i]); + global_state->mixer_to_crtc_id[i]); drm_puts(p, "\n"); =20 drm_puts(p, "\tctl=3D"); - for (i =3D 0; i < ARRAY_SIZE(global_state->ctl_to_enc_id); i++) + for (i =3D 0; i < ARRAY_SIZE(global_state->ctl_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->ctl_blks[i], - global_state->ctl_to_enc_id[i]); + global_state->ctl_to_crtc_id[i]); drm_puts(p, "\n"); =20 drm_puts(p, "\tdspp=3D"); - for (i =3D 0; i < ARRAY_SIZE(global_state->dspp_to_enc_id); i++) + for (i =3D 0; i < ARRAY_SIZE(global_state->dspp_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->dspp_blks[i], - global_state->dspp_to_enc_id[i]); + global_state->dspp_to_crtc_id[i]); drm_puts(p, "\n"); =20 drm_puts(p, "\tdsc=3D"); - for (i =3D 0; i < ARRAY_SIZE(global_state->dsc_to_enc_id); i++) + for (i =3D 0; i < ARRAY_SIZE(global_state->dsc_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->dsc_blks[i], - global_state->dsc_to_enc_id[i]); + global_state->dsc_to_crtc_id[i]); drm_puts(p, "\n"); =20 drm_puts(p, "\tcdm=3D"); dpu_rm_print_state_helper(p, rm->cdm_blk, - global_state->cdm_to_enc_id); + global_state->cdm_to_crtc_id); drm_puts(p, "\n"); =20 drm_puts(p, "\tsspp=3D"); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.h index 227a486b2b83a..ba2d9bc1cc687 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -66,14 +66,33 @@ int dpu_rm_init(struct drm_device *dev, const struct msm_mdss_data *mdss_data, void __iomem *mmio); =20 -int dpu_rm_reserve(struct dpu_rm *rm, +/** + * dpu_rm_reserve - Given a CRTC->Encoder->Connector display chain, analyze + * the use connections and user requirements, specified through related + * topology control properties, and reserve hardware blocks to that + * display chain. + * HW blocks can then be accessed through dpu_rm_get_* functions. + * HW Reservations should be released via dpu_rm_release_hw. + * @rm: DPU Resource Manager handle + * @crtc: DRM CRTC handle + * @topology: Pointer to topology info for the display + * @Return: 0 on Success otherwise -ERROR + */ +int dpu_rm_reserve( + struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *drm_enc, - struct drm_crtc_state *crtc_state, + struct drm_crtc *crtc, struct msm_display_topology topology); =20 +/** + * dpu_rm_release - Given the crtc for the display chain, release any + * HW blocks previously reserved for that use case. + * @rm: DPU Resource Manager handle + * @crtc: DRM CRTC handle + * @Return: 0 on Success otherwise -ERROR + */ void dpu_rm_release(struct dpu_global_state *global_state, - struct drm_encoder *enc); + struct drm_crtc *crtc); =20 struct dpu_hw_sspp *dpu_rm_reserve_sspp(struct dpu_rm *rm, struct dpu_global_state *global_state, @@ -83,8 +102,11 @@ struct dpu_hw_sspp *dpu_rm_reserve_sspp(struct dpu_rm *= rm, void dpu_rm_release_all_sspp(struct dpu_global_state *global_state, struct drm_crtc *crtc); =20 +/** + * Get hw resources of the given type that are assigned to this crtc. + */ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, - struct dpu_global_state *global_state, uint32_t enc_id, + struct dpu_global_state *global_state, struct drm_crtc *crtc, enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size); =20 void dpu_rm_print_state(struct drm_printer *p, --=20 2.34.1 From nobody Thu Dec 18 20:22:07 2025 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C295217737 for ; Thu, 19 Dec 2024 07:50:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594621; cv=none; b=MVvK3g2OuJ8qwosOJ1yLD/az9nX8xUdnASsfAn0kfdfRmVSMcdnRF4t/e4dmBhNmASYg2dNDU23c6hpUSGlnteYIUJiD5ZstxCzI/BlP9mlXT+0KLK5Jf63L1VSUA0x8vlX7F6uNVqs6bif5wavJnS342Ryqp0ZE2KBdl/tZjIM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594621; c=relaxed/simple; bh=1P83PCfCS2lfs0H8yVBLl5bdtpLcjuxoQO6Bi/oLzx4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CghWI1zNT0WNTfsHs4e9kGqeZHKc9d6+89t50wW7EJUSavLGGFb8cp6X3cfcoCctLnO/M90BLzga6WAhIWa4Y3CcUMj14Cy06iBiP5q93tUPsYvbrYT+XqfGxi1EktC5IFvlpMQ9likROofE7bz4KNLMrEDB14p0uRstNeQg8e4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=UCnrFyWz; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="UCnrFyWz" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-2156e078563so4358005ad.2 for ; Wed, 18 Dec 2024 23:50:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1734594618; x=1735199418; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Lli+5tH2X+U8aWpWoMo1klotVHUOV8UtSv6HuUwkGTQ=; b=UCnrFyWzmw5WQJaVvripIxbD6aQc8/oomCgvzskigqDeDpPYkBFO3OiEaG6nfA9Ntj t34ZM3jB9pUJ8BqXvySuPmxsu9wn+aDQ4aDtMR7Z0dhbU7CyoFgC8SufAiTjIuurYVry Ak7AV1TV2itw6SkEofxoaj4QpHEcOQrv58Q0yMrtCWS17kTUQ0N026K5sgbUyl9bop9y zp++RoFQjNarP0FMwzYR5In1zhar0B3xctEz50p4lYKZ94SjCxk7oTYHzBcFLKFkeGvS 2la/bI5mVbMOjrnzcJ57cfi2TaM3IZG+djXUIG0WNrR9chofLGkKHZXqoJHuNEnEuM04 /I2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734594618; x=1735199418; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lli+5tH2X+U8aWpWoMo1klotVHUOV8UtSv6HuUwkGTQ=; b=jOz+UVgf0kDi71NsC+XYlXYa15dhdMi4NFwbk0C9spX9sNnIFffiEjUDRpDTqS7Qck C+nBkUOnEH7RBAkUaZQkUhhtUWXFT+p6jUHl5R0XIAdbfBQrIx36kAjyyIzR/6Z00nPO NSS4qbZj4Sq0zMfQwiDSGgTYN4e2n93e5hCPAkgXhEljHFMepm6SkTl11ls2wCdvb9gS O9/Ao3El2jmrbHrLFNOKUSm2ia0rLE8haqNkr55QHL1KQOJXQc3Ydwvmr4ORzJjSdkEz CgV9gSOpDbfZX+8Q3HfSWQ1JmUZG8hpnWLUoazr/Y80amnboUHrdB9k/IRQmgblh2NSO Wytw== X-Forwarded-Encrypted: i=1; AJvYcCX5su/eRbKF6D2Eog7ef1+ruqnKjkCJ6PPMBMi2PYpZv67KyHS+g6QzOskmkJRVxLu0aoD5tOzreiNdx98=@vger.kernel.org X-Gm-Message-State: AOJu0YzIgoxD0Qtr+AKkCvN963RFOj533EgXXU+vSpSiaorkNFrTU4gz EPcdlM7/AuzybmVl53QECsaU4lJ2HDmxAjOx9In/uJH8yRcwpyqnhkMZ5y5dZRk= X-Gm-Gg: ASbGnctWxJh5Ckcmkb2CgqWisvdyKhpz6iFi4litJ/uHLQ2jW52hqWWVFj7ViJYRKlM 3fWTp84nxa9S9XJ+bWugU8UootwOxaku2G0AyynzcOhLa9maILgtWAMPFdXn5pH3CjVpOKo+qOd gOVVsJdU8lOKBTbha3M4JU60L2xzJT6AbiiTFfZJSKVPnk3c/63p2jSfAd78fQn+rm2ERWxX/oJ zuUBDiKTLUofkAeiI5lgkmbofxzU/5cuGYupCSps5WEvAeU92GUvw== X-Google-Smtp-Source: AGHT+IEQSTniNO//F/A9g+Zys4CYNcQ3vYbwx5b3wwx5Lzn1nZuhKfyiY+QWxw8KJsSb8lhBnthlDw== X-Received: by 2002:a17:902:e881:b0:215:96bc:b670 with SMTP id d9443c01a7336-218d7216b9emr76595075ad.18.1734594618593; Wed, 18 Dec 2024 23:50:18 -0800 (PST) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc97432dsm6784445ad.110.2024.12.18.23.50.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2024 23:50:18 -0800 (PST) From: Jun Nie Date: Thu, 19 Dec 2024 15:49:25 +0800 Subject: [PATCH v3 07/15] drm/msm/dpu: bind correct pingpong for quad pipe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-7-92c7c0a228e3@linaro.org> References: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> In-Reply-To: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734594568; l=1925; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=1P83PCfCS2lfs0H8yVBLl5bdtpLcjuxoQO6Bi/oLzx4=; b=0illn173nHN5yDx+5A36VQEy2DoORmhhY2O/tudk2pDLuA4TxygTKgNARKLN3M3jphyKuTD7U z62ZZKZDsBLCufkl1g9MZTldnP3NvxVSY/YwSMcYS3pe0CCTv0WWqUN X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= There are 2 interfaces and 4 pingpong in quad pipe. Map the 2nd interface to 3rd PP instead of the 2nd PP. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index fd32ef468d5f9..96d06db3e4be5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1220,7 +1220,8 @@ static void dpu_encoder_virt_atomic_mode_set(struct d= rm_encoder *drm_enc, struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC]; - int num_ctl, num_pp, num_dsc; + struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; + int num_lm, num_ctl, num_pp, num_dsc, num_pp_per_intf; unsigned int dsc_mask =3D 0; int i; =20 @@ -1275,11 +1276,21 @@ static void dpu_encoder_virt_atomic_mode_set(struct= drm_encoder *drm_enc, dpu_enc->cur_master->hw_cdm =3D hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL; } =20 + num_lm =3D dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, + drm_enc->crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); + + + /* + * There may be 4 PP and 2 INTF for quad pipe case, so INTF is not + * mapped to PP 1:1. Let's calculate the stride with pipe/INTF + */ + num_pp_per_intf =3D num_lm / dpu_enc->num_phys_encs; + for (i =3D 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys =3D dpu_enc->phys_encs[i]; struct dpu_hw_ctl *ctl0 =3D to_dpu_hw_ctl(hw_ctl[0]); =20 - phys->hw_pp =3D dpu_enc->hw_pp[i]; + phys->hw_pp =3D dpu_enc->hw_pp[num_pp_per_intf * i]; if (!phys->hw_pp) { DPU_ERROR_ENC(dpu_enc, "no pp block assigned at idx: %d\n", i); --=20 2.34.1 From nobody Thu Dec 18 20:22:07 2025 Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C835217737 for ; Thu, 19 Dec 2024 07:50:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594627; cv=none; b=U4WSVxUAQes2vSVgSg2FmsipTSeumlS/Z4ajBcISgJ7GXcGOKtB0NLpzK+bkbfwzh6J2LWYvgAJs1D1ZZ9FgjC/9HsQSWEsgO1t2SP6dwTOAfOkcpUk1OB0ou+f9T7MAFJ9UI/4BQIGg8s5bnJqS0IheVK8ZVo+JnrNsWMLgfZ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594627; c=relaxed/simple; bh=4pyUFh744sHDJvsbdJzxiAFnDWjxYhxne+lkj5Hq3Vs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CJ4L9JH0T2LF3s0pBnWaSOx6VisrCNOGmXYZNnrctza0SxBISEfHSL0Txi2GrTYCzwg3TKIgEr+HevDvYzDWKpFrLv/+Ry+ESIErag0eFytuvkoXaB4fS0pZXgHV5TEGAiAfiKCsofUBgnZYjZVkDIK3zr8dTNlH6fIzOj8+SVY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=zlGGRL0D; arc=none smtp.client-ip=209.85.210.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="zlGGRL0D" Received: by mail-pf1-f176.google.com with SMTP id d2e1a72fcca58-725f2f79ed9so401040b3a.2 for ; Wed, 18 Dec 2024 23:50:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1734594624; x=1735199424; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=5N2dfgd64p0DEPdhl9OFTPzqRUIYGuvPDldjhaIkvSI=; b=zlGGRL0Dj0hiVBFIzi3K0I374cxDDA5559lUxte+YweEMnjui3cPXk6V8gPoK+HSTT VbG8DC1rpRC/JUk6zbhTeYBGIWO5rO9nYfVUWOQrZs948/GEAQpXyGb4R6MinuHakWHc F8mY1Dsyek+GhpEDAJ5wjlS4/FDSd8o7nsJQ7ZZpIGRiwrd7ta00fPcnXqCvqKppCqwg 273weIjnMDn6ai8Wj0AwbN0TGs8cAQI9DPBgWGAo5AxViax15Yx2voNvK9sQlUxPSnu4 xk7SAfSZRpeQnQ9UgHKh7IyScmENWPkeStqB0HgKU6vLsGsgBrqmmewZQJyMWcPFpaA0 5DqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734594624; x=1735199424; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5N2dfgd64p0DEPdhl9OFTPzqRUIYGuvPDldjhaIkvSI=; b=Iv6o6Gec8r2BrgBCeoIvZCkrS8Mkn3J/7sHoad2DS/5Ps+aK8XBaWZh4L5WXB9wyFE Ia4IRy4pEm2JiIvC/8vMeC9U+Q6QbUkYGLzQp660fSj0B9DFqAROpj2//4DTS16x1ejK XVscencEdZJArRhLxCAf3YFGPSOqqKXAX4TGIQ3vbmzrXbdFNtp7yezQIsNEzfbQSABv j+QUUeqO80V6djl9Pq8rtEF8XqsJ9WKnTgIcHgBRX4k5bKCI636Y8Z9/64fpu6EaGD7d V6ioBoh+N2SUgia/WqwijGrsfL519Yagr3YNMtHAk7kaAifUMp+pXnWKhtqFrXAbpYSb l1RA== X-Forwarded-Encrypted: i=1; AJvYcCUgOEKvFDzzKPkx1Fo94ztltuJ4ufCHBLDoxeWT4KndrfK++pwloigkbi9EO5xlRddCW8DGQCiKHIcWDHU=@vger.kernel.org X-Gm-Message-State: AOJu0YwIy9WkSvymVYHkUyBQKKe+N4AyAxPPKwYSPbITGVeVYrTa2vgO Q0h6VVPj5t9SA+DuqzkhdhhY9MCoMeHG7SNuXfy3f2ycy91zDJaviVcqLDMZxN0= X-Gm-Gg: ASbGncuxtmknX4IpOmDkGKcENy2ueO3xDZ++hl0JdFp7BT+Lgq0BSnPU9P/lZjRLK0R LdfX0/31bkVIcwIlXRh/zj42Bt5YbOPXH80VV5mhJuOpGH6c7ny+Uf7y6uMSh8iGZkn6n1lVUGv KhTUF/TsFhhhqNDqiUoVjMWRortx05PHHFmaNt17yBPvbMg/xDFIJH6xrCpNEzRgV8v0+p3Vx4Z MWvkdGNcLvaOfUxIOox+VFuaEcl2X6gbzmGvieiGfsiAm1rBy4CsA== X-Google-Smtp-Source: AGHT+IFJDv2dpGa6yqwPKTMIPyJa8ryu7xIRojO3KAN24TMOhbZFGlWjR6cZtD/LKF5xiFZwx+LyCA== X-Received: by 2002:a17:902:d2ca:b0:20b:6d82:acb with SMTP id d9443c01a7336-219d963ba5fmr36448065ad.23.1734594624575; Wed, 18 Dec 2024 23:50:24 -0800 (PST) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc97432dsm6784445ad.110.2024.12.18.23.50.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2024 23:50:24 -0800 (PST) From: Jun Nie Date: Thu, 19 Dec 2024 15:49:26 +0800 Subject: [PATCH v3 08/15] drm/msm/dpu: handle pipes as array Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-8-92c7c0a228e3@linaro.org> References: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> In-Reply-To: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734594568; l=16697; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=4pyUFh744sHDJvsbdJzxiAFnDWjxYhxne+lkj5Hq3Vs=; b=+zGF4jGNmmOuKegdzw4ZClk/JbmB8OOKCjQmXsHO3Nd4Ne/f8+fBKrk+qqiOsIJn5x4GNtz/7 oAu7L0rS+CnBI/DoX0QsPV0QxGcKpt+2xj8XAKrPxoWi1CRxFJIiJkD X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Store pipes in array with removing dedicated r_pipe. There are 2 pipes in a drm plane at most currently. While 4 pipes are needed for new usage case. This change generalize the handling to pipe pair and ease handling to another pipe pair later. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 35 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 170 +++++++++++++++++---------= ---- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 12 +-- 3 files changed, 113 insertions(+), 104 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 41c9d3e3e3c7c..a0284b1425b1f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -442,7 +442,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, const struct msm_format *format; struct dpu_hw_ctl *ctl =3D mixer->lm_ctl; =20 - uint32_t lm_idx; + uint32_t lm_idx, i; bool bg_alpha_enable =3D false; DECLARE_BITMAP(fetch_active, SSPP_MAX); =20 @@ -463,20 +463,15 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_cr= tc *crtc, if (pstate->stage =3D=3D DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable =3D true; =20 - set_bit(pstate->pipe.sspp->idx, fetch_active); - _dpu_crtc_blend_setup_pipe(crtc, plane, - mixer, cstate->num_mixers, - pstate->stage, - format, fb ? fb->modifier : 0, - &pstate->pipe, 0, stage_cfg); - - if (pstate->r_pipe.sspp) { - set_bit(pstate->r_pipe.sspp->idx, fetch_active); + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (!pstate->pipe[i].sspp) + continue; + set_bit(pstate->pipe[i].sspp->idx, fetch_active); _dpu_crtc_blend_setup_pipe(crtc, plane, mixer, cstate->num_mixers, pstate->stage, format, fb ? fb->modifier : 0, - &pstate->r_pipe, 1, stage_cfg); + &pstate->pipe[i], i, stage_cfg); } =20 /* blend config update */ @@ -1440,15 +1435,15 @@ static int _dpu_debugfs_status_show(struct seq_file= *s, void *data) seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n", state->crtc_x, state->crtc_y, state->crtc_w, state->crtc_h); - seq_printf(s, "\tsspp[0]:%s\n", - pstate->pipe.sspp->cap->name); - seq_printf(s, "\tmultirect[0]: mode: %d index: %d\n", - pstate->pipe.multirect_mode, pstate->pipe.multirect_index); - if (pstate->r_pipe.sspp) { - seq_printf(s, "\tsspp[1]:%s\n", - pstate->r_pipe.sspp->cap->name); - seq_printf(s, "\tmultirect[1]: mode: %d index: %d\n", - pstate->r_pipe.multirect_mode, pstate->r_pipe.multirect_index); + + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (pstate->pipe[i].sspp) { + seq_printf(s, "\tsspp[%d]:%s\n", + i, pstate->pipe[i].sspp->cap->name); + seq_printf(s, "\tmultirect[%d]: mode: %d index: %d\n", + i, pstate->pipe[i].multirect_mode, + pstate->pipe[i].multirect_index); + } } =20 seq_puts(s, "\n"); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 098abc2c0003c..aaf934ec96be5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -619,6 +619,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdp= u, struct msm_drm_private *priv =3D plane->dev->dev_private; struct dpu_plane_state *pstate =3D to_dpu_plane_state(plane->state); u32 fill_color =3D (color & 0xFFFFFF) | ((alpha & 0xFF) << 24); + int i; =20 DPU_DEBUG_PLANE(pdpu, "\n"); =20 @@ -632,12 +633,12 @@ static void _dpu_plane_color_fill(struct dpu_plane *p= dpu, return; =20 /* update sspp */ - _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_r= ect, - fill_color, fmt); - - if (pstate->r_pipe.sspp) - _dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg.= dst_rect, - fill_color, fmt); + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (pstate->pipe[i].sspp) + _dpu_plane_color_fill_pipe(pstate, &pstate->pipe[i], + &pstate->pipe_cfg[i].dst_rect, + fill_color, fmt); + } } =20 static int dpu_plane_prepare_fb(struct drm_plane *plane, @@ -799,8 +800,8 @@ static int dpu_plane_atomic_check_nosspp(struct drm_pla= ne *plane, struct dpu_kms *kms =3D _dpu_plane_get_kms(&pdpu->base); u64 max_mdp_clk_rate =3D kms->perf.max_core_clk_rate; struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; + struct dpu_sw_pipe_cfg *pipe_cfg; + struct dpu_sw_pipe_cfg *r_pipe_cfg; struct drm_rect fb_rect =3D { 0 }; uint32_t max_linewidth; =20 @@ -825,6 +826,9 @@ static int dpu_plane_atomic_check_nosspp(struct drm_pla= ne *plane, return -EINVAL; } =20 + /* move the assignment here, to ease handling to another pairs later */ + pipe_cfg =3D &pstate->pipe_cfg[0]; + r_pipe_cfg =3D &pstate->pipe_cfg[1]; /* state->src is 16.16, src_rect is not */ drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); =20 @@ -921,11 +925,11 @@ static int dpu_plane_atomic_check_sspp(struct drm_pla= ne *plane, drm_atomic_get_new_plane_state(state, plane); struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); - struct dpu_sw_pipe *pipe =3D &pstate->pipe; - struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; const struct msm_format *fmt; - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; + struct dpu_sw_pipe *pipe =3D &pstate->pipe[0]; + struct dpu_sw_pipe *r_pipe =3D &pstate->pipe[1]; + struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg[0]; + struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->pipe_cfg[1]; uint32_t supported_rotations; const struct dpu_sspp_cfg *pipe_hw_caps; const struct dpu_sspp_sub_blks *sblk; @@ -1010,10 +1014,10 @@ static int dpu_plane_atomic_check(struct drm_plane = *plane, struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); - struct dpu_sw_pipe *pipe =3D &pstate->pipe; - struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; + struct dpu_sw_pipe *pipe =3D &pstate->pipe[0]; + struct dpu_sw_pipe *r_pipe =3D &pstate->pipe[1]; + struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg[0]; + struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->pipe_cfg[1]; const struct drm_crtc_state *crtc_state =3D NULL; uint32_t max_linewidth =3D dpu_kms->catalog->caps->max_linewidth; =20 @@ -1057,7 +1061,7 @@ static int dpu_plane_virtual_atomic_check(struct drm_= plane *plane, drm_atomic_get_old_plane_state(state, plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(plane_state); struct drm_crtc_state *crtc_state; - int ret; + int ret, i; =20 if (plane_state->crtc) crtc_state =3D drm_atomic_get_new_crtc_state(state, @@ -1072,8 +1076,8 @@ static int dpu_plane_virtual_atomic_check(struct drm_= plane *plane, * resources are freed by dpu_crtc_assign_plane_resources(), * but clean them here. */ - pstate->pipe.sspp =3D NULL; - pstate->r_pipe.sspp =3D NULL; + for (i =3D 0; i < PIPES_PER_STAGE; i++) + pstate->pipe[i].sspp =3D NULL; =20 return 0; } @@ -1110,19 +1114,22 @@ static int dpu_plane_virtual_assign_resources(struc= t drm_crtc *crtc, struct dpu_sw_pipe_cfg *pipe_cfg; struct dpu_sw_pipe_cfg *r_pipe_cfg; const struct msm_format *fmt; + int i; =20 if (plane_state->crtc) crtc_state =3D drm_atomic_get_new_crtc_state(state, plane_state->crtc); =20 pstate =3D to_dpu_plane_state(plane_state); - pipe =3D &pstate->pipe; - r_pipe =3D &pstate->r_pipe; - pipe_cfg =3D &pstate->pipe_cfg; - r_pipe_cfg =3D &pstate->r_pipe_cfg; =20 - pipe->sspp =3D NULL; - r_pipe->sspp =3D NULL; + /* TODO: loop below code for another pair later */ + pipe =3D &pstate->pipe[0]; + r_pipe =3D &pstate->pipe[1]; + pipe_cfg =3D &pstate->pipe_cfg[0]; + r_pipe_cfg =3D &pstate->pipe_cfg[1]; + + for (i =3D 0; i < PIPES_PER_STAGE; i++) + pstate->pipe[i].sspp =3D NULL; =20 if (!plane_state->fb) return -EINVAL; @@ -1212,6 +1219,7 @@ void dpu_plane_flush(struct drm_plane *plane) { struct dpu_plane *pdpu; struct dpu_plane_state *pstate; + int i; =20 if (!plane || !plane->state) { DPU_ERROR("invalid plane\n"); @@ -1232,8 +1240,8 @@ void dpu_plane_flush(struct drm_plane *plane) /* force 100% alpha */ _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); else { - dpu_plane_flush_csc(pdpu, &pstate->pipe); - dpu_plane_flush_csc(pdpu, &pstate->r_pipe); + for (i =3D 0; i < PIPES_PER_STAGE; i++) + dpu_plane_flush_csc(pdpu, &pstate->pipe[i]); } =20 /* flag h/w flush complete */ @@ -1334,15 +1342,19 @@ static void dpu_plane_sspp_atomic_update(struct drm= _plane *plane, struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct drm_plane_state *state =3D plane->state; struct dpu_plane_state *pstate =3D to_dpu_plane_state(state); - struct dpu_sw_pipe *pipe =3D &pstate->pipe; - struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; struct drm_crtc *crtc =3D state->crtc; struct drm_framebuffer *fb =3D state->fb; bool is_rt_pipe; const struct msm_format *fmt =3D msm_framebuffer_format(fb); - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; + struct dpu_hw_fmt_layout layout; + int ret, i; + + ret =3D dpu_format_populate_plane_sizes(fb, &layout); + if (ret) { + DPU_ERROR_PLANE(pdpu, "failed to get format plane sizes, %d\n", ret); + return; + } =20 pstate->pending =3D true; =20 @@ -1357,12 +1369,12 @@ static void dpu_plane_sspp_atomic_update(struct drm= _plane *plane, crtc->base.id, DRM_RECT_ARG(&state->dst), &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt)); =20 - dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt, - drm_mode_vrefresh(&crtc->mode), - &pstate->layout); - - if (r_pipe->sspp) { - dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt, + /* move the assignment here, to ease handling to another pairs later */ + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (!pstate->pipe[i].sspp) + continue; + dpu_plane_sspp_update_pipe(plane, &pstate->pipe[i], + &pstate->pipe_cfg[i], fmt, drm_mode_vrefresh(&crtc->mode), &pstate->layout); } @@ -1370,15 +1382,17 @@ static void dpu_plane_sspp_atomic_update(struct drm= _plane *plane, if (pstate->needs_qos_remap) pstate->needs_qos_remap =3D false; =20 - pstate->plane_fetch_bw =3D _dpu_plane_calc_bw(pdpu->catalog, fmt, - &crtc->mode, pipe_cfg); - - pstate->plane_clk =3D _dpu_plane_calc_clk(&crtc->mode, pipe_cfg); - - if (r_pipe->sspp) { - pstate->plane_fetch_bw +=3D _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc= ->mode, r_pipe_cfg); + pstate->plane_fetch_bw =3D 0; + pstate->plane_clk =3D 0; + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (!pstate->pipe[i].sspp) + continue; + pstate->plane_fetch_bw +=3D _dpu_plane_calc_bw(pdpu->catalog, fmt, + &crtc->mode, &pstate->pipe_cfg[i]); =20 - pstate->plane_clk =3D max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->= mode, r_pipe_cfg)); + pstate->plane_clk =3D max(pstate->plane_clk, + _dpu_plane_calc_clk(&crtc->mode, + &pstate->pipe_cfg[i])); } } =20 @@ -1386,17 +1400,24 @@ static void _dpu_plane_atomic_disable(struct drm_pl= ane *plane) { struct drm_plane_state *state =3D plane->state; struct dpu_plane_state *pstate =3D to_dpu_plane_state(state); - struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; + struct dpu_sw_pipe *pipe; + int i; =20 - trace_dpu_plane_disable(DRMID(plane), false, - pstate->pipe.multirect_mode); + for (i =3D 0; i < PIPES_PER_STAGE; i +=3D 1) { + pipe =3D &pstate->pipe[i]; + if (!pipe->sspp) + continue; =20 - if (r_pipe->sspp) { - r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + trace_dpu_plane_disable(DRMID(plane), false, + pstate->pipe[i].multirect_mode); =20 - if (r_pipe->sspp->ops.setup_multirect) - r_pipe->sspp->ops.setup_multirect(r_pipe); + if (pipe->sspp && i =3D=3D 1) { + pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + + if (pipe->sspp->ops.setup_multirect) + pipe->sspp->ops.setup_multirect(pipe); + } } =20 pstate->pending =3D true; @@ -1491,31 +1512,26 @@ static void dpu_plane_atomic_print_state(struct drm= _printer *p, const struct drm_plane_state *state) { const struct dpu_plane_state *pstate =3D to_dpu_plane_state(state); - const struct dpu_sw_pipe *pipe =3D &pstate->pipe; - const struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - const struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; - const struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; + const struct dpu_sw_pipe *pipe; + const struct dpu_sw_pipe_cfg *pipe_cfg; + int i; =20 drm_printf(p, "\tstage=3D%d\n", pstate->stage); =20 - if (pipe->sspp) { - drm_printf(p, "\tsspp[0]=3D%s\n", pipe->sspp->cap->name); - drm_printf(p, "\tmultirect_mode[0]=3D%s\n", + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + pipe =3D &pstate->pipe[i]; + if (!pipe->sspp) + continue; + pipe_cfg =3D &pstate->pipe_cfg[i]; + drm_printf(p, "\tsspp[%d]=3D%s\n", i, pipe->sspp->cap->name); + drm_printf(p, "\tmultirect_mode[%d]=3D%s\n", i, dpu_get_multirect_mode(pipe->multirect_mode)); - drm_printf(p, "\tmultirect_index[0]=3D%s\n", + drm_printf(p, "\tmultirect_index[%d]=3D%s\n", i, dpu_get_multirect_index(pipe->multirect_index)); - drm_printf(p, "\tsrc[0]=3D" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->s= rc_rect)); - drm_printf(p, "\tdst[0]=3D" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->d= st_rect)); - } - - if (r_pipe->sspp) { - drm_printf(p, "\tsspp[1]=3D%s\n", r_pipe->sspp->cap->name); - drm_printf(p, "\tmultirect_mode[1]=3D%s\n", - dpu_get_multirect_mode(r_pipe->multirect_mode)); - drm_printf(p, "\tmultirect_index[1]=3D%s\n", - dpu_get_multirect_index(r_pipe->multirect_index)); - drm_printf(p, "\tsrc[1]=3D" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg-= >src_rect)); - drm_printf(p, "\tdst[1]=3D" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg-= >dst_rect)); + drm_printf(p, "\tsrc[%d]=3D" DRM_RECT_FMT "\n", i, + DRM_RECT_ARG(&pipe_cfg->src_rect)); + drm_printf(p, "\tdst[%d]=3D" DRM_RECT_FMT "\n", i, + DRM_RECT_ARG(&pipe_cfg->dst_rect)); } } =20 @@ -1553,14 +1569,16 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane = *plane, bool enable) struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(plane->state); struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); + int i; =20 if (!pdpu->is_rt_pipe) return; =20 pm_runtime_get_sync(&dpu_kms->pdev->dev); - _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable); - if (pstate->r_pipe.sspp) - _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable); + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (pstate->pipe[i].sspp) + _dpu_plane_set_qos_ctrl(plane, &pstate->pipe[i], enable); + } pm_runtime_put_sync(&dpu_kms->pdev->dev); } #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.h index acd5725175cdd..052fd046e8463 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -18,10 +18,8 @@ * struct dpu_plane_state: Define dpu extension of drm plane state object * @base: base drm plane state object * @aspace: pointer to address space for input/output buffers - * @pipe: software pipe description - * @r_pipe: software pipe description of the second pipe - * @pipe_cfg: software pipe configuration - * @r_pipe_cfg: software pipe configuration for the second pipe + * @pipe: software pipe description array + * @pipe_cfg: software pipe configuration array * @stage: assigned by crtc blender * @needs_qos_remap: qos remap settings need to be updated * @multirect_index: index of the rectangle of SSPP @@ -35,10 +33,8 @@ struct dpu_plane_state { struct drm_plane_state base; struct msm_gem_address_space *aspace; - struct dpu_sw_pipe pipe; - struct dpu_sw_pipe r_pipe; - struct dpu_sw_pipe_cfg pipe_cfg; - struct dpu_sw_pipe_cfg r_pipe_cfg; + struct dpu_sw_pipe pipe[PIPES_PER_STAGE]; + struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_STAGE]; enum dpu_stage stage; bool needs_qos_remap; bool pending; --=20 2.34.1 From nobody Thu Dec 18 20:22:07 2025 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 837D0218854 for ; Thu, 19 Dec 2024 07:50:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594633; cv=none; b=Ro7kobh2QHaNicasraiXIAbiTo3NiKFhLqi0uXjWrYxb4sjZurB61JYsBLOUofp0Mb9/9/vixoluLGwj6YE0KCOe53zVGPaM7cQij+8RRqGTBlg+LI9unDdEVhB9VCe+hKNBinzj1WZHd3zQtyCEqtkD9fohC1Cq4oXLTFdr3U0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594633; c=relaxed/simple; bh=lJNk0O7zKbjtRBUPK/q7deOXG2gRF1mUYLxIqB8dl4g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MakRqfHOORZyOB3Kx+DaJ5lKxahaJEbuWVfAc04aJrvsY5Ls4/L3i31gKO9kA0JvTWPaTFCWF2WVmqee/JaWzswOOWO5vHpYKffNQnAc4zZq6OVUYfosbzviL2N3BcwxWp7ZugPNo/t+LpIYXLhbX+xxPAcpm77ct4DmxF22Gd4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=G+92ZR2u; arc=none smtp.client-ip=209.85.214.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="G+92ZR2u" Received: by mail-pl1-f175.google.com with SMTP id d9443c01a7336-21683192bf9so4896025ad.3 for ; Wed, 18 Dec 2024 23:50:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1734594631; x=1735199431; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=0y4Yjsb8dzPb2yoZQl9aqLWS59hh0GNRfXMNjyDZkkU=; b=G+92ZR2u9MYDKXXK8jfNiQqYbMh6RR9dvvDDey8pF23jGbOfzaMz+cXz3/Br47Mfpe H9FBk551xwP9KKm94aAsQ1rwxQCb+BGbaKCmScgVawnrCGo4lW6yJUE+Js3WUU8E/TCz KjJU3MQBteu4TMhLYEwdU1HGHyiCa+ypSiyei1dDOZelsoaXgnim+lwL1ZiE4zBRwlar yh2MfUFn9YJZCuaurdBSOOiO370rVJW+bk+ZLovmOKfDGR/8Vzp2dHj3AQnODUUG6mXW KuHdcI6e2XZchPVGRsIOGna0qcUHzNmfK/T6tlE4Qggl51C5gj3351lEvFRzznZNeTtJ T/Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734594631; x=1735199431; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0y4Yjsb8dzPb2yoZQl9aqLWS59hh0GNRfXMNjyDZkkU=; b=RsQNgFpJquvIPWWl2yQ9phxyEZYRFHBVkRAkh4kujWm1MPg90XY+sTkresBonNzuzA iJ7RMhE4wS3hfWywe25K8YDInB5bB9tV+2TryndC3cOhAQKS41F8t2PzwKhiUi2Ex6yH 63loS8LO9Vq3vG6n/lYW1ndKJGjySTDKL2QsUI0/ekijRzOJMRV6KyZXUK2c5hzEqPAs qzeAezJyl8hsMmpP47ahiOXlNSP5KY78UHAgm0CLm5HcSx6v5hUPs1ubQ73kIkSO/H6c lzr34gAlIzFHua+6DzBvh/c4AxTQ4q0ufdgrAkmaPS+d01HI+a71TQRwmXSJJiW8AA/t 8dXA== X-Forwarded-Encrypted: i=1; AJvYcCXOcoNC2vmSxuaVgx8f32wbNOuIXIGz3MZgQBrykcVwexHOicr/B3IRd1yEAvfOsIWHOhyV9YR2YTRwjXc=@vger.kernel.org X-Gm-Message-State: AOJu0YwTw4Rm3vThFXmGX2HLFEtVccapwzqMnIU8mP6Jhzn0lsz66tK2 N6na6TdMOb2a9SChy91OFV8UiIQTCwozkUbY0lbfp1eiYPjllaJTbSHVMY/5H+c= X-Gm-Gg: ASbGncs3NoAqLQlHrV3ePN3e9Hx1JQTH5rftKE7CZdGsj5kuNSxqzMoROV7rbDntket EQ+lxqFJFOVHxEZKtIdUbieSJiD7VjepRfHasQYu7Gkdd3ZBF3Q7W49beXhdMb9AnmOPIiBFP/7 0ItglT+q7YiBe8jSEyocycUjEjPHFotWl5BdiEygRnZKzspGhj8yEOTMMjxSg0zK+1DgeULBNWu alLpVJ2xsUI+TXt6lel4SVBHCxButAH+4YQhB2YaIv9G/GpJfmiDA== X-Google-Smtp-Source: AGHT+IGJQBzx46oVDkkr51UYNg9QQolgkooANHZOCytLLBosiKXTDeptUQsxwc5OV1zLGoWGtnUwbA== X-Received: by 2002:a17:902:d508:b0:216:393b:23d4 with SMTP id d9443c01a7336-218d6fd5ebbmr82321875ad.11.1734594630933; Wed, 18 Dec 2024 23:50:30 -0800 (PST) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc97432dsm6784445ad.110.2024.12.18.23.50.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2024 23:50:30 -0800 (PST) From: Jun Nie Date: Thu, 19 Dec 2024 15:49:27 +0800 Subject: [PATCH v3 09/15] drm/msm/dpu: split PIPES_PER_STAGE definition per plane and mixer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-9-92c7c0a228e3@linaro.org> References: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> In-Reply-To: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734594568; l=5820; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=lJNk0O7zKbjtRBUPK/q7deOXG2gRF1mUYLxIqB8dl4g=; b=7ZNggoMXbrc/XSTgAUtIIo9jiSmKwjXmu+WIot50hbQGRU7mY3fZSgTank3joTqQ5OAR2XHCa qAKK5AwOl1LCyC4QW0SaftwOZlwIRP+zsXHCI9LlZ03dXIvM51Rk7Dr X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Split PIPES_PER_STAGE definition per plane and mixer pair. Because there are more than 2 pipes in quad pipe case, while 2 pipes at most per mixer pair. A stage struct serve a mixer pair, so pipes per plane is split out as PIPES_PER_PLANE. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 18 +++++++++--------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 4 ++-- 4 files changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index a0284b1425b1f..72ed8749cd716 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -463,7 +463,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, if (pstate->stage =3D=3D DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable =3D true; =20 - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_PLANE; i++) { if (!pstate->pipe[i].sspp) continue; set_bit(pstate->pipe[i].sspp->idx, fetch_active); @@ -1436,7 +1436,7 @@ static int _dpu_debugfs_status_show(struct seq_file *= s, void *data) state->crtc_x, state->crtc_y, state->crtc_w, state->crtc_h); =20 - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_PLANE; i++) { if (pstate->pipe[i].sspp) { seq_printf(s, "\tsspp[%d]:%s\n", i, pstate->pipe[i].sspp->cap->name); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_mdss.h index f8806a4d317be..68867c2f40d4b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -32,6 +32,7 @@ #define DPU_MAX_PLANES 4 #endif =20 +#define PIPES_PER_PLANE 2 #define PIPES_PER_STAGE 2 #ifndef DPU_MAX_DE_CURVES #define DPU_MAX_DE_CURVES 3 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index aaf934ec96be5..46c6b6126fe5c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -633,7 +633,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdp= u, return; =20 /* update sspp */ - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_PLANE; i++) { if (pstate->pipe[i].sspp) _dpu_plane_color_fill_pipe(pstate, &pstate->pipe[i], &pstate->pipe_cfg[i].dst_rect, @@ -1076,7 +1076,7 @@ static int dpu_plane_virtual_atomic_check(struct drm_= plane *plane, * resources are freed by dpu_crtc_assign_plane_resources(), * but clean them here. */ - for (i =3D 0; i < PIPES_PER_STAGE; i++) + for (i =3D 0; i < PIPES_PER_PLANE; i++) pstate->pipe[i].sspp =3D NULL; =20 return 0; @@ -1128,7 +1128,7 @@ static int dpu_plane_virtual_assign_resources(struct = drm_crtc *crtc, pipe_cfg =3D &pstate->pipe_cfg[0]; r_pipe_cfg =3D &pstate->pipe_cfg[1]; =20 - for (i =3D 0; i < PIPES_PER_STAGE; i++) + for (i =3D 0; i < PIPES_PER_PLANE; i++) pstate->pipe[i].sspp =3D NULL; =20 if (!plane_state->fb) @@ -1240,7 +1240,7 @@ void dpu_plane_flush(struct drm_plane *plane) /* force 100% alpha */ _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); else { - for (i =3D 0; i < PIPES_PER_STAGE; i++) + for (i =3D 0; i < PIPES_PER_PLANE; i++) dpu_plane_flush_csc(pdpu, &pstate->pipe[i]); } =20 @@ -1370,7 +1370,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_p= lane *plane, &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt)); =20 /* move the assignment here, to ease handling to another pairs later */ - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_PLANE; i++) { if (!pstate->pipe[i].sspp) continue; dpu_plane_sspp_update_pipe(plane, &pstate->pipe[i], @@ -1384,7 +1384,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_p= lane *plane, =20 pstate->plane_fetch_bw =3D 0; pstate->plane_clk =3D 0; - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_PLANE; i++) { if (!pstate->pipe[i].sspp) continue; pstate->plane_fetch_bw +=3D _dpu_plane_calc_bw(pdpu->catalog, fmt, @@ -1403,7 +1403,7 @@ static void _dpu_plane_atomic_disable(struct drm_plan= e *plane) struct dpu_sw_pipe *pipe; int i; =20 - for (i =3D 0; i < PIPES_PER_STAGE; i +=3D 1) { + for (i =3D 0; i < PIPES_PER_PLANE; i +=3D 1) { pipe =3D &pstate->pipe[i]; if (!pipe->sspp) continue; @@ -1518,7 +1518,7 @@ static void dpu_plane_atomic_print_state(struct drm_p= rinter *p, =20 drm_printf(p, "\tstage=3D%d\n", pstate->stage); =20 - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_PLANE; i++) { pipe =3D &pstate->pipe[i]; if (!pipe->sspp) continue; @@ -1575,7 +1575,7 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane *p= lane, bool enable) return; =20 pm_runtime_get_sync(&dpu_kms->pdev->dev); - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_PLANE; i++) { if (pstate->pipe[i].sspp) _dpu_plane_set_qos_ctrl(plane, &pstate->pipe[i], enable); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.h index 052fd046e8463..18ff5ec2603ed 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -33,8 +33,8 @@ struct dpu_plane_state { struct drm_plane_state base; struct msm_gem_address_space *aspace; - struct dpu_sw_pipe pipe[PIPES_PER_STAGE]; - struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_STAGE]; + struct dpu_sw_pipe pipe[PIPES_PER_PLANE]; + struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_PLANE]; enum dpu_stage stage; bool needs_qos_remap; bool pending; --=20 2.34.1 From nobody Thu Dec 18 20:22:07 2025 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75095218854 for ; Thu, 19 Dec 2024 07:50:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594640; cv=none; b=gKdcV1sOQIvyzb75KJW3B+csSdccPDYESxVTfmipOeYY9+M1cCbQAfrZmOIiFAZGUi54FsDc8BKhxYPuurp6kE+pcMDpHUqHGlPtHoZlf1bS7bw9T/Bw822lJdBY8KL0Gl5apXEHwAGtrRK6uV2/qOzeQyLh0uY2tSIW/W28+uc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594640; c=relaxed/simple; bh=6ZtdpxhXB/rhz3hCMyuJbmAdwfkWhh1P6PW5UxiXJuE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kPvYv6bW5NMKGPRop2XD4V9ZsxqyZaC6tmE6gO9TGn4QaDjDcHjLYyRQh0LwF77LU5fONfA1OlmzpXvB557YKT6ozWK1fE/w+E5Ba7D6Zp7AlqlMJ122ht+Nl35H25kBuBH6KBn+cbBUkBXJ1SPiLZEV85kkY2bx049DLpv8SNk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=z8vyB5It; arc=none smtp.client-ip=209.85.214.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="z8vyB5It" Received: by mail-pl1-f182.google.com with SMTP id d9443c01a7336-2163b0c09afso4584975ad.0 for ; Wed, 18 Dec 2024 23:50:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1734594638; x=1735199438; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=6QACPLHbU96vR5yGnVxi+OCvdrWdXj07n9rpK8uCOHE=; b=z8vyB5It8dtH0aMAtM0DVVm08/ghs+QoEARuBkIOSNdlielp0hRxGhvJpFIdO1uzce bU+9f0CYtOC4AI4uOTtHAp8SthYa55v9DylQilaAksxavkmL5mm+uaUBlgt6Mr7rVzoe r4W15m+7er6O0Yk6OGho+N1fd63hsgGAx1u8G9c3FMO6A4aJmXJdikb5u+qv3iMuvo4p t5WapnfHN2diNe449vuWi/P+jgaNPIqAPEY3mGv+NnbhuoBJHKda+yr9brgdnkXM+9KX 7/rOEhApJR6t+ODRpPmJGQF2DHepq0lwQB1s7h0EZM1J5bWtuTcEezugCBLLcE82Z+V6 FzoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734594638; x=1735199438; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6QACPLHbU96vR5yGnVxi+OCvdrWdXj07n9rpK8uCOHE=; b=phv4E1EOpgl8mMaZYm3MUAvsvVSXWjLYwCs+owubvX+lJtmbKSt1yjAjsCruey2IxC 613Xue2SvJoVdFmLMc+DV9bk8dFnGMvJpRobqN+dfV1wB2s3LAj3S2KbRFdAJ2WS5zVT ArTOJBaVUfRo/PSezkDS/AJvW8oPAgR5o87WjXRkO+f09eHvbdRlYtYBBdMHUV9luPt7 nuh7GUr7+ma1S0fPdC+pdtWbgt169o1UV/QhvKGKqxwNbtNFCxL/NdUN5k0bvcTw5VAy UxeHttAud/gNfRVkOjICQxBYqaX46ZVLxAZUv5LCN4BeMF3AVV669FWveTjcHM1L1XMU /B6g== X-Forwarded-Encrypted: i=1; AJvYcCURMg9/Mc1VB1hkhE/agTNVSaRY2cFHVUB4f8g+cRKt0q6g6sQLYEKrOGgJHgkqX16qa0JQEbs/L0UOLng=@vger.kernel.org X-Gm-Message-State: AOJu0YzSxjSGoI2v0Rii2AdrTEDGQEm4UnTNwXoU/sZeqkDQtmoBVM14 kzmib3nqulk1O284fGgT9d26QsyIxQP59YMOYyDT7lO+1TIOzUbmLa9NExj8I24= X-Gm-Gg: ASbGncvP5P4AjpzKkSSLLSVwxSNnuqEI7lW6rsnsVHbIwNxyz5bIhvKHIiC5+ivu2PM vS2M5/HmuLVn/uSeex5drqGB+L12XfPSogFn+L/td8QHwqPGeIQcVUBDb+o58ETAWwghCuX+rV9 SP0yDwBKigK2u4vubcc1oTXx6JL2Mc+xEB5ZDooIyQvR0ToCg7PGJ77Y+8dwlt1hzUejxyfBeYH CNMsAT4y64XVGVcwFkYQ3ewXFi3Sr37HXkUIjhIhqJocnGc1zVzhg== X-Google-Smtp-Source: AGHT+IFw74Cgq7jywjWum0/vvzCufwreSULGiGLizUIz+reETmaHjliDxBUvaVtVLedA+GKu2zL2mg== X-Received: by 2002:a17:903:18b:b0:216:2a36:5b2a with SMTP id d9443c01a7336-218d727dd8cmr83172895ad.47.1734594637757; Wed, 18 Dec 2024 23:50:37 -0800 (PST) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc97432dsm6784445ad.110.2024.12.18.23.50.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2024 23:50:37 -0800 (PST) From: Jun Nie Date: Thu, 19 Dec 2024 15:49:28 +0800 Subject: [PATCH v3 10/15] drm/msm/dpu: Add pipe as trace argument Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-10-92c7c0a228e3@linaro.org> References: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> In-Reply-To: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734594568; l=2230; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=6ZtdpxhXB/rhz3hCMyuJbmAdwfkWhh1P6PW5UxiXJuE=; b=DKvn2dcBo0LBd5J6yg1T8LHUwMwZBR8+U8I5tnUqhsqeeWjSyF2K1WgAOy2JmiekoigPcSUOf 7AmgzuaRziLAakLiBOKe45if2lXog+ljyKv2gKGx/xOlvKMcfT04XH6 X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Add pipe as trace argument to ease converting pipe into pipe array later. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 72ed8749cd716..6841d0504d450 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -411,7 +411,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc = *crtc, =20 trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane), state, to_dpu_plane_state(state), stage_idx, - format->pixel_format, + format->pixel_format, pipe, modifier); =20 DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d multirect_idx= %d\n", diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_trace.h index 5307cbc2007c5..cb24ad2a6d8d3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h @@ -651,9 +651,9 @@ TRACE_EVENT(dpu_crtc_setup_mixer, TP_PROTO(uint32_t crtc_id, uint32_t plane_id, struct drm_plane_state *state, struct dpu_plane_state *pstate, uint32_t stage_idx, uint32_t pixel_format, - uint64_t modifier), + struct dpu_sw_pipe *pipe, uint64_t modifier), TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx, - pixel_format, modifier), + pixel_format, pipe, modifier), TP_STRUCT__entry( __field( uint32_t, crtc_id ) __field( uint32_t, plane_id ) @@ -676,9 +676,9 @@ TRACE_EVENT(dpu_crtc_setup_mixer, __entry->dst_rect =3D drm_plane_state_dest(state); __entry->stage_idx =3D stage_idx; __entry->stage =3D pstate->stage; - __entry->sspp =3D pstate->pipe.sspp->idx; - __entry->multirect_idx =3D pstate->pipe.multirect_index; - __entry->multirect_mode =3D pstate->pipe.multirect_mode; + __entry->sspp =3D pipe->sspp->idx; + __entry->multirect_idx =3D pipe->multirect_index; + __entry->multirect_mode =3D pipe->multirect_mode; __entry->pixel_format =3D pixel_format; __entry->modifier =3D modifier; ), --=20 2.34.1 From nobody Thu Dec 18 20:22:07 2025 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5800C217F4B for ; Thu, 19 Dec 2024 07:50:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594646; cv=none; b=UymtmdSCP+ypGkkouFjB49xe0PxuFxlBhk3EhRZ0yfWuat6uSbxZ/yT3YcyAL6yQJ6w4hLy//2LqQrfcW5hxK98MLB7acYKyPRJcqG6+v0M21vW56vg1SOFYs6yHvKqaVRVCcrp/96zpFHT2rRY0GbXr5erUyIVza2h/FyKHfxs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594646; c=relaxed/simple; bh=oxfzARhHE0/oq4CY3TryYx9jMpUF/fTBmG2EofRgAt8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NrXvhBoqZZnc2FS08LHwQt96o8IEKA4T2LhQFWRqfKuWdeobL8zslZ3zXb63BqbKcLz1X142uWBDh4B6lR0Nb8J2rhoWXJhnEVjDmtG9Gbxpk4bhMnWFpT3gE8JU0pKjr5A8zG4zXzqrD+v9PHcBkwMb18Mh+tJenjH5emSBDu0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=OO+oc0Il; arc=none smtp.client-ip=209.85.214.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="OO+oc0Il" Received: by mail-pl1-f176.google.com with SMTP id d9443c01a7336-216281bc30fso5980845ad.0 for ; Wed, 18 Dec 2024 23:50:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1734594643; x=1735199443; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ENyMFx72ZbBjFc06s6EFkz2rNCIxTdMxqvx5v8cSqvI=; b=OO+oc0IlnxFs49ogdLVKbvxwIJ+bi86/4Usiirk2K9MdWQ1xxapzZfjum+yB7imQKo xCSuTzjQsNHq16GNxbpQ+7NQUvoIab5IwxRuhecCNH6CE1w/ZJIFDhEZBgGp7jIPyCT5 MyP5JOPNav83EkT293VHLca8SC+8gh++haTb4nt5faUHZDkLQ9nL7XHP4IaULpSCW4PA Fyh3ZkUDmlguYXxyIE99TzrXvIWVluWJuIz29U694xg8rcW9TcdzZSdv7Legs4KiyuAa 5nps255Qfv/fOgAaKahZTUebqmj/mkqemiGFcn6a8IzjeL0uECVwLSWe1NHPFS28QM/o c8kQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734594643; x=1735199443; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ENyMFx72ZbBjFc06s6EFkz2rNCIxTdMxqvx5v8cSqvI=; b=qP6HsYNRfWZDOp3EV2/H3eH8WZ0i02XlKyilOXnqW+bmges/TTrUGNZTvgjZlWA6C2 kynX1s9MuzzwKqjgQW7rrYRzAgTFwG/SJUHO/sXxid/tRDeYLorrOolPtf2J3miqWc2L Kw7gS+68b1k4iITNmBUqVP1gMcJAAjadlxKAJOy/tzQC0V+50sSwoBQDxNq0KSpWNods 8KUPutnBDRSwQX05k2Key+Tr3RMnvUeKA5n3Tx7b2XBPJArradUqSS8g0aZtTOYA/2UU iSr5Q2heCpFOgQOKjvdHIdKgq6GmXuW3YQL26j7W0tPuIvliLDFXATzOhYs6IhEilW10 vsvw== X-Forwarded-Encrypted: i=1; AJvYcCVjhWO3dNH5ze2ixU4XFPDo1pcSFDfnkKVuODEmIqEQ4dljil+4ZwxyfPp6R/LKffP0J/aT1ickj0+rX2c=@vger.kernel.org X-Gm-Message-State: AOJu0YxgmhIJi3LBQHcSB/Mm/STYikRmucuehiipQOknJG5ifsiwVT05 LC2YUJz0nT37WWbcgjjx7j3ZURfCUKS76MCIPtxENvtk2c0VbbrSF59Ei/Je0sU= X-Gm-Gg: ASbGncu7/QIgeXgFgo7oPWCqh2FBwKEVmlvcKVaZmNM5H0d5wMjbTTnfV4jKVNkYcjN xrEQvovc0Q5LdWl7LVqnuE5y1OzH6dsvhZz9Pa73sY4/iZvCXEXEO6rRmoU/3QJ6y4AXcKq3q1d t62vYMyBy9Vkod/PKfCS1uMdQv/daQ0tFEWFEZCrKqS3VX/ZIPbT2iWmnY3WM3muPemIQ+3jzym MV06BW0lZgUuqdhJs+8aCAI+EOMhBKbK9rb4INnNu1D6RTNXcP/bA== X-Google-Smtp-Source: AGHT+IFmpHu4d1IsZ65VlCxjfUI3RfnJ3SyPUSxBWEEQxMEDM9PoBBmloo1N8vMAb0BH43O2dSKsZA== X-Received: by 2002:a17:903:2306:b0:215:b74c:d7ad with SMTP id d9443c01a7336-218d725f86emr101088515ad.36.1734594643625; Wed, 18 Dec 2024 23:50:43 -0800 (PST) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc97432dsm6784445ad.110.2024.12.18.23.50.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2024 23:50:43 -0800 (PST) From: Jun Nie Date: Thu, 19 Dec 2024 15:49:29 +0800 Subject: [PATCH v3 11/15] drm/msm/dpu: blend pipes per mixer pairs config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-11-92c7c0a228e3@linaro.org> References: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> In-Reply-To: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734594568; l=3915; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=oxfzARhHE0/oq4CY3TryYx9jMpUF/fTBmG2EofRgAt8=; b=4VJ/vrmSv8023lmyh58C9GHrKJCLCtsc079xQYjNxU1PjwMNPdtal4TXeYiH+XxluBWXIBxv6 cio4O+HUxoXBoQdmaVODcZCYQp/364gkSdqbwGST3Kpk4tPOKgqGnzG X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Blend pipes by set of mixer pair config. The first 2 pipes are for left half screen with the first set of mixer pair config. And the later 2 pipes are for right in quad pipe case. A stage structure serves a mixer pair, that is coupled with 2 pipes. So the stage array number is defined as STAGES_PER_PLANE. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 38 ++++++++++++++++++-------= ---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 1 + 2 files changed, 25 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 6841d0504d450..6ef7e6ed00238 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -442,7 +442,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, const struct msm_format *format; struct dpu_hw_ctl *ctl =3D mixer->lm_ctl; =20 - uint32_t lm_idx, i; + uint32_t lm_idx, stage, i, pipe_idx; bool bg_alpha_enable =3D false; DECLARE_BITMAP(fetch_active, SSPP_MAX); =20 @@ -463,15 +463,20 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_cr= tc *crtc, if (pstate->stage =3D=3D DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable =3D true; =20 - for (i =3D 0; i < PIPES_PER_PLANE; i++) { - if (!pstate->pipe[i].sspp) - continue; - set_bit(pstate->pipe[i].sspp->idx, fetch_active); - _dpu_crtc_blend_setup_pipe(crtc, plane, - mixer, cstate->num_mixers, - pstate->stage, - format, fb ? fb->modifier : 0, - &pstate->pipe[i], i, stage_cfg); + /* loop pipe per mixer pair that's served by a stage structure */ + for (stage =3D 0; stage < PIPES_PER_PLANE / STAGES_PER_PLANE; stage++) { + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + pipe_idx =3D i + stage * PIPES_PER_STAGE; + if (!pstate->pipe[pipe_idx].sspp) + continue; + set_bit(pstate->pipe[pipe_idx].sspp->idx, fetch_active); + _dpu_crtc_blend_setup_pipe(crtc, plane, + mixer, cstate->num_mixers, + pstate->stage, + format, fb ? fb->modifier : 0, + &pstate->pipe[pipe_idx], i, + &stage_cfg[stage]); + } } =20 /* blend config update */ @@ -503,7 +508,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) struct dpu_crtc_mixer *mixer =3D cstate->mixers; struct dpu_hw_ctl *ctl; struct dpu_hw_mixer *lm; - struct dpu_hw_stage_cfg stage_cfg; + struct dpu_hw_stage_cfg stage_cfg[STAGES_PER_PLANE]; int i; =20 DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name); @@ -516,9 +521,9 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) } =20 /* initialize stage cfg */ - memset(&stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg)); + memset(&stage_cfg, 0, sizeof(stage_cfg)); =20 - _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg); + _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg[0]); =20 for (i =3D 0; i < cstate->num_mixers; i++) { ctl =3D mixer[i].lm_ctl; @@ -535,8 +540,13 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crt= c) mixer[i].mixer_op_mode, ctl->idx - CTL_0); =20 + /* + * call dpu_hw_ctl_setup_blendstage() to blend layers per stage cfg. + * There is 4 mixers at most. The first 2 are for the left half, and + * the later 2 are for the right half. + */ ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, - &stage_cfg); + &stage_cfg[i / 2]); } } =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_mdss.h index 68867c2f40d4b..27ef0771da5d2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -32,6 +32,7 @@ #define DPU_MAX_PLANES 4 #endif =20 +#define STAGES_PER_PLANE 2 #define PIPES_PER_PLANE 2 #define PIPES_PER_STAGE 2 #ifndef DPU_MAX_DE_CURVES --=20 2.34.1 From nobody Thu Dec 18 20:22:07 2025 Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1892217F57 for ; Thu, 19 Dec 2024 07:50:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594652; cv=none; b=U43M8Exre4Q1vysq4kaYjbYxDnnoZ61TxBCHab++NCecBmv0pDdDWMG6y+GXGUNXTtBK+W8cLPmVS44hANs9uB2+N1BhtlrUQzN5CP3o9f5E1NL4CLjo+pPvlsvmqFeb1N3P0VoMQDQo/5bB7it/JuzkNMWRQop7jOQQdULWFPU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594652; c=relaxed/simple; bh=TlGDQaK+RIr4jaGppe96K5ODnLOh+oTUjGh0kiPdyMc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=P0Zl5Bo85ztnSvoTZJmnPbI6AEHq4lrZVU66D5neUOvi9/v4HtJ2HC31bfDghE2syQTGvIWo4shrcQ/Ys9SeXKj5m6nbfRA8M+PTNnFGwpehLnFxSjldGI0Q17Ch3yn5phRe/1acktkoN8N8I91pLUFf6F511qT/S/DRmnm1Yyc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=cUMbc2nB; arc=none smtp.client-ip=209.85.214.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="cUMbc2nB" Received: by mail-pl1-f174.google.com with SMTP id d9443c01a7336-2162c0f6a39so14933085ad.0 for ; Wed, 18 Dec 2024 23:50:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1734594650; x=1735199450; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=18nlxVwPoKLr3E2wHXVPadI8cx5c0FRvaFnyj0j882Q=; b=cUMbc2nBm3l3/YTxgmJg7W698Fxj3Q6Y74x0XQ25A6mpDK0JaQBlR9Jzh8uEi1H8kN inkisILgUXTT6uSYrMoACIeoL3+3744P82CeH8333oQD3zbRvQfAXMc3uheMVCKR4c0B 4lH5lDeNls1TxuG7d0jA+dtWA1AhYrs5i+ptmQ60ZyxFT3z0wjDodtd6PJQ0sJD3AmN9 ff5Sslyg0O32OAHcYjJ4vMQJ8rPka2AjNkYERKrZBPg6F/kqbN6eo5NCChwWxT+O9Kbp FN8RxIJLqyywshVrWw3ylf4jpDp46BrcRTLx+dBnhciC4FdTyiS7ITMUGCiLNQqVO3VU Yy0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734594650; x=1735199450; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=18nlxVwPoKLr3E2wHXVPadI8cx5c0FRvaFnyj0j882Q=; b=aFzXWUJ6lVUs/zPsIxcmXiZ0ztwnzTRePjgDEzb1dbSMgLq3xgAQgy17bkssBR90Uj Tmd2t74mB/c6/W0Efj6ZJd7t0af1J2wuFQCMpglM2DE9XGiWs0thmdRDLlh5zgGY43Xg 3vd9gCIvDvQ1yYftVi9+up8Wooz7JN/dvz01dBQniajlhKP+FBwqX8kpXFDoco8lOWK9 Adt/qiaoYzU8mkSHGL1z+MXDVW1bgOf4JyivO8CeAwbyuovWu8YUUQ38mfOpa1fOb3+O cM0v1Vi4wkQCrm2D7wWqOkw5o4nGbhMlV/4VznrOH2uZ50uJ5WZU7O+srzQOxqSWl9pD PlTg== X-Forwarded-Encrypted: i=1; AJvYcCUxt/m/PN8yVnS1ooaVY5UiJPq8oSK2EzSsPQ1rwH0TfPtzb8ozQhAXTWmkxEyCzPFpDbg2+KmgSsdqXu4=@vger.kernel.org X-Gm-Message-State: AOJu0YxxMaJrcP/YUgbPAgwzlvjetXizcBw6Fo4HiEl4a9gko9Fv6vUI wh2u0g2BR5u4U5XMXk/JbmlodfBiFAh+U+xOiLKXQxeYbukWseST41e/dXEwuhk= X-Gm-Gg: ASbGncvme7xk/JjnenV29Q6wKhK4o9e+CDB8bU+EilyNXJ3+TgtcwjlUzXenAb6X01T 5dLHdd8actiNGYYQt/q5Q04AQwo7I9NSe5goMOHo/H8n2j3Lwq11UtZjqBgPUP5XZ1Guy0mK2Ki ZomMsOhcAGR5vJP43CSQqC75IKB7u4K0sXWEbtVkX8B+zQ/r1W+KvFlALmotiCH14NgRmY4xnrd Itoju0/tQk2scGlfWYfoAoMC4RzP4/wl/1+oLUZN5BRBnQq2lqM8Q== X-Google-Smtp-Source: AGHT+IHGhWssJJ0I+Rok6/BWTnxTjdpxP2HomvpGSIQ0VmIZFtIkQM1HyIQshxHoKEuwfXQuoAnk8w== X-Received: by 2002:a17:902:ebc2:b0:216:311e:b1c4 with SMTP id d9443c01a7336-219da5b9cc6mr33955365ad.4.1734594650003; Wed, 18 Dec 2024 23:50:50 -0800 (PST) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc97432dsm6784445ad.110.2024.12.18.23.50.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2024 23:50:49 -0800 (PST) From: Jun Nie Date: Thu, 19 Dec 2024 15:49:30 +0800 Subject: [PATCH v3 12/15] drm/msm/dpu: support plane splitting in quad-pipe case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-12-92c7c0a228e3@linaro.org> References: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> In-Reply-To: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734594568; l=8743; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=TlGDQaK+RIr4jaGppe96K5ODnLOh+oTUjGh0kiPdyMc=; b=LKCvbzjbUtlNpAKUkKExLqmo0i3GGPxESU3z90s8W9GgCw34CyAtD/b5Wa0IsMuu1F9plhR0a ccJBs8JH8H0BJy81Q/+92vcBjC9m4jtUDqLKvEniSzKTmV/zze0vt1v X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= The content of every half of screen is sent out via one interface in dual-DSI case. The content for every interface is blended by a LM pair, thus no content of any pipe shall cross the LM pair. We need to clip plane into pipes per left and right half screen ROI if topology is quad pipe. The clipped rectangle on every half of screen will be split further by half if its width still exceeds limit. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 7 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 6 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 108 +++++++++++++++++++++---= ---- 4 files changed, 97 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 6ef7e6ed00238..bad75af4e50ab 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1363,6 +1363,13 @@ int dpu_crtc_vblank(struct drm_crtc *crtc, bool en) return 0; } =20 +unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state) +{ + struct dpu_crtc_state *cstate =3D to_dpu_crtc_state(state); + + return cstate->num_mixers; +} + #ifdef CONFIG_DEBUG_FS static int _dpu_debugfs_status_show(struct seq_file *s, void *data) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.h index 0b148f3ce0d7a..d1bb3f84fe440 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -264,4 +264,10 @@ static inline enum dpu_crtc_client_type dpu_crtc_get_c= lient_type( =20 void dpu_crtc_frame_event_cb(struct drm_crtc *crtc, u32 event); =20 +/** + * dpu_crtc_get_num_lm - Get mixer number in this CRTC pipeline + * state: Pointer to drm crtc state object + */ +unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state); + #endif /* _DPU_CRTC_H_ */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_sspp.h index 56a0edf2a57c6..39fe338e76691 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -145,11 +145,13 @@ struct dpu_hw_pixel_ext { * such as decimation, flip etc to program this field * @dest_rect: destination ROI. * @rotation: simplified drm rotation hint + * @valid: notify that this pipe and config is in use */ struct dpu_sw_pipe_cfg { struct drm_rect src_rect; struct drm_rect dst_rect; unsigned int rotation; + bool valid; }; =20 /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 46c6b6126fe5c..fca6e609898a6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -802,8 +802,14 @@ static int dpu_plane_atomic_check_nosspp(struct drm_pl= ane *plane, struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); struct dpu_sw_pipe_cfg *pipe_cfg; struct dpu_sw_pipe_cfg *r_pipe_cfg; + struct dpu_sw_pipe *pipe; + struct dpu_sw_pipe *r_pipe; + struct dpu_sw_pipe_cfg init_pipe_cfg; struct drm_rect fb_rect =3D { 0 }; + const struct drm_display_mode *mode =3D &crtc_state->adjusted_mode; uint32_t max_linewidth; + u32 num_lm; + int stage_id, num_stages; =20 min_scale =3D FRAC_16_16(1, MAX_UPSCALE_RATIO); max_scale =3D MAX_DOWNSCALE_RATIO << 16; @@ -826,13 +832,10 @@ static int dpu_plane_atomic_check_nosspp(struct drm_p= lane *plane, return -EINVAL; } =20 - /* move the assignment here, to ease handling to another pairs later */ - pipe_cfg =3D &pstate->pipe_cfg[0]; - r_pipe_cfg =3D &pstate->pipe_cfg[1]; - /* state->src is 16.16, src_rect is not */ - drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); + num_lm =3D dpu_crtc_get_num_lm(crtc_state); =20 - pipe_cfg->dst_rect =3D new_plane_state->dst; + /* state->src is 16.16, src_rect is not */ + drm_rect_fp_to_int(&init_pipe_cfg.src_rect, &new_plane_state->src); =20 fb_rect.x2 =3D new_plane_state->fb->width; fb_rect.y2 =3D new_plane_state->fb->height; @@ -857,34 +860,87 @@ static int dpu_plane_atomic_check_nosspp(struct drm_p= lane *plane, =20 max_linewidth =3D pdpu->catalog->caps->max_linewidth; =20 - drm_rect_rotate(&pipe_cfg->src_rect, + drm_rect_rotate(&init_pipe_cfg.src_rect, new_plane_state->fb->width, new_plane_state->fb->height, new_plane_state->rotation); =20 - if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || - _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_= clk_rate) { - if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { - DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", - DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); - return -E2BIG; + /* + * We have 1 mixer pair cfg for 1:1:1 and 2:2:1 topology, 2 mixer pair + * configs for left and right half screen in case of 4:4:2 topology. + * But we may have 2 rect to split plane with 1 config for 2:2:1. + * So need to handle super wide plane splitting, and plane on right half + * for quad-pipe case. Check dest rectangle left/right clipping + * first, then check super wide rectangle splitting in every half next. + */ + num_stages =3D (num_lm + 1) / 2; + /* iterate mixer configs for this plane, to separate left/right with the = id */ + for (stage_id =3D 0; stage_id < num_stages; stage_id++) { + struct drm_rect mixer_rect =3D {stage_id * mode->hdisplay / num_stages, = 0, + (stage_id + 1) * mode->hdisplay / num_stages, + mode->vdisplay}; + int cfg_idx =3D stage_id * PIPES_PER_STAGE; + + pipe =3D &pstate->pipe[cfg_idx]; + r_pipe =3D &pstate->pipe[cfg_idx + 1]; + pipe_cfg =3D &pstate->pipe_cfg[cfg_idx]; + r_pipe_cfg =3D &pstate->pipe_cfg[cfg_idx + 1]; + + drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); + pipe_cfg->dst_rect =3D new_plane_state->dst; + + DPU_DEBUG_PLANE(pdpu, "checking src " DRM_RECT_FMT + " vs clip window " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), + DRM_RECT_ARG(&mixer_rect)); + + /* + * If this plane does not fall into mixer rect, check next + * mixer rect. + */ + if (!drm_rect_clip_scaled(&pipe_cfg->src_rect, + &pipe_cfg->dst_rect, + &mixer_rect)) { + memset(pipe_cfg, 0, 2 * sizeof(struct dpu_sw_pipe_cfg)); + memset(pipe, 0, 2 * sizeof(struct dpu_sw_pipe)); + continue; } =20 - *r_pipe_cfg =3D *pipe_cfg; - pipe_cfg->src_rect.x2 =3D (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2= ) >> 1; - pipe_cfg->dst_rect.x2 =3D (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2= ) >> 1; - r_pipe_cfg->src_rect.x1 =3D pipe_cfg->src_rect.x2; - r_pipe_cfg->dst_rect.x1 =3D pipe_cfg->dst_rect.x2; - } else { - memset(r_pipe_cfg, 0, sizeof(*r_pipe_cfg)); - } + pipe_cfg->valid =3D true; + pipe_cfg->dst_rect.x1 -=3D mixer_rect.x1; + pipe_cfg->dst_rect.x2 -=3D mixer_rect.x1; + + DPU_DEBUG_PLANE(pdpu, "Got clip src:" DRM_RECT_FMT " dst: " DRM_RECT_FMT= "\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), DRM_RECT_ARG(&pipe_cfg->dst_rect)); + + /* Split super wide rect into 2 rect */ + if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || + _dpu_plane_calc_clk(mode, pipe_cfg) > max_mdp_clk_rate) { + + if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { + DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); + return -E2BIG; + } + + memcpy(r_pipe_cfg, pipe_cfg, sizeof(struct dpu_sw_pipe_cfg)); + pipe_cfg->src_rect.x2 =3D (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x= 2) >> 1; + pipe_cfg->dst_rect.x2 =3D (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x= 2) >> 1; + r_pipe_cfg->src_rect.x1 =3D pipe_cfg->src_rect.x2; + r_pipe_cfg->dst_rect.x1 =3D pipe_cfg->dst_rect.x2; + r_pipe_cfg->valid =3D true; + DPU_DEBUG_PLANE(pdpu, "Split super wide plane into:" + DRM_RECT_FMT " and " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), + DRM_RECT_ARG(&r_pipe_cfg->src_rect)); + } else { + memset(r_pipe_cfg, 0, sizeof(struct dpu_sw_pipe_cfg)); + memset(r_pipe, 0, sizeof(struct dpu_sw_pipe)); + } =20 - drm_rect_rotate_inv(&pipe_cfg->src_rect, - new_plane_state->fb->width, new_plane_state->fb->height, - new_plane_state->rotation); - if (drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0) - drm_rect_rotate_inv(&r_pipe_cfg->src_rect, + drm_rect_rotate_inv(&pipe_cfg->src_rect, new_plane_state->fb->width, new_plane_state->fb->height, new_plane_state->rotation); + } =20 pstate->needs_qos_remap =3D drm_atomic_crtc_needs_modeset(crtc_state); =20 --=20 2.34.1 From nobody Thu Dec 18 20:22:07 2025 Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A2B1217F57 for ; Thu, 19 Dec 2024 07:50:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594659; cv=none; b=FSCIn5082TCvqqQLPQRe7ciXSKoaEshR+sFgGQggKIJi4Is91onh2FTpvd3d43I42zl0pAFiEBBPbKxji4ajCLNUFnu6uX1VpZRddv8g4fs+t+HEMVynt0iwsRiurHjuX8Z2nYzrWftvacb4oFxrwpW5rRV847/B7YC2inwVCMU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594659; c=relaxed/simple; bh=F5vdJwFxIcC21jVkfwNGwrZjNxJ2H5r+EMS30BWgqAo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SaKt5rauTSFHiJKOE4fexBbHqiqzVFvBhn36j78INRbJGMinMO0c1aZHKIGdTSClygbA93E/A+td8l1bPWx3l/AV+DuX/1C3Tvpb1T8zvorEsdds/qAaDBs5hPMeA8qKVwKRj/1wA0kqIWmRMJsQh0Hjw35djvR54ByTE6rz+1s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=fyDR2iOr; arc=none smtp.client-ip=209.85.214.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="fyDR2iOr" Received: by mail-pl1-f174.google.com with SMTP id d9443c01a7336-2165448243fso5510205ad.1 for ; Wed, 18 Dec 2024 23:50:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1734594656; x=1735199456; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=GJmsZZpuwbe+vGhIhYkh/sA+lzfRDGmnljR17dLmKnE=; b=fyDR2iOrXj28aXD2GYYYH/Lo09BiLVa53luztYeMhuM0QSthJYjKS/Qh18tioWHABg SIsWJaMrFFUVLgxoRexmruIqobDoq5FZiXuIJl5XjjNDTY1kGDNzrZqGbAHxJaVxsyQG jPB6Tufczfszomh/8pchMFiJz/MUGwlibqG11y9MyJEm9hubH59S54upuUB+eJFkd6Bl 2K0sQr4qrIgDs+V9Cp6xgLIPhzKJ37XWom90OzIHrKOkHRNMJ4wZxH0EpJC11h6X2J9e W/1WduETStS2EiCsjKiL56n87uaKZ+Sd3qxLA6O3Qaq0bgJJM99kpT3G7VOICnwMU+4c w4LQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734594656; x=1735199456; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GJmsZZpuwbe+vGhIhYkh/sA+lzfRDGmnljR17dLmKnE=; b=lOww1n1xguv3x6xnhTCP6YBjkuKC79q1UpwzFHP35tjvyJFOrAU1Qq2L1ImpNaMulw s+70FnUaJHxjT64dIEoDP43c+uKAqP5goyD0hmVOaieMr7D4Wq9IWeTgDwL/yvw8Xj7J oftR0GGtejWSqGiE4alpMjcYAxQQC6iozHQiXhm8EDZK6hzopdZbW4uKCVx5lhoGPWd2 HHN+geBi0n0sJ1HwkQGK8/0uINT2fQqavN8ZuHdmwfbZMgWzVM1F2YpMzx4B70ZI0Q8X thgsb/hV+SrhtRCEnr1TDhgsB+P7rZp4aCoKL6D2PHqfgg9fZsb9/6BcG6pnnZ0V/0Xj BWGg== X-Forwarded-Encrypted: i=1; AJvYcCXIB+QucnhC3qP3UCYWQn83lslQPVtGfPTmmAhGQQFZfWFNF7d3GkfEYsSsnt7igc2LwKLaPh5/hvJKGIw=@vger.kernel.org X-Gm-Message-State: AOJu0YzWlMcdpb86jPBEcxYJ5wArvKnySKghNsntccgGoVq/sTd5mGSD Vh4PXMu0wT9oOCbHbppJemjUhJb3oLSzW9taIv6WM5toaG4eeuWxp++fLwPyDDY= X-Gm-Gg: ASbGncuXa0K9D1yXn+yPNBZhUiQunm9rnMRnJiDUPpcP8UnNkD3BvVcALwd2cIlQxXy cCyQkHSrRqBfAD/5qHA39UIRoLk80IxFhOEAv8N24pP15I1FMZ5Vi30gduoriw4G/UVBTDhNdDY fVgc1Dks2qmijoGjJM0c7H+ijgMEe8g8WQxaX1+q9lrjvxao3jSVVEo1z9mDLPZJhI3bV3gvwOA CCBYP4HnJ423/H/ufNqgQhxtulBTLMsj7242Tz7zYggAZ0cjWQhPw== X-Google-Smtp-Source: AGHT+IEOqA1vJf2uFvBqIESm9Tov34I/A0aYwu0QNTS1g6acpaxijvfrMk0duLvIL4x6NLUt1a8Z1g== X-Received: by 2002:a17:902:d510:b0:216:59ed:1a9c with SMTP id d9443c01a7336-218d726d7f9mr74054205ad.55.1734594656721; Wed, 18 Dec 2024 23:50:56 -0800 (PST) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc97432dsm6784445ad.110.2024.12.18.23.50.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2024 23:50:56 -0800 (PST) From: Jun Nie Date: Thu, 19 Dec 2024 15:49:31 +0800 Subject: [PATCH v3 13/15] drm/msm/dpu: Support quad-pipe in SSPP checking Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-13-92c7c0a228e3@linaro.org> References: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> In-Reply-To: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734594568; l=4472; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=F5vdJwFxIcC21jVkfwNGwrZjNxJ2H5r+EMS30BWgqAo=; b=lePD4rWXUf7a8kUW35TLtTYSAqcnRIc9x4Bkc604Bb7xiZ+vYvR8cP6h183sxiT1ncmdFxY/t fFjQ27KJyaPDj1t+3m1gCliw0IrjT/HtGtorJSxK5JVCfiSmRv2JhZM X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Move requreiment check to routine of every pipe check. There will be multiple SSPPs for quad-pipe case in future. Only check valid pipe as some pipes are for multi-rect or right half of screen that may not be used. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 86 +++++++++++++++------------= ---- 1 file changed, 42 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index fca6e609898a6..1cd98892898a4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -730,12 +730,40 @@ static int dpu_plane_check_inline_rotation(struct dpu= _plane *pdpu, static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe, struct dpu_sw_pipe_cfg *pipe_cfg, - const struct msm_format *fmt, - const struct drm_display_mode *mode) + const struct drm_display_mode *mode, + struct drm_plane_state *new_plane_state) { uint32_t min_src_size; struct dpu_kms *kms =3D _dpu_plane_get_kms(&pdpu->base); int ret; + const struct msm_format *fmt; + uint32_t supported_rotations; + const struct dpu_sspp_cfg *pipe_hw_caps; + const struct dpu_sspp_sub_blks *sblk; + + pipe_hw_caps =3D pipe->sspp->cap; + sblk =3D pipe->sspp->cap->sblk; + + /* + * We already have verified scaling against platform limitations. + * Now check if the SSPP supports scaling at all. + */ + if (!sblk->scaler_blk.len && + ((drm_rect_width(&new_plane_state->src) >> 16 !=3D + drm_rect_width(&new_plane_state->dst)) || + (drm_rect_height(&new_plane_state->src) >> 16 !=3D + drm_rect_height(&new_plane_state->dst)))) + return -ERANGE; + + fmt =3D msm_framebuffer_format(new_plane_state->fb); + + supported_rotations =3D DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; + + if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) + supported_rotations |=3D DRM_MODE_ROTATE_90; + + pipe_cfg->rotation =3D drm_rotation_simplify(new_plane_state->rotation, + supported_rotations); =20 min_src_size =3D MSM_FORMAT_IS_YUV(fmt) ? 2 : 1; =20 @@ -981,49 +1009,19 @@ static int dpu_plane_atomic_check_sspp(struct drm_pl= ane *plane, drm_atomic_get_new_plane_state(state, plane); struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); - const struct msm_format *fmt; - struct dpu_sw_pipe *pipe =3D &pstate->pipe[0]; - struct dpu_sw_pipe *r_pipe =3D &pstate->pipe[1]; - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg[0]; - struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->pipe_cfg[1]; - uint32_t supported_rotations; - const struct dpu_sspp_cfg *pipe_hw_caps; - const struct dpu_sspp_sub_blks *sblk; - int ret =3D 0; - - pipe_hw_caps =3D pipe->sspp->cap; - sblk =3D pipe->sspp->cap->sblk; - - /* - * We already have verified scaling against platform limitations. - * Now check if the SSPP supports scaling at all. - */ - if (!sblk->scaler_blk.len && - ((drm_rect_width(&new_plane_state->src) >> 16 !=3D - drm_rect_width(&new_plane_state->dst)) || - (drm_rect_height(&new_plane_state->src) >> 16 !=3D - drm_rect_height(&new_plane_state->dst)))) - return -ERANGE; - - fmt =3D msm_framebuffer_format(new_plane_state->fb); - - supported_rotations =3D DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; - - if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) - supported_rotations |=3D DRM_MODE_ROTATE_90; - - pipe_cfg->rotation =3D drm_rotation_simplify(new_plane_state->rotation, - supported_rotations); - r_pipe_cfg->rotation =3D pipe_cfg->rotation; - - ret =3D dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt, - &crtc_state->adjusted_mode); - if (ret) - return ret; + struct dpu_sw_pipe *pipe; + struct dpu_sw_pipe_cfg *pipe_cfg; + int ret =3D 0, i; =20 - if (drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0) { - ret =3D dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt, - &crtc_state->adjusted_mode); + for (i =3D 0; i < PIPES_PER_PLANE; i++) { + pipe =3D &pstate->pipe[i]; + pipe_cfg =3D &pstate->pipe_cfg[i]; + if (!pipe_cfg->valid || !pipe->sspp) + continue; + DPU_DEBUG_PLANE(pdpu, "pipe %d is in use, validate it\n", i); + ret =3D dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, + &crtc_state->adjusted_mode, + new_plane_state); if (ret) return ret; } --=20 2.34.1 From nobody Thu Dec 18 20:22:07 2025 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC1B321767D for ; Thu, 19 Dec 2024 07:51:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594666; cv=none; b=QcgG8fiP8lXE8CJhp8AUOAb6rFjZmZ/XFqvZs4Y12K+Hs35IFO5AYDiBxKcLfEmh19rxGFyaPBJz5cjXV1DicJ2weqmylrfxrFRuRkHnwnAAXpmc2P5zb8K5HLJr62aWPqLT4u3rJZPfSCOhINx5OclcQ96OR1WK3G+HutOh6fM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594666; c=relaxed/simple; bh=tA3alNV9otTl28ZQS8OwFjLP2xaRsfRU08APLwodDys=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uHywvjtsF9cIx0Yk6H6ianmSCUGwT4/DG+m2ocl/pco8JF4MKn7hsJSQJ6ZeaB43ghQiZ3o8aH8CvkX0x7b/TerWwIfJZg7kpaMH2uncQzB2izQIkIvsPrmtF4AmGvznt2RATOGhKJkn9ODD7Kj1Xsxpp7d6vSW2CSX+V5Oynac= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=A9GniXtQ; arc=none smtp.client-ip=209.85.214.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="A9GniXtQ" Received: by mail-pl1-f182.google.com with SMTP id d9443c01a7336-21683192bf9so4900555ad.3 for ; Wed, 18 Dec 2024 23:51:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1734594664; x=1735199464; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=RgvnOTs2uY1dsly9HgOib3tl/7lDapvkf4uxsPWHol0=; b=A9GniXtQQ5Juzi9gDqXQqv2xvm8FhKhV92ac5gsLv6lxg+gp20jukqmUKk2tbzM91E Sp8aitX00cYivxWUw0Ll+stM7Q3Nq4zFK5eb8bla94v1MqCnDq2DXLymUWT0tRr3nSsF zlY3FyIxogWFboNe7YBMOrFA/YmSSHvh3E2JBYOvtz0Qplet3APlBugLshwzPpsUYctI qFs3llrMRjptn8LH5nm0yFtBvIRG4TfKDPEZ3y5upIsbfqaX48uhEgBOGVGz7mljAuxA 0baj8Iw9w5BaonkLaRTz9/ATymPEAM038djUqyEMAbVspFRliFvPerAIU04Fa1bRrBBq a0DQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734594664; x=1735199464; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RgvnOTs2uY1dsly9HgOib3tl/7lDapvkf4uxsPWHol0=; b=MmzVdYOpfsxzmaO5HIL+jQTzj9PYoJHO02no1XYJ0yTxMJDAh4w65ePKaKAhSxEcie cBuV0TNi7U4cGulYePDCM2vM/qAT+Boq9kxNBkNjb/B0IpNQIw8EZ5T5K0RVHme0NSvi /Qv9pzY6VwFXCvz/9giAzaNIguvxY5BioNjxJWahc6uOxpdyI5JWxSgwHodb1OpJbS01 VOIgiGZPIwZBpy3BFPCVMuYNbujPfUQTjHOXAeS5y8zDEEwH6eP7YTwvD4+YtP5U8W7l zNNnl9C4Uib9auN9hs04Di5dbjR+EDAP7z/hqTmhCfp39vGrplj89h/H/au63x+zTT/z obzQ== X-Forwarded-Encrypted: i=1; AJvYcCWT+9XwdsBNxkfoEAlJJ9eyPIP/kUItgG6XSJbYor7DJbPcutIDq8HZx2gpPUBWt/0jJFrrDyMPQO5lc48=@vger.kernel.org X-Gm-Message-State: AOJu0YxN2AZJQG8yn7UhWGXYzjUTyjyBf9fvkNfzXrI/Dv1y5isoEWuj hSq1Vy9+iAyK3JkBM/yfrKjkePi4W4PjR6B/kgp16mkwOXBLletdBg7zsWD7uk4= X-Gm-Gg: ASbGncuRzpzcmmoxO9WSUbI8NFwlE8o8shTVio+xsIZDNGJCaR1HVYJWnE+bISFkAEd hKfXbCsaKMeepcVHGnrrngGI+W//tkdMO+Mrb58qWos9W+Z8c/fAHgtYlh3A6TMKG02K8+D+8bC JceJig35ow2TxFUtUgEFb4UHwQG09rqEgeNTTuACv8OjmHMfBE7h+wLVKDJDiFwb5pVrFTxVgSm R4ET4RpnlsgZh7nwlE9YRTnZtOx+NP+XuripQDgF6edEApcs6AtMw== X-Google-Smtp-Source: AGHT+IGwaAxcVSn4iX1XZOIX8Wg+snyJY0Kv6ikKPptCVVAmPgXHQ4NSJbP4uqVO2uhW3137qBScNw== X-Received: by 2002:a17:902:e5c1:b0:216:5b8b:9062 with SMTP id d9443c01a7336-218d726cd69mr84265435ad.54.1734594663939; Wed, 18 Dec 2024 23:51:03 -0800 (PST) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc97432dsm6784445ad.110.2024.12.18.23.50.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2024 23:51:03 -0800 (PST) From: Jun Nie Date: Thu, 19 Dec 2024 15:49:32 +0800 Subject: [PATCH v3 14/15] drm/msm/dpu: support SSPP assignment for quad-pipe case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-14-92c7c0a228e3@linaro.org> References: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> In-Reply-To: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734594568; l=4031; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=tA3alNV9otTl28ZQS8OwFjLP2xaRsfRU08APLwodDys=; b=E7WIJ2rZG+R3RNiWLgSS7yjJEJ5MHTpRWMKhf43PADnxUFgiPrrcgzCtHR5I67K90C0yTqiER GBEgH4QJZApBXDJ6YlXZWb0DFe69Iolhya8bCW7D3hDvn2JNRgXvL07 X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Support SSPP assignment for quad-pipe case with unified method. The first 2 pipes can share a set of mixer config and enable multi-rect mode if condition is met. It is also the case for the later 2 pipes. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 67 ++++++++++++++++++---------= ---- 1 file changed, 38 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 1cd98892898a4..57ccb73c45683 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -1163,12 +1163,9 @@ static int dpu_plane_virtual_assign_resources(struct= drm_crtc *crtc, struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); struct dpu_rm_sspp_requirements reqs; struct dpu_plane_state *pstate; - struct dpu_sw_pipe *pipe; - struct dpu_sw_pipe *r_pipe; - struct dpu_sw_pipe_cfg *pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg; + struct dpu_plane *pdpu =3D to_dpu_plane(plane); const struct msm_format *fmt; - int i; + int i, num_lm, stage_id, num_stages; =20 if (plane_state->crtc) crtc_state =3D drm_atomic_get_new_crtc_state(state, @@ -1176,12 +1173,6 @@ static int dpu_plane_virtual_assign_resources(struct= drm_crtc *crtc, =20 pstate =3D to_dpu_plane_state(plane_state); =20 - /* TODO: loop below code for another pair later */ - pipe =3D &pstate->pipe[0]; - r_pipe =3D &pstate->pipe[1]; - pipe_cfg =3D &pstate->pipe_cfg[0]; - r_pipe_cfg =3D &pstate->pipe_cfg[1]; - for (i =3D 0; i < PIPES_PER_PLANE; i++) pstate->pipe[i].sspp =3D NULL; =20 @@ -1195,24 +1186,42 @@ static int dpu_plane_virtual_assign_resources(struc= t drm_crtc *crtc, =20 reqs.rot90 =3D drm_rotation_90_or_270(plane_state->rotation); =20 - pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &req= s); - if (!pipe->sspp) - return -ENODEV; - - if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, - pipe->sspp, - msm_framebuffer_format(plane_state->fb), - dpu_kms->catalog->caps->max_linewidth)) { - /* multirect is not possible, use two SSPP blocks */ - r_pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &= reqs); - if (!r_pipe->sspp) - return -ENODEV; - - pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; - - r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + num_lm =3D dpu_crtc_get_num_lm(crtc_state); + num_stages =3D (num_lm + 1) / 2; + for (stage_id =3D 0; stage_id < num_stages; stage_id++) { + for (i =3D stage_id * PIPES_PER_STAGE; i < (stage_id + 1) * PIPES_PER_ST= AGE; i++) { + struct dpu_sw_pipe *pipe =3D &pstate->pipe[i]; + struct dpu_sw_pipe *r_pipe =3D &pstate->pipe[i + 1]; + struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg[i]; + struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->pipe_cfg[i + 1]; + + if (!pipe_cfg->valid) + break; + + pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &r= eqs); + if (!pipe->sspp) + return -ENODEV; + + /* + * If current pipe is the first pipe in pipe pair, check + * multi-rect opportunity for the 2nd pipe in the pair. + * SSPP multi-rect mode cross mixer pairs is not supported. + */ + if ((i % PIPES_PER_STAGE =3D=3D 0) && + r_pipe_cfg->valid && + !dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cf= g, + pipe->sspp, + msm_framebuffer_format(plane_state->fb), + dpu_kms->catalog->caps->max_linewidth)) { + i++; + } else { + /* multirect is not possible, use two SSPP blocks */ + pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + DPU_DEBUG_PLANE(pdpu, "allocating sspp_%d for pipe %d.\n", + pipe->sspp->idx - SSPP_NONE, i); + } + } } =20 return dpu_plane_atomic_check_sspp(plane, state, crtc_state); --=20 2.34.1 From nobody Thu Dec 18 20:22:07 2025 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 192F821770F for ; Thu, 19 Dec 2024 07:51:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594672; cv=none; b=ZyaS+wHjPWyFv/KwoLrCNQDXsG6G1g2GA/v591QHTSltPxiORncrzVgpokvy+oh+4a+hEw0d5fejHkwTJK3+XkDstnaDAX5blFvRyCoWbGJlpgwJKikpS+CQzzayLky/rNpH4s0I7efSssS4HuI9L0x8tDxrkS5WRMcuFK9nAmg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734594672; c=relaxed/simple; bh=Kgvxz+JddimpExknfUGmCF8U+2CnnDWzoXq631c2AJ8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hQiv6K+NJb8aACVhiKZvAE1O2PViCfGxHjXPnGacYi25eEoJbNRCafXRyM0uxes5x5FZuoMomO86cfVmQ0xWlCN4uKboW1RLW9I9caP1yBM4FHVupz948gbOx+pbBeToF3siCEIK8WntLv9vAbcI2iXaNVcwNilocAkv0tSSsSc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=eRsGOmzI; arc=none smtp.client-ip=209.85.214.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="eRsGOmzI" Received: by mail-pl1-f182.google.com with SMTP id d9443c01a7336-2167141dfa1so4501215ad.1 for ; Wed, 18 Dec 2024 23:51:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1734594670; x=1735199470; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ncMQeFnI8FyNCTzJzx/U9WczMhrNIAA5qgalqkzfgpM=; b=eRsGOmzIz7WDLTcCu896mDwYtsgShJF2oGTErhbY2QYEofgrsgxqekQMPGa9mxZjCa NuaU3JYCgT797c3X3prW1gvs6KxCaOeoHnsjBVlf2aAh2r3cITxTDfXUGvPM3S9T1znc MTqkMVyNWYopoSaHtpV7YqymiTDrfjZ9DruPWY1cm8GRVNZ01ug4oGYY8YNMOUGWuEYL pAeKa7XoNH0A5Rk3Phq+y8kq58Tqh8amAV0jPdUXJub3qWw+VK4Fw5Q3kkN/XsEorFDI V+/MBLiPFx3qnR6TzLFVkUOcth2/rP/rBUfmnYIy1b6sW4+14q6r/rhaQ7ODEaSRY/Vd kbkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734594670; x=1735199470; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ncMQeFnI8FyNCTzJzx/U9WczMhrNIAA5qgalqkzfgpM=; b=T74mhBXKQEx1VYxi0qTlbBijLQ4MAPdB3y+h1fVnRK9FCLdUKgarp0uusTsCC4nJ4v 2a01WjZcgqOg3E/BD0GnLrd8JL2T4TdaNnR7BQ3omQHiDGrNSt6p6hk8//fzaSbWtUjP H+jyd0SVmrIheAmtlizZ6X9IRvAg4kKGx3Kt4/+FoOgaR2/cDJ2Vkf9vyP7X2qaS5S2E eDBZf5+MrdDsUoiTyp94yHTIx2QiRW55Nya84reCevQzQnNz8fkpXzX78WDEG7zykqo0 gjnd1ECeaYmjd6LexvV4Q/ei6P/vNF5K6zhRWDKcgzzn5srzd14VSW5Byt5Hb1P716Yg bayg== X-Forwarded-Encrypted: i=1; AJvYcCVExFijyV91TUxEgFsXwCWyguMWuWdLy3jPAbE5p7VXzJSiFemuUvBzKfayKFBUKd0SZ/ma8rrpOK2WjIM=@vger.kernel.org X-Gm-Message-State: AOJu0YzBUUZqX/A00F8uuDmNHIjJb5RsDxFfATs4gc5I3+2hr5G5djHi aH9Cd02Xw3w8mbpdaqxYZdB8Q4RIYlyb5B0GM01LjSh0IB/9iYpeL2tI2kZEwfY= X-Gm-Gg: ASbGncudejaeB/7LdePmJKSK4DeXpCKBjMTisA4OkUZJJATaAh/g8vICuQdbhqB1zVX ho0TucMCkckwCjwjIRFvZRLcxh2Fasm7cY6ua3B5uK+IKZ71y62UGQv+ZuBGl64BHjXRu4APDxM SBzA3feCIUkPLPJ41nOvc5K8HQc5GTylVdudWF9FtxDWJzM0OxkB8P49Zr7Jk51M/m8TC163VrE BCh1eJ5yX6q+LFww4LncaP+Q5HnLcdmE0nBkaxzUcAixsdK9GWfGQ== X-Google-Smtp-Source: AGHT+IE6wutQ9rGCjIBHFXRUP8U2cudK8bKqUGf+H0wx8eea9x5QHkaF7AyJwuwtdVhfnshpWOkZ7w== X-Received: by 2002:a17:902:da81:b0:216:59f1:c7d9 with SMTP id d9443c01a7336-219da6eabaemr34112635ad.19.1734594670471; Wed, 18 Dec 2024 23:51:10 -0800 (PST) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc97432dsm6784445ad.110.2024.12.18.23.51.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2024 23:51:10 -0800 (PST) From: Jun Nie Date: Thu, 19 Dec 2024 15:49:33 +0800 Subject: [PATCH v3 15/15] drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-15-92c7c0a228e3@linaro.org> References: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> In-Reply-To: <20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734594568; l=6569; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=Kgvxz+JddimpExknfUGmCF8U+2CnnDWzoXq631c2AJ8=; b=IVh/pEC+zDsiWrKgIH1DqGmvx8qOE4k3X8IdEM3/dTiXEa5wLm4olw4osrKyvaGNlOBhMWFJ7 KLSTqXVzqnQAaIwcDd+r75zXKTztI0vY3Zw8qAwibtxfiN5SybfAveG X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Request 4 mixers and 4 DSC for the case that both dual-DSI and DSC are enabled. We prefer to use 4 pipes for dual DSI case for it is power optimal for DSC. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 6 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 28 ++++++++++++++++++--= ---- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 3 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 +- 7 files changed, 30 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index bad75af4e50ab..3c51c199f3e05 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -200,7 +200,7 @@ static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc, struct dpu_crtc_state *crtc_state) { struct dpu_crtc_mixer *m; - u32 crcs[CRTC_DUAL_MIXERS]; + u32 crcs[CRTC_QUAD_MIXERS]; =20 int rc =3D 0; int i; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.h index d1bb3f84fe440..ce41fb364f3db 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -210,7 +210,7 @@ struct dpu_crtc_state { =20 bool bw_control; bool bw_split_vote; - struct drm_rect lm_bounds[CRTC_DUAL_MIXERS]; + struct drm_rect lm_bounds[CRTC_QUAD_MIXERS]; =20 uint64_t input_fence_timeout_ns; =20 @@ -218,10 +218,10 @@ struct dpu_crtc_state { =20 /* HW Resources reserved for the crtc */ u32 num_mixers; - struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS]; + struct dpu_crtc_mixer mixers[CRTC_QUAD_MIXERS]; =20 u32 num_ctls; - struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS]; + struct dpu_hw_ctl *hw_ctls[CRTC_QUAD_MIXERS]; =20 enum dpu_crtc_crc_source crc_source; int crc_frame_skip_count; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index 96d06db3e4be5..6e54ddeaffacd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -54,7 +54,7 @@ #define MAX_PHYS_ENCODERS_PER_VIRTUAL \ (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES) =20 -#define MAX_CHANNELS_PER_ENC 2 +#define MAX_CHANNELS_PER_ENC 4 =20 #define IDLE_SHORT_TIMEOUT 1 =20 @@ -664,15 +664,19 @@ static struct msm_display_topology dpu_encoder_get_to= pology( =20 /* Datapath topology selection * - * Dual display + * Dual display without DSC * 2 LM, 2 INTF ( Split display using 2 interfaces) * + * Dual display with DSC + * 4 LM, 2 INTF ( Split display using 2 interfaces) + * * Single display * 1 LM, 1 INTF * 2 LM, 1 INTF (stream merge to support high resolution interfaces) * * Add dspps to the reservation requirements if ctm is requested */ + if (intf_count =3D=3D 2) topology.num_lm =3D 2; else if (!dpu_kms->catalog->caps->has_3d_merge) @@ -691,10 +695,20 @@ static struct msm_display_topology dpu_encoder_get_to= pology( * 2 DSC encoders, 2 layer mixers and 1 interface * this is power optimal and can drive up to (including) 4k * screens + * But for dual display case, we prefer 4 layer mixers. Because + * the resolution is always high in the case and 4 DSCs are more + * power optimal. */ - topology.num_dsc =3D 2; - topology.num_lm =3D 2; - topology.num_intf =3D 1; + + if (intf_count =3D=3D 2) { + topology.num_dsc =3D 4; + topology.num_lm =3D 4; + topology.num_intf =3D 2; + } else { + topology.num_dsc =3D 2; + topology.num_lm =3D 2; + topology.num_intf =3D 1; + } } =20 return topology; @@ -2195,8 +2209,8 @@ static void dpu_encoder_helper_reset_mixers(struct dp= u_encoder_phys *phys_enc) struct dpu_hw_mixer_cfg mixer; int i, num_lm; struct dpu_global_state *global_state; - struct dpu_hw_blk *hw_lm[2]; - struct dpu_hw_mixer *hw_mixer[2]; + struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; + struct dpu_hw_mixer *hw_mixer[MAX_CHANNELS_PER_ENC]; struct dpu_hw_ctl *ctl =3D phys_enc->hw_ctl; =20 memset(&mixer, 0, sizeof(mixer)); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu= /drm/msm/disp/dpu1/dpu_encoder_phys.h index 63f09857025c2..d378a990cc0fb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -302,7 +302,8 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper= _get_3d_blend_mode( =20 /* Use merge_3d unless DSC MERGE topology is used */ if (phys_enc->split_role =3D=3D ENC_ROLE_SOLO && - dpu_cstate->num_mixers =3D=3D CRTC_DUAL_MIXERS && + (dpu_cstate->num_mixers =3D=3D CRTC_DUAL_MIXERS || + dpu_cstate->num_mixers =3D=3D CRTC_QUAD_MIXERS) && !dpu_encoder_use_dsc_merge(phys_enc->parent)) return BLEND_3D_H_ROW_INT; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 3ab79092a7f25..d9cc84b081b1f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -25,6 +25,7 @@ #define DPU_MAX_IMG_HEIGHT 0x3fff =20 #define CRTC_DUAL_MIXERS 2 +#define CRTC_QUAD_MIXERS 4 =20 #define MAX_XIN_COUNT 16 =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_mdss.h index 27ef0771da5d2..1fe21087a141a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -33,8 +33,8 @@ #endif =20 #define STAGES_PER_PLANE 2 -#define PIPES_PER_PLANE 2 #define PIPES_PER_STAGE 2 +#define PIPES_PER_PLANE (STAGES_PER_PLANE * STAGES_PER_PLANE) #ifndef DPU_MAX_DE_CURVES #define DPU_MAX_DE_CURVES 3 #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 57ccb73c45683..b5c1ad2a75594 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -1474,7 +1474,7 @@ static void _dpu_plane_atomic_disable(struct drm_plan= e *plane) trace_dpu_plane_disable(DRMID(plane), false, pstate->pipe[i].multirect_mode); =20 - if (pipe->sspp && i =3D=3D 1) { + if (pipe->sspp && pipe->multirect_index =3D=3D DPU_SSPP_RECT_1) { pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; =20 --=20 2.34.1