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Wed, 18 Dec 2024 15:01:23 -0800 (PST) Received: from linaro.org ([2a00:23c5:6829:901:7895:12a9:ae3b:17a1]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43656b190f3sm33291835e9.32.2024.12.18.15.01.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2024 15:01:23 -0800 (PST) From: Mike Leach To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org Cc: james.clark@linaro.org, mike.leach@linaro.org, suzuki.poulose@arm.com, alexander.shishkin@linux.intel.com Subject: [PATCH v3 2/3] coresight: tmc: Update error logging in tmc common functions Date: Wed, 18 Dec 2024 23:01:17 +0000 Message-Id: <20241218230118.999859-3-mike.leach@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241218230118.999859-1-mike.leach@linaro.org> References: <20241218230118.999859-1-mike.leach@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enhance the error logging in the tmc_wait_for_tmcready() and tmc_flush_and_stop() to print key tmc register values on error conditions to improve hardware debug information. Signed-off-by: Mike Leach --- .../hwtracing/coresight/coresight-tmc-core.c | 44 +++++++++++++++---- drivers/hwtracing/coresight/coresight-tmc.h | 2 +- 2 files changed, 37 insertions(+), 9 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index e9876252a789..dff82facada3 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -34,25 +34,39 @@ DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr"); =20 +#define TMC_WAIT_READY_FMT_STR "timeout while waiting for TMC to be Ready = [STS=3D0x%04x]\n" + int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) { struct coresight_device *csdev =3D drvdata->csdev; struct csdev_access *csa =3D &csdev->access; + u32 tmc_sts =3D 0; =20 /* Ensure formatter, unformatter and hardware fifo are empty */ - if (coresight_timeout(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) { - dev_err(&csdev->dev, - "timeout while waiting for TMC to be Ready\n"); + if (coresight_timeout_retval(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1, + &tmc_sts)) { + dev_err(&csdev->dev, TMC_WAIT_READY_FMT_STR, tmc_sts); + if (tmc_sts & TMC_STS_MEMERR) + dev_err(&csdev->dev, + "MemErr in STS reg waiting for TMC ready\n"); return -EBUSY; } return 0; } =20 -void tmc_flush_and_stop(struct tmc_drvdata *drvdata) +int tmc_flush_and_stop(struct tmc_drvdata *drvdata) { struct coresight_device *csdev =3D drvdata->csdev; struct csdev_access *csa =3D &csdev->access; - u32 ffcr; + u32 ffcr, ffsr, tmc_sts; + int rc =3D 0; + + /* note any MemErr present when stopping TMC */ + tmc_sts =3D readl_relaxed(drvdata->base + TMC_STS); + if (tmc_sts & TMC_STS_MEMERR) + dev_err(&csdev->dev, + "MemErr detected before Manual Flush; STS[0x%02x]\n", + tmc_sts); =20 ffcr =3D readl_relaxed(drvdata->base + TMC_FFCR); ffcr |=3D TMC_FFCR_STOP_ON_FLUSH; @@ -60,12 +74,26 @@ void tmc_flush_and_stop(struct tmc_drvdata *drvdata) ffcr |=3D BIT(TMC_FFCR_FLUSHMAN_BIT); writel_relaxed(ffcr, drvdata->base + TMC_FFCR); /* Ensure flush completes */ - if (coresight_timeout(csa, TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) { + if (coresight_timeout_retval(csa, TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0, + &ffcr)) { + ffsr =3D readl_relaxed(drvdata->base + TMC_FFSR); + tmc_sts =3D readl_relaxed(drvdata->base + TMC_STS); dev_err(&csdev->dev, - "timeout while waiting for completion of Manual Flush\n"); + "timeout while waiting for completion of Manual Flush\n"); + dev_err(&csdev->dev, + "regs: FFCR[0x%02x] FFSR[0x%02x] STS[0x%02x]\n", + ffcr, ffsr, tmc_sts); + if (tmc_sts & TMC_STS_MEMERR) + dev_err(&csdev->dev, + "MemErr in STS reg waiting for flush complete\n"); + rc =3D -EBUSY; } =20 - tmc_wait_for_tmcready(drvdata); + if (tmc_wait_for_tmcready(drvdata)) { + dev_err(&csdev->dev, "TMC ready error after Manual flush\n"); + rc =3D -EBUSY; + } + return rc; } =20 void tmc_enable_hw(struct tmc_drvdata *drvdata) diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index 2671926be62a..34513f07c3aa 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -259,7 +259,7 @@ struct tmc_sg_table { =20 /* Generic functions */ int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); -void tmc_flush_and_stop(struct tmc_drvdata *drvdata); +int tmc_flush_and_stop(struct tmc_drvdata *drvdata); void tmc_enable_hw(struct tmc_drvdata *drvdata); void tmc_disable_hw(struct tmc_drvdata *drvdata); u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata); --=20 2.25.1